From: Greg Kroah-Hartman Date: Mon, 10 Mar 2025 17:03:24 +0000 (+0100) Subject: drop riscv patch from 5.4 and 5.10, breaks the build X-Git-Tag: v5.4.291~16 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=b2a9e9f6d2bfc81fc5678c9852a69cb6546058f5;p=thirdparty%2Fkernel%2Fstable-queue.git drop riscv patch from 5.4 and 5.10, breaks the build --- diff --git a/queue-5.10/revert-riscv-set-more-data-to-cacheinfo.patch b/queue-5.10/revert-riscv-set-more-data-to-cacheinfo.patch deleted file mode 100644 index 90afc7a8ed..0000000000 --- a/queue-5.10/revert-riscv-set-more-data-to-cacheinfo.patch +++ /dev/null @@ -1,129 +0,0 @@ -From bbd414673ff6cc7e821cf05ee44878b8650ea259 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Wed, 8 Mar 2023 14:47:34 +0800 -Subject: Revert "riscv: Set more data to cacheinfo" - -From: Song Shuai - -[ Upstream commit 6a24915145c922b79d3ac78f681137a4c14a6d6b ] - -This reverts commit baf7cbd94b5688f167443a2cc3dcea3300132099. - -There are some duplicate cache attributes populations executed -in both ci_leaf_init() and later cache_setup_properties(). - -Revert the commit baf7cbd94b56 ("riscv: Set more data to cacheinfo") -to setup only the level and type attributes at this early place. - -Signed-off-by: Song Shuai -Acked-by: Sudeep Holla -Acked-by: Conor Dooley -Link: https://lore.kernel.org/r/20230308064734.512457-1-suagrfillet@gmail.com -Signed-off-by: Palmer Dabbelt -Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties") -Signed-off-by: Sasha Levin ---- - arch/riscv/kernel/cacheinfo.c | 66 ++++++++--------------------------- - 1 file changed, 15 insertions(+), 51 deletions(-) - -diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c -index 90deabfe63eaa..56141a65c7348 100644 ---- a/arch/riscv/kernel/cacheinfo.c -+++ b/arch/riscv/kernel/cacheinfo.c -@@ -64,53 +64,12 @@ uintptr_t get_cache_geometry(u32 level, enum cache_type type) - 0; - } - --static void ci_leaf_init(struct cacheinfo *this_leaf, enum cache_type type, -- unsigned int level, unsigned int size, -- unsigned int sets, unsigned int line_size) -+static void ci_leaf_init(struct cacheinfo *this_leaf, -+ struct device_node *node, -+ enum cache_type type, unsigned int level) - { - this_leaf->level = level; - this_leaf->type = type; -- this_leaf->size = size; -- this_leaf->number_of_sets = sets; -- this_leaf->coherency_line_size = line_size; -- -- /* -- * If the cache is fully associative, there is no need to -- * check the other properties. -- */ -- if (sets == 1) -- return; -- -- /* -- * Set the ways number for n-ways associative, make sure -- * all properties are big than zero. -- */ -- if (sets > 0 && size > 0 && line_size > 0) -- this_leaf->ways_of_associativity = (size / sets) / line_size; --} -- --static void fill_cacheinfo(struct cacheinfo **this_leaf, -- struct device_node *node, unsigned int level) --{ -- unsigned int size, sets, line_size; -- -- if (!of_property_read_u32(node, "cache-size", &size) && -- !of_property_read_u32(node, "cache-block-size", &line_size) && -- !of_property_read_u32(node, "cache-sets", &sets)) { -- ci_leaf_init((*this_leaf)++, CACHE_TYPE_UNIFIED, level, size, sets, line_size); -- } -- -- if (!of_property_read_u32(node, "i-cache-size", &size) && -- !of_property_read_u32(node, "i-cache-sets", &sets) && -- !of_property_read_u32(node, "i-cache-block-size", &line_size)) { -- ci_leaf_init((*this_leaf)++, CACHE_TYPE_INST, level, size, sets, line_size); -- } -- -- if (!of_property_read_u32(node, "d-cache-size", &size) && -- !of_property_read_u32(node, "d-cache-sets", &sets) && -- !of_property_read_u32(node, "d-cache-block-size", &line_size)) { -- ci_leaf_init((*this_leaf)++, CACHE_TYPE_DATA, level, size, sets, line_size); -- } - } - - int init_cache_level(unsigned int cpu) -@@ -163,24 +122,29 @@ int populate_cache_leaves(unsigned int cpu) - struct device_node *prev = NULL; - int levels = 1, level = 1; - -- /* Level 1 caches in cpu node */ -- fill_cacheinfo(&this_leaf, np, level); -+ if (of_property_read_bool(np, "cache-size")) -+ ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level); -+ if (of_property_read_bool(np, "i-cache-size")) -+ ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level); -+ if (of_property_read_bool(np, "d-cache-size")) -+ ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level); - -- /* Next level caches in cache nodes */ - prev = np; - while ((np = of_find_next_cache_node(np))) { - of_node_put(prev); - prev = np; -- - if (!of_device_is_compatible(np, "cache")) - break; - if (of_property_read_u32(np, "cache-level", &level)) - break; - if (level <= levels) - break; -- -- fill_cacheinfo(&this_leaf, np, level); -- -+ if (of_property_read_bool(np, "cache-size")) -+ ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level); -+ if (of_property_read_bool(np, "i-cache-size")) -+ ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level); -+ if (of_property_read_bool(np, "d-cache-size")) -+ ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level); - levels = level; - } - of_node_put(np); --- -2.39.5 - diff --git a/queue-5.10/riscv-cacheinfo-initialize-cacheinfo-s-level-and-typ.patch b/queue-5.10/riscv-cacheinfo-initialize-cacheinfo-s-level-and-typ.patch deleted file mode 100644 index 50c4cb5fd3..0000000000 --- a/queue-5.10/riscv-cacheinfo-initialize-cacheinfo-s-level-and-typ.patch +++ /dev/null @@ -1,74 +0,0 @@ -From c7ffa1c4b7defeca1ed7aa50907abd22e263a484 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 17 Jun 2024 21:14:24 +0800 -Subject: riscv: cacheinfo: initialize cacheinfo's level and type from ACPI - PPTT - -From: Yunhui Cui - -[ Upstream commit 604f32ea6909b0ebb8ab0bf1ab7dc66ee3dc8955 ] - -Before cacheinfo can be built correctly, we need to initialize level -and type. Since RISC-V currently does not have a register group that -describes cache-related attributes like ARM64, we cannot obtain them -directly, so now we obtain cache leaves from the ACPI PPTT table -(acpi_get_cache_info()) and set the cache type through split_levels. - -Suggested-by: Jeremy Linton -Suggested-by: Sudeep Holla -Reviewed-by: Conor Dooley -Reviewed-by: Sunil V L -Reviewed-by: Jeremy Linton -Reviewed-by: Sudeep Holla -Signed-off-by: Yunhui Cui -Link: https://lore.kernel.org/r/20240617131425.7526-2-cuiyunhui@bytedance.com -Signed-off-by: Palmer Dabbelt -Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties") -Signed-off-by: Sasha Levin ---- - arch/riscv/kernel/cacheinfo.c | 22 ++++++++++++++++++++++ - 1 file changed, 22 insertions(+) - -diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c -index 7c6dff3dac2d6..8290cced2e62e 100644 ---- a/arch/riscv/kernel/cacheinfo.c -+++ b/arch/riscv/kernel/cacheinfo.c -@@ -3,6 +3,7 @@ - * Copyright (C) 2017 SiFive - */ - -+#include - #include - #include - #include -@@ -121,6 +122,27 @@ int populate_cache_leaves(unsigned int cpu) - struct device_node *prev = NULL; - int levels = 1, level = 1; - -+ if (!acpi_disabled) { -+ int ret, fw_levels, split_levels; -+ -+ ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels); -+ if (ret) -+ return ret; -+ -+ BUG_ON((split_levels > fw_levels) || -+ (split_levels + fw_levels > this_cpu_ci->num_leaves)); -+ -+ for (; level <= this_cpu_ci->num_levels; level++) { -+ if (level <= split_levels) { -+ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); -+ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); -+ } else { -+ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); -+ } -+ } -+ return 0; -+ } -+ - if (of_property_read_bool(np, "cache-size")) - ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); - if (of_property_read_bool(np, "i-cache-size")) --- -2.39.5 - diff --git a/queue-5.10/riscv-cacheinfo-remove-the-useless-input-parameter-n.patch b/queue-5.10/riscv-cacheinfo-remove-the-useless-input-parameter-n.patch deleted file mode 100644 index fdb02e6196..0000000000 --- a/queue-5.10/riscv-cacheinfo-remove-the-useless-input-parameter-n.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 2948d79f6ffa783c397aa87f33c6f28de1eebd9c Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 17 Jun 2024 21:14:23 +0800 -Subject: riscv: cacheinfo: remove the useless input parameter (node) of - ci_leaf_init() - -From: Yunhui Cui - -[ Upstream commit ee3fab10cb1566562aa683f319066eaeecccf918 ] - -ci_leaf_init() is a declared static function. The implementation of the -function body and the caller do not use the parameter (struct device_node -*node) input parameter, so remove it. - -Fixes: 6a24915145c9 ("Revert "riscv: Set more data to cacheinfo"") -Signed-off-by: Yunhui Cui -Reviewed-by: Jeremy Linton -Reviewed-by: Sudeep Holla -Link: https://lore.kernel.org/r/20240617131425.7526-1-cuiyunhui@bytedance.com -Signed-off-by: Palmer Dabbelt -Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties") -Signed-off-by: Sasha Levin ---- - arch/riscv/kernel/cacheinfo.c | 13 ++++++------- - 1 file changed, 6 insertions(+), 7 deletions(-) - -diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c -index 56141a65c7348..7c6dff3dac2d6 100644 ---- a/arch/riscv/kernel/cacheinfo.c -+++ b/arch/riscv/kernel/cacheinfo.c -@@ -65,7 +65,6 @@ uintptr_t get_cache_geometry(u32 level, enum cache_type type) - } - - static void ci_leaf_init(struct cacheinfo *this_leaf, -- struct device_node *node, - enum cache_type type, unsigned int level) - { - this_leaf->level = level; -@@ -123,11 +122,11 @@ int populate_cache_leaves(unsigned int cpu) - int levels = 1, level = 1; - - if (of_property_read_bool(np, "cache-size")) -- ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level); -+ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); - if (of_property_read_bool(np, "i-cache-size")) -- ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level); -+ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); - if (of_property_read_bool(np, "d-cache-size")) -- ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level); -+ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); - - prev = np; - while ((np = of_find_next_cache_node(np))) { -@@ -140,11 +139,11 @@ int populate_cache_leaves(unsigned int cpu) - if (level <= levels) - break; - if (of_property_read_bool(np, "cache-size")) -- ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level); -+ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); - if (of_property_read_bool(np, "i-cache-size")) -- ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level); -+ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); - if (of_property_read_bool(np, "d-cache-size")) -- ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level); -+ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); - levels = level; - } - of_node_put(np); --- -2.39.5 - diff --git a/queue-5.10/riscv-cacheinfo-use-of_property_present-for-non-bool.patch b/queue-5.10/riscv-cacheinfo-use-of_property_present-for-non-bool.patch deleted file mode 100644 index 3645e42c6c..0000000000 --- a/queue-5.10/riscv-cacheinfo-use-of_property_present-for-non-bool.patch +++ /dev/null @@ -1,65 +0,0 @@ -From d91dfd65707ad051bc5666c3658859aa587c86d1 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 4 Nov 2024 13:03:13 -0600 -Subject: riscv: cacheinfo: Use of_property_present() for non-boolean - properties -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -From: Rob Herring - -[ Upstream commit fb8179ce2996bffaa36a04e2b6262843b01b7565 ] - -The use of of_property_read_bool() for non-boolean properties is -deprecated in favor of of_property_present() when testing for property -presence. - -Signed-off-by: Rob Herring (Arm) -Reviewed-by: Clément Léger -Cc: stable@vger.kernel.org -Fixes: 76d2a0493a17 ("RISC-V: Init and Halt Code") -Link: https://lore.kernel.org/r/20241104190314.270095-1-robh@kernel.org -Signed-off-by: Palmer Dabbelt -Signed-off-by: Sasha Levin ---- - arch/riscv/kernel/cacheinfo.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c -index c196d1a0b8d98..f42c0886484a4 100644 ---- a/arch/riscv/kernel/cacheinfo.c -+++ b/arch/riscv/kernel/cacheinfo.c -@@ -146,11 +146,11 @@ int populate_cache_leaves(unsigned int cpu) - if (!np) - return -ENOENT; - -- if (of_property_read_bool(np, "cache-size")) -+ if (of_property_present(np, "cache-size")) - ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); -- if (of_property_read_bool(np, "i-cache-size")) -+ if (of_property_present(np, "i-cache-size")) - ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); -- if (of_property_read_bool(np, "d-cache-size")) -+ if (of_property_present(np, "d-cache-size")) - ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); - - prev = np; -@@ -163,11 +163,11 @@ int populate_cache_leaves(unsigned int cpu) - break; - if (level <= levels) - break; -- if (of_property_read_bool(np, "cache-size")) -+ if (of_property_present(np, "cache-size")) - ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); -- if (of_property_read_bool(np, "i-cache-size")) -+ if (of_property_present(np, "i-cache-size")) - ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); -- if (of_property_read_bool(np, "d-cache-size")) -+ if (of_property_present(np, "d-cache-size")) - ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); - levels = level; - } --- -2.39.5 - diff --git a/queue-5.10/riscv-prevent-a-bad-reference-count-on-cpu-nodes.patch b/queue-5.10/riscv-prevent-a-bad-reference-count-on-cpu-nodes.patch deleted file mode 100644 index 7d0cf4de04..0000000000 --- a/queue-5.10/riscv-prevent-a-bad-reference-count-on-cpu-nodes.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 6b369a3c46963b05c18e2ef44f3407561169d48c Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Fri, 13 Sep 2024 10:00:52 +0200 -Subject: riscv: Prevent a bad reference count on CPU nodes -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -From: Miquel Sabaté Solà - -[ Upstream commit 37233169a6ea912020c572f870075a63293b786a ] - -When populating cache leaves we previously fetched the CPU device node -at the very beginning. But when ACPI is enabled we go through a -specific branch which returns early and does not call 'of_node_put' for -the node that was acquired. - -Since we are not using a CPU device node for the ACPI code anyways, we -can simply move the initialization of it just passed the ACPI block, and -we are guaranteed to have an 'of_node_put' call for the acquired node. -This prevents a bad reference count of the CPU device node. - -Moreover, the previous function did not check for errors when acquiring -the device node, so a return -ENOENT has been added for that case. - -Signed-off-by: Miquel Sabaté Solà -Reviewed-by: Sudeep Holla -Reviewed-by: Sunil V L -Reviewed-by: Alexandre Ghiti -Fixes: 604f32ea6909 ("riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT") -Cc: stable@vger.kernel.org -Link: https://lore.kernel.org/r/20240913080053.36636-1-mikisabate@gmail.com -Signed-off-by: Palmer Dabbelt -Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties") -Signed-off-by: Sasha Levin ---- - arch/riscv/kernel/cacheinfo.c | 7 +++++-- - 1 file changed, 5 insertions(+), 2 deletions(-) - -diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c -index 8290cced2e62e..c196d1a0b8d98 100644 ---- a/arch/riscv/kernel/cacheinfo.c -+++ b/arch/riscv/kernel/cacheinfo.c -@@ -118,8 +118,7 @@ int populate_cache_leaves(unsigned int cpu) - { - struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); - struct cacheinfo *this_leaf = this_cpu_ci->info_list; -- struct device_node *np = of_cpu_device_node_get(cpu); -- struct device_node *prev = NULL; -+ struct device_node *np, *prev; - int levels = 1, level = 1; - - if (!acpi_disabled) { -@@ -143,6 +142,10 @@ int populate_cache_leaves(unsigned int cpu) - return 0; - } - -+ np = of_cpu_device_node_get(cpu); -+ if (!np) -+ return -ENOENT; -+ - if (of_property_read_bool(np, "cache-size")) - ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); - if (of_property_read_bool(np, "i-cache-size")) --- -2.39.5 - diff --git a/queue-5.10/series b/queue-5.10/series index 58bf5ffa3e..95f8b38044 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -394,11 +394,6 @@ acct-perform-last-write-from-workqueue.patch smb-client-add-check-for-next_buffer-in-receive_encr.patch drm-amdgpu-check-extended-configuration-space-regist.patch drm-amdgpu-disable-bar-resize-on-dell-g5-se.patch -revert-riscv-set-more-data-to-cacheinfo.patch -riscv-cacheinfo-remove-the-useless-input-parameter-n.patch -riscv-cacheinfo-initialize-cacheinfo-s-level-and-typ.patch -riscv-prevent-a-bad-reference-count-on-cpu-nodes.patch -riscv-cacheinfo-use-of_property_present-for-non-bool.patch efi-don-t-map-the-entire-mokvar-table-to-determine-i.patch revert-of-reserved-memory-fix-using-wrong-number-of-cells-to-get-property-alignment.patch hid-appleir-fix-potential-null-dereference-at-raw-event-handle.patch diff --git a/queue-5.4/revert-riscv-set-more-data-to-cacheinfo.patch b/queue-5.4/revert-riscv-set-more-data-to-cacheinfo.patch deleted file mode 100644 index 0a8ed35fce..0000000000 --- a/queue-5.4/revert-riscv-set-more-data-to-cacheinfo.patch +++ /dev/null @@ -1,129 +0,0 @@ -From 8b9defccfcd6bc7363f18a104d22c2db65a38d75 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Wed, 8 Mar 2023 14:47:34 +0800 -Subject: Revert "riscv: Set more data to cacheinfo" - -From: Song Shuai - -[ Upstream commit 6a24915145c922b79d3ac78f681137a4c14a6d6b ] - -This reverts commit baf7cbd94b5688f167443a2cc3dcea3300132099. - -There are some duplicate cache attributes populations executed -in both ci_leaf_init() and later cache_setup_properties(). - -Revert the commit baf7cbd94b56 ("riscv: Set more data to cacheinfo") -to setup only the level and type attributes at this early place. - -Signed-off-by: Song Shuai -Acked-by: Sudeep Holla -Acked-by: Conor Dooley -Link: https://lore.kernel.org/r/20230308064734.512457-1-suagrfillet@gmail.com -Signed-off-by: Palmer Dabbelt -Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties") -Signed-off-by: Sasha Levin ---- - arch/riscv/kernel/cacheinfo.c | 66 ++++++++--------------------------- - 1 file changed, 15 insertions(+), 51 deletions(-) - -diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c -index 09892077ae087..31d8f35c4f077 100644 ---- a/arch/riscv/kernel/cacheinfo.c -+++ b/arch/riscv/kernel/cacheinfo.c -@@ -55,53 +55,12 @@ uintptr_t get_cache_geometry(u32 level, enum cache_type type) - 0; - } - --static void ci_leaf_init(struct cacheinfo *this_leaf, enum cache_type type, -- unsigned int level, unsigned int size, -- unsigned int sets, unsigned int line_size) -+static void ci_leaf_init(struct cacheinfo *this_leaf, -+ struct device_node *node, -+ enum cache_type type, unsigned int level) - { - this_leaf->level = level; - this_leaf->type = type; -- this_leaf->size = size; -- this_leaf->number_of_sets = sets; -- this_leaf->coherency_line_size = line_size; -- -- /* -- * If the cache is fully associative, there is no need to -- * check the other properties. -- */ -- if (sets == 1) -- return; -- -- /* -- * Set the ways number for n-ways associative, make sure -- * all properties are big than zero. -- */ -- if (sets > 0 && size > 0 && line_size > 0) -- this_leaf->ways_of_associativity = (size / sets) / line_size; --} -- --static void fill_cacheinfo(struct cacheinfo **this_leaf, -- struct device_node *node, unsigned int level) --{ -- unsigned int size, sets, line_size; -- -- if (!of_property_read_u32(node, "cache-size", &size) && -- !of_property_read_u32(node, "cache-block-size", &line_size) && -- !of_property_read_u32(node, "cache-sets", &sets)) { -- ci_leaf_init((*this_leaf)++, CACHE_TYPE_UNIFIED, level, size, sets, line_size); -- } -- -- if (!of_property_read_u32(node, "i-cache-size", &size) && -- !of_property_read_u32(node, "i-cache-sets", &sets) && -- !of_property_read_u32(node, "i-cache-block-size", &line_size)) { -- ci_leaf_init((*this_leaf)++, CACHE_TYPE_INST, level, size, sets, line_size); -- } -- -- if (!of_property_read_u32(node, "d-cache-size", &size) && -- !of_property_read_u32(node, "d-cache-sets", &sets) && -- !of_property_read_u32(node, "d-cache-block-size", &line_size)) { -- ci_leaf_init((*this_leaf)++, CACHE_TYPE_DATA, level, size, sets, line_size); -- } - } - - int init_cache_level(unsigned int cpu) -@@ -154,24 +113,29 @@ int populate_cache_leaves(unsigned int cpu) - struct device_node *prev = NULL; - int levels = 1, level = 1; - -- /* Level 1 caches in cpu node */ -- fill_cacheinfo(&this_leaf, np, level); -+ if (of_property_read_bool(np, "cache-size")) -+ ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level); -+ if (of_property_read_bool(np, "i-cache-size")) -+ ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level); -+ if (of_property_read_bool(np, "d-cache-size")) -+ ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level); - -- /* Next level caches in cache nodes */ - prev = np; - while ((np = of_find_next_cache_node(np))) { - of_node_put(prev); - prev = np; -- - if (!of_device_is_compatible(np, "cache")) - break; - if (of_property_read_u32(np, "cache-level", &level)) - break; - if (level <= levels) - break; -- -- fill_cacheinfo(&this_leaf, np, level); -- -+ if (of_property_read_bool(np, "cache-size")) -+ ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level); -+ if (of_property_read_bool(np, "i-cache-size")) -+ ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level); -+ if (of_property_read_bool(np, "d-cache-size")) -+ ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level); - levels = level; - } - of_node_put(np); --- -2.39.5 - diff --git a/queue-5.4/riscv-add-cache-information-in-aux-vector.patch b/queue-5.4/riscv-add-cache-information-in-aux-vector.patch deleted file mode 100644 index 427fdc4afb..0000000000 --- a/queue-5.4/riscv-add-cache-information-in-aux-vector.patch +++ /dev/null @@ -1,176 +0,0 @@ -From 2765d9652afac0a32f530d242038dfcb971dbb99 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 31 Aug 2020 15:33:50 +0800 -Subject: riscv: Add cache information in AUX vector - -From: Zong Li - -[ Upstream commit 38f5bd23deae24c8fa67a2c574b6d43df27a8aa8 ] - -There are no standard CSR registers to provide cache information, the -way for RISC-V is to get this information from DT. Currently, AT_L1I_X, -AT_L1D_X and AT_L2_X are present in glibc header, and sysconf syscall -could use them to get information of cache through AUX vector. - -The result of 'getconf -a' as follows: -LEVEL1_ICACHE_SIZE 32768 -LEVEL1_ICACHE_ASSOC 8 -LEVEL1_ICACHE_LINESIZE 64 -LEVEL1_DCACHE_SIZE 32768 -LEVEL1_DCACHE_ASSOC 8 -LEVEL1_DCACHE_LINESIZE 64 -LEVEL2_CACHE_SIZE 2097152 -LEVEL2_CACHE_ASSOC 32 -LEVEL2_CACHE_LINESIZE 64 - -Signed-off-by: Zong Li -Reviewed-by: Palmer Dabbelt -Reviewed-by: Pekka Enberg -Signed-off-by: Palmer Dabbelt -Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties") -Signed-off-by: Sasha Levin ---- - arch/riscv/include/asm/cacheinfo.h | 5 +++++ - arch/riscv/include/asm/elf.h | 13 +++++++++++ - arch/riscv/include/uapi/asm/auxvec.h | 23 +++++++++++++++++++- - arch/riscv/kernel/cacheinfo.c | 32 +++++++++++++++++++++++++++- - 4 files changed, 71 insertions(+), 2 deletions(-) - -diff --git a/arch/riscv/include/asm/cacheinfo.h b/arch/riscv/include/asm/cacheinfo.h -index 5d9662e9aba85..d1a365215ec00 100644 ---- a/arch/riscv/include/asm/cacheinfo.h -+++ b/arch/riscv/include/asm/cacheinfo.h -@@ -1,4 +1,7 @@ - /* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (C) 2020 SiFive -+ */ - - #ifndef _ASM_RISCV_CACHEINFO_H - #define _ASM_RISCV_CACHEINFO_H -@@ -11,5 +14,7 @@ struct riscv_cacheinfo_ops { - }; - - void riscv_set_cacheinfo_ops(struct riscv_cacheinfo_ops *ops); -+uintptr_t get_cache_size(u32 level, enum cache_type type); -+uintptr_t get_cache_geometry(u32 level, enum cache_type type); - - #endif /* _ASM_RISCV_CACHEINFO_H */ -diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h -index ef04084bf0dee..4031cce8dd734 100644 ---- a/arch/riscv/include/asm/elf.h -+++ b/arch/riscv/include/asm/elf.h -@@ -11,6 +11,7 @@ - #include - #include - #include -+#include - - /* - * These are used to set parameters in the core dumps. -@@ -60,6 +61,18 @@ extern unsigned long elf_hwcap; - do { \ - NEW_AUX_ENT(AT_SYSINFO_EHDR, \ - (elf_addr_t)current->mm->context.vdso); \ -+ NEW_AUX_ENT(AT_L1I_CACHESIZE, \ -+ get_cache_size(1, CACHE_TYPE_INST)); \ -+ NEW_AUX_ENT(AT_L1I_CACHEGEOMETRY, \ -+ get_cache_geometry(1, CACHE_TYPE_INST)); \ -+ NEW_AUX_ENT(AT_L1D_CACHESIZE, \ -+ get_cache_size(1, CACHE_TYPE_DATA)); \ -+ NEW_AUX_ENT(AT_L1D_CACHEGEOMETRY, \ -+ get_cache_geometry(1, CACHE_TYPE_DATA)); \ -+ NEW_AUX_ENT(AT_L2_CACHESIZE, \ -+ get_cache_size(2, CACHE_TYPE_UNIFIED)); \ -+ NEW_AUX_ENT(AT_L2_CACHEGEOMETRY, \ -+ get_cache_geometry(2, CACHE_TYPE_UNIFIED)); \ - } while (0) - - -diff --git a/arch/riscv/include/uapi/asm/auxvec.h b/arch/riscv/include/uapi/asm/auxvec.h -index 22e0ae8884061..32c73ba1d5313 100644 ---- a/arch/riscv/include/uapi/asm/auxvec.h -+++ b/arch/riscv/include/uapi/asm/auxvec.h -@@ -10,7 +10,28 @@ - /* vDSO location */ - #define AT_SYSINFO_EHDR 33 - -+/* -+ * The set of entries below represent more extensive information -+ * about the caches, in the form of two entry per cache type, -+ * one entry containing the cache size in bytes, and the other -+ * containing the cache line size in bytes in the bottom 16 bits -+ * and the cache associativity in the next 16 bits. -+ * -+ * The associativity is such that if N is the 16-bit value, the -+ * cache is N way set associative. A value if 0xffff means fully -+ * associative, a value of 1 means directly mapped. -+ * -+ * For all these fields, a value of 0 means that the information -+ * is not known. -+ */ -+#define AT_L1I_CACHESIZE 40 -+#define AT_L1I_CACHEGEOMETRY 41 -+#define AT_L1D_CACHESIZE 42 -+#define AT_L1D_CACHEGEOMETRY 43 -+#define AT_L2_CACHESIZE 44 -+#define AT_L2_CACHEGEOMETRY 45 -+ - /* entries in ARCH_DLINFO */ --#define AT_VECTOR_SIZE_ARCH 1 -+#define AT_VECTOR_SIZE_ARCH 7 - - #endif /* _UAPI_ASM_RISCV_AUXVEC_H */ -diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c -index 8cd8224f47ee1..09892077ae087 100644 ---- a/arch/riscv/kernel/cacheinfo.c -+++ b/arch/riscv/kernel/cacheinfo.c -@@ -3,7 +3,6 @@ - * Copyright (C) 2017 SiFive - */ - --#include - #include - #include - #include -@@ -25,6 +24,37 @@ cache_get_priv_group(struct cacheinfo *this_leaf) - return NULL; - } - -+static struct cacheinfo *get_cacheinfo(u32 level, enum cache_type type) -+{ -+ struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(smp_processor_id()); -+ struct cacheinfo *this_leaf; -+ int index; -+ -+ for (index = 0; index < this_cpu_ci->num_leaves; index++) { -+ this_leaf = this_cpu_ci->info_list + index; -+ if (this_leaf->level == level && this_leaf->type == type) -+ return this_leaf; -+ } -+ -+ return NULL; -+} -+ -+uintptr_t get_cache_size(u32 level, enum cache_type type) -+{ -+ struct cacheinfo *this_leaf = get_cacheinfo(level, type); -+ -+ return this_leaf ? this_leaf->size : 0; -+} -+ -+uintptr_t get_cache_geometry(u32 level, enum cache_type type) -+{ -+ struct cacheinfo *this_leaf = get_cacheinfo(level, type); -+ -+ return this_leaf ? (this_leaf->ways_of_associativity << 16 | -+ this_leaf->coherency_line_size) : -+ 0; -+} -+ - static void ci_leaf_init(struct cacheinfo *this_leaf, enum cache_type type, - unsigned int level, unsigned int size, - unsigned int sets, unsigned int line_size) --- -2.39.5 - diff --git a/queue-5.4/riscv-cacheinfo-implement-cache_get_priv_group-with-.patch b/queue-5.4/riscv-cacheinfo-implement-cache_get_priv_group-with-.patch deleted file mode 100644 index 9135462850..0000000000 --- a/queue-5.4/riscv-cacheinfo-implement-cache_get_priv_group-with-.patch +++ /dev/null @@ -1,80 +0,0 @@ -From df149035c335d53ff1d1193c7407784f1cd91a30 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Thu, 20 Feb 2020 10:45:18 +0530 -Subject: riscv: cacheinfo: Implement cache_get_priv_group with a generic ops - structure - -From: Yash Shah - -[ Upstream commit 087958a17658dcd92cdc9292e6ce4319a25198fb ] - -Implement cache_get_priv_group() that will make use of a generic ops -structure to return a private attribute group for custom cache info. - -Using riscv_set_cacheinfo_ops() users can hook their own custom function -to return the private attribute group for cacheinfo. In future we can -add more ops to this generic ops structure for SOC specific cacheinfo. - -Signed-off-by: Yash Shah -Reviewed-by: Anup Patel -Signed-off-by: Palmer Dabbelt -Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties") -Signed-off-by: Sasha Levin ---- - arch/riscv/include/asm/cacheinfo.h | 15 +++++++++++++++ - arch/riscv/kernel/cacheinfo.c | 17 +++++++++++++++++ - 2 files changed, 32 insertions(+) - create mode 100644 arch/riscv/include/asm/cacheinfo.h - -diff --git a/arch/riscv/include/asm/cacheinfo.h b/arch/riscv/include/asm/cacheinfo.h -new file mode 100644 -index 0000000000000..5d9662e9aba85 ---- /dev/null -+++ b/arch/riscv/include/asm/cacheinfo.h -@@ -0,0 +1,15 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+ -+#ifndef _ASM_RISCV_CACHEINFO_H -+#define _ASM_RISCV_CACHEINFO_H -+ -+#include -+ -+struct riscv_cacheinfo_ops { -+ const struct attribute_group * (*get_priv_group)(struct cacheinfo -+ *this_leaf); -+}; -+ -+void riscv_set_cacheinfo_ops(struct riscv_cacheinfo_ops *ops); -+ -+#endif /* _ASM_RISCV_CACHEINFO_H */ -diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c -index d930bd073b7b2..21dadeba06753 100644 ---- a/arch/riscv/kernel/cacheinfo.c -+++ b/arch/riscv/kernel/cacheinfo.c -@@ -7,6 +7,23 @@ - #include - #include - #include -+#include -+ -+static struct riscv_cacheinfo_ops *rv_cache_ops; -+ -+void riscv_set_cacheinfo_ops(struct riscv_cacheinfo_ops *ops) -+{ -+ rv_cache_ops = ops; -+} -+EXPORT_SYMBOL_GPL(riscv_set_cacheinfo_ops); -+ -+const struct attribute_group * -+cache_get_priv_group(struct cacheinfo *this_leaf) -+{ -+ if (rv_cache_ops && rv_cache_ops->get_priv_group) -+ return rv_cache_ops->get_priv_group(this_leaf); -+ return NULL; -+} - - static void ci_leaf_init(struct cacheinfo *this_leaf, - struct device_node *node, --- -2.39.5 - diff --git a/queue-5.4/riscv-cacheinfo-initialize-cacheinfo-s-level-and-typ.patch b/queue-5.4/riscv-cacheinfo-initialize-cacheinfo-s-level-and-typ.patch deleted file mode 100644 index b641dabcc1..0000000000 --- a/queue-5.4/riscv-cacheinfo-initialize-cacheinfo-s-level-and-typ.patch +++ /dev/null @@ -1,74 +0,0 @@ -From c99eb453dd4dc4b7f1f1976bcaac31b1e48cf91e Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 17 Jun 2024 21:14:24 +0800 -Subject: riscv: cacheinfo: initialize cacheinfo's level and type from ACPI - PPTT - -From: Yunhui Cui - -[ Upstream commit 604f32ea6909b0ebb8ab0bf1ab7dc66ee3dc8955 ] - -Before cacheinfo can be built correctly, we need to initialize level -and type. Since RISC-V currently does not have a register group that -describes cache-related attributes like ARM64, we cannot obtain them -directly, so now we obtain cache leaves from the ACPI PPTT table -(acpi_get_cache_info()) and set the cache type through split_levels. - -Suggested-by: Jeremy Linton -Suggested-by: Sudeep Holla -Reviewed-by: Conor Dooley -Reviewed-by: Sunil V L -Reviewed-by: Jeremy Linton -Reviewed-by: Sudeep Holla -Signed-off-by: Yunhui Cui -Link: https://lore.kernel.org/r/20240617131425.7526-2-cuiyunhui@bytedance.com -Signed-off-by: Palmer Dabbelt -Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties") -Signed-off-by: Sasha Levin ---- - arch/riscv/kernel/cacheinfo.c | 22 ++++++++++++++++++++++ - 1 file changed, 22 insertions(+) - -diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c -index 1d173fdbf4632..4464174836efc 100644 ---- a/arch/riscv/kernel/cacheinfo.c -+++ b/arch/riscv/kernel/cacheinfo.c -@@ -3,6 +3,7 @@ - * Copyright (C) 2017 SiFive - */ - -+#include - #include - #include - #include -@@ -112,6 +113,27 @@ int populate_cache_leaves(unsigned int cpu) - struct device_node *prev = NULL; - int levels = 1, level = 1; - -+ if (!acpi_disabled) { -+ int ret, fw_levels, split_levels; -+ -+ ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels); -+ if (ret) -+ return ret; -+ -+ BUG_ON((split_levels > fw_levels) || -+ (split_levels + fw_levels > this_cpu_ci->num_leaves)); -+ -+ for (; level <= this_cpu_ci->num_levels; level++) { -+ if (level <= split_levels) { -+ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); -+ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); -+ } else { -+ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); -+ } -+ } -+ return 0; -+ } -+ - if (of_property_read_bool(np, "cache-size")) - ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); - if (of_property_read_bool(np, "i-cache-size")) --- -2.39.5 - diff --git a/queue-5.4/riscv-cacheinfo-remove-the-useless-input-parameter-n.patch b/queue-5.4/riscv-cacheinfo-remove-the-useless-input-parameter-n.patch deleted file mode 100644 index 245c3ae861..0000000000 --- a/queue-5.4/riscv-cacheinfo-remove-the-useless-input-parameter-n.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 55bab6338ee414d53bfca90435a21a67630c0828 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 17 Jun 2024 21:14:23 +0800 -Subject: riscv: cacheinfo: remove the useless input parameter (node) of - ci_leaf_init() - -From: Yunhui Cui - -[ Upstream commit ee3fab10cb1566562aa683f319066eaeecccf918 ] - -ci_leaf_init() is a declared static function. The implementation of the -function body and the caller do not use the parameter (struct device_node -*node) input parameter, so remove it. - -Fixes: 6a24915145c9 ("Revert "riscv: Set more data to cacheinfo"") -Signed-off-by: Yunhui Cui -Reviewed-by: Jeremy Linton -Reviewed-by: Sudeep Holla -Link: https://lore.kernel.org/r/20240617131425.7526-1-cuiyunhui@bytedance.com -Signed-off-by: Palmer Dabbelt -Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties") -Signed-off-by: Sasha Levin ---- - arch/riscv/kernel/cacheinfo.c | 13 ++++++------- - 1 file changed, 6 insertions(+), 7 deletions(-) - -diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c -index 31d8f35c4f077..1d173fdbf4632 100644 ---- a/arch/riscv/kernel/cacheinfo.c -+++ b/arch/riscv/kernel/cacheinfo.c -@@ -56,7 +56,6 @@ uintptr_t get_cache_geometry(u32 level, enum cache_type type) - } - - static void ci_leaf_init(struct cacheinfo *this_leaf, -- struct device_node *node, - enum cache_type type, unsigned int level) - { - this_leaf->level = level; -@@ -114,11 +113,11 @@ int populate_cache_leaves(unsigned int cpu) - int levels = 1, level = 1; - - if (of_property_read_bool(np, "cache-size")) -- ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level); -+ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); - if (of_property_read_bool(np, "i-cache-size")) -- ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level); -+ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); - if (of_property_read_bool(np, "d-cache-size")) -- ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level); -+ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); - - prev = np; - while ((np = of_find_next_cache_node(np))) { -@@ -131,11 +130,11 @@ int populate_cache_leaves(unsigned int cpu) - if (level <= levels) - break; - if (of_property_read_bool(np, "cache-size")) -- ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level); -+ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); - if (of_property_read_bool(np, "i-cache-size")) -- ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level); -+ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); - if (of_property_read_bool(np, "d-cache-size")) -- ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level); -+ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); - levels = level; - } - of_node_put(np); --- -2.39.5 - diff --git a/queue-5.4/riscv-cacheinfo-use-of_property_present-for-non-bool.patch b/queue-5.4/riscv-cacheinfo-use-of_property_present-for-non-bool.patch deleted file mode 100644 index e086ddf4ba..0000000000 --- a/queue-5.4/riscv-cacheinfo-use-of_property_present-for-non-bool.patch +++ /dev/null @@ -1,65 +0,0 @@ -From db056268c2d9008c0934fa6b3cb57d4cfcd6b320 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 4 Nov 2024 13:03:13 -0600 -Subject: riscv: cacheinfo: Use of_property_present() for non-boolean - properties -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -From: Rob Herring - -[ Upstream commit fb8179ce2996bffaa36a04e2b6262843b01b7565 ] - -The use of of_property_read_bool() for non-boolean properties is -deprecated in favor of of_property_present() when testing for property -presence. - -Signed-off-by: Rob Herring (Arm) -Reviewed-by: Clément Léger -Cc: stable@vger.kernel.org -Fixes: 76d2a0493a17 ("RISC-V: Init and Halt Code") -Link: https://lore.kernel.org/r/20241104190314.270095-1-robh@kernel.org -Signed-off-by: Palmer Dabbelt -Signed-off-by: Sasha Levin ---- - arch/riscv/kernel/cacheinfo.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c -index 69897100e4263..86efb7e62c552 100644 ---- a/arch/riscv/kernel/cacheinfo.c -+++ b/arch/riscv/kernel/cacheinfo.c -@@ -137,11 +137,11 @@ int populate_cache_leaves(unsigned int cpu) - if (!np) - return -ENOENT; - -- if (of_property_read_bool(np, "cache-size")) -+ if (of_property_present(np, "cache-size")) - ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); -- if (of_property_read_bool(np, "i-cache-size")) -+ if (of_property_present(np, "i-cache-size")) - ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); -- if (of_property_read_bool(np, "d-cache-size")) -+ if (of_property_present(np, "d-cache-size")) - ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); - - prev = np; -@@ -154,11 +154,11 @@ int populate_cache_leaves(unsigned int cpu) - break; - if (level <= levels) - break; -- if (of_property_read_bool(np, "cache-size")) -+ if (of_property_present(np, "cache-size")) - ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); -- if (of_property_read_bool(np, "i-cache-size")) -+ if (of_property_present(np, "i-cache-size")) - ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); -- if (of_property_read_bool(np, "d-cache-size")) -+ if (of_property_present(np, "d-cache-size")) - ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); - levels = level; - } --- -2.39.5 - diff --git a/queue-5.4/riscv-prevent-a-bad-reference-count-on-cpu-nodes.patch b/queue-5.4/riscv-prevent-a-bad-reference-count-on-cpu-nodes.patch deleted file mode 100644 index f134157723..0000000000 --- a/queue-5.4/riscv-prevent-a-bad-reference-count-on-cpu-nodes.patch +++ /dev/null @@ -1,67 +0,0 @@ -From ce8f9224c6726c4f14bb17a7803521c08fd0b92b Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Fri, 13 Sep 2024 10:00:52 +0200 -Subject: riscv: Prevent a bad reference count on CPU nodes -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -From: Miquel Sabaté Solà - -[ Upstream commit 37233169a6ea912020c572f870075a63293b786a ] - -When populating cache leaves we previously fetched the CPU device node -at the very beginning. But when ACPI is enabled we go through a -specific branch which returns early and does not call 'of_node_put' for -the node that was acquired. - -Since we are not using a CPU device node for the ACPI code anyways, we -can simply move the initialization of it just passed the ACPI block, and -we are guaranteed to have an 'of_node_put' call for the acquired node. -This prevents a bad reference count of the CPU device node. - -Moreover, the previous function did not check for errors when acquiring -the device node, so a return -ENOENT has been added for that case. - -Signed-off-by: Miquel Sabaté Solà -Reviewed-by: Sudeep Holla -Reviewed-by: Sunil V L -Reviewed-by: Alexandre Ghiti -Fixes: 604f32ea6909 ("riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT") -Cc: stable@vger.kernel.org -Link: https://lore.kernel.org/r/20240913080053.36636-1-mikisabate@gmail.com -Signed-off-by: Palmer Dabbelt -Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties") -Signed-off-by: Sasha Levin ---- - arch/riscv/kernel/cacheinfo.c | 7 +++++-- - 1 file changed, 5 insertions(+), 2 deletions(-) - -diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c -index 4464174836efc..69897100e4263 100644 ---- a/arch/riscv/kernel/cacheinfo.c -+++ b/arch/riscv/kernel/cacheinfo.c -@@ -109,8 +109,7 @@ int populate_cache_leaves(unsigned int cpu) - { - struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); - struct cacheinfo *this_leaf = this_cpu_ci->info_list; -- struct device_node *np = of_cpu_device_node_get(cpu); -- struct device_node *prev = NULL; -+ struct device_node *np, *prev; - int levels = 1, level = 1; - - if (!acpi_disabled) { -@@ -134,6 +133,10 @@ int populate_cache_leaves(unsigned int cpu) - return 0; - } - -+ np = of_cpu_device_node_get(cpu); -+ if (!np) -+ return -ENOENT; -+ - if (of_property_read_bool(np, "cache-size")) - ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); - if (of_property_read_bool(np, "i-cache-size")) --- -2.39.5 - diff --git a/queue-5.4/riscv-set-more-data-to-cacheinfo.patch b/queue-5.4/riscv-set-more-data-to-cacheinfo.patch deleted file mode 100644 index e35fc94bd2..0000000000 --- a/queue-5.4/riscv-set-more-data-to-cacheinfo.patch +++ /dev/null @@ -1,122 +0,0 @@ -From fb166e44b79839e51320a1a11396e73de92da357 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 31 Aug 2020 15:33:48 +0800 -Subject: riscv: Set more data to cacheinfo - -From: Zong Li - -[ Upstream commit baf7cbd94b5688f167443a2cc3dcea3300132099 ] - -Set cacheinfo.{size,sets,line_size} for each cache node, then we can -get these information from userland through auxiliary vector. - -Signed-off-by: Zong Li -Reviewed-by: Pekka Enberg -Signed-off-by: Palmer Dabbelt -Stable-dep-of: fb8179ce2996 ("riscv: cacheinfo: Use of_property_present() for non-boolean properties") -Signed-off-by: Sasha Levin ---- - arch/riscv/kernel/cacheinfo.c | 66 +++++++++++++++++++++++++++-------- - 1 file changed, 51 insertions(+), 15 deletions(-) - -diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c -index 21dadeba06753..8cd8224f47ee1 100644 ---- a/arch/riscv/kernel/cacheinfo.c -+++ b/arch/riscv/kernel/cacheinfo.c -@@ -25,12 +25,53 @@ cache_get_priv_group(struct cacheinfo *this_leaf) - return NULL; - } - --static void ci_leaf_init(struct cacheinfo *this_leaf, -- struct device_node *node, -- enum cache_type type, unsigned int level) -+static void ci_leaf_init(struct cacheinfo *this_leaf, enum cache_type type, -+ unsigned int level, unsigned int size, -+ unsigned int sets, unsigned int line_size) - { - this_leaf->level = level; - this_leaf->type = type; -+ this_leaf->size = size; -+ this_leaf->number_of_sets = sets; -+ this_leaf->coherency_line_size = line_size; -+ -+ /* -+ * If the cache is fully associative, there is no need to -+ * check the other properties. -+ */ -+ if (sets == 1) -+ return; -+ -+ /* -+ * Set the ways number for n-ways associative, make sure -+ * all properties are big than zero. -+ */ -+ if (sets > 0 && size > 0 && line_size > 0) -+ this_leaf->ways_of_associativity = (size / sets) / line_size; -+} -+ -+static void fill_cacheinfo(struct cacheinfo **this_leaf, -+ struct device_node *node, unsigned int level) -+{ -+ unsigned int size, sets, line_size; -+ -+ if (!of_property_read_u32(node, "cache-size", &size) && -+ !of_property_read_u32(node, "cache-block-size", &line_size) && -+ !of_property_read_u32(node, "cache-sets", &sets)) { -+ ci_leaf_init((*this_leaf)++, CACHE_TYPE_UNIFIED, level, size, sets, line_size); -+ } -+ -+ if (!of_property_read_u32(node, "i-cache-size", &size) && -+ !of_property_read_u32(node, "i-cache-sets", &sets) && -+ !of_property_read_u32(node, "i-cache-block-size", &line_size)) { -+ ci_leaf_init((*this_leaf)++, CACHE_TYPE_INST, level, size, sets, line_size); -+ } -+ -+ if (!of_property_read_u32(node, "d-cache-size", &size) && -+ !of_property_read_u32(node, "d-cache-sets", &sets) && -+ !of_property_read_u32(node, "d-cache-block-size", &line_size)) { -+ ci_leaf_init((*this_leaf)++, CACHE_TYPE_DATA, level, size, sets, line_size); -+ } - } - - int init_cache_level(unsigned int cpu) -@@ -83,29 +124,24 @@ int populate_cache_leaves(unsigned int cpu) - struct device_node *prev = NULL; - int levels = 1, level = 1; - -- if (of_property_read_bool(np, "cache-size")) -- ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level); -- if (of_property_read_bool(np, "i-cache-size")) -- ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level); -- if (of_property_read_bool(np, "d-cache-size")) -- ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level); -+ /* Level 1 caches in cpu node */ -+ fill_cacheinfo(&this_leaf, np, level); - -+ /* Next level caches in cache nodes */ - prev = np; - while ((np = of_find_next_cache_node(np))) { - of_node_put(prev); - prev = np; -+ - if (!of_device_is_compatible(np, "cache")) - break; - if (of_property_read_u32(np, "cache-level", &level)) - break; - if (level <= levels) - break; -- if (of_property_read_bool(np, "cache-size")) -- ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level); -- if (of_property_read_bool(np, "i-cache-size")) -- ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level); -- if (of_property_read_bool(np, "d-cache-size")) -- ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level); -+ -+ fill_cacheinfo(&this_leaf, np, level); -+ - levels = level; - } - of_node_put(np); --- -2.39.5 - diff --git a/queue-5.4/series b/queue-5.4/series index b7782c3813..d59717fbc2 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -271,14 +271,6 @@ acct-perform-last-write-from-workqueue.patch drm-amdgpu-skip-bar-resizing-if-the-bios-already-did.patch drm-amdgpu-check-extended-configuration-space-regist.patch drm-amdgpu-disable-bar-resize-on-dell-g5-se.patch -riscv-cacheinfo-implement-cache_get_priv_group-with-.patch -riscv-set-more-data-to-cacheinfo.patch -riscv-add-cache-information-in-aux-vector.patch -revert-riscv-set-more-data-to-cacheinfo.patch -riscv-cacheinfo-remove-the-useless-input-parameter-n.patch -riscv-cacheinfo-initialize-cacheinfo-s-level-and-typ.patch -riscv-prevent-a-bad-reference-count-on-cpu-nodes.patch -riscv-cacheinfo-use-of_property_present-for-non-bool.patch revert-of-reserved-memory-fix-using-wrong-number-of-cells-to-get-property-alignment.patch hid-appleir-fix-potential-null-dereference-at-raw-event-handle.patch alsa-hda-intel-add-dell-alc3271-to-power_save-denylist.patch