From: Andreas Schwab Date: Thu, 10 Jul 2025 13:32:18 +0000 (+0200) Subject: riscv: traps_misaligned: properly sign extend value in misaligned load handler X-Git-Tag: v6.16-rc7~22^2~2 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=b3510183ab7d63c71a3f5c89043d31686a76a34c;p=thirdparty%2Flinux.git riscv: traps_misaligned: properly sign extend value in misaligned load handler Add missing cast to signed long. Signed-off-by: Andreas Schwab Fixes: 956d705dd279 ("riscv: Unaligned load/store handling for M_MODE") Tested-by: Clément Léger Link: https://lore.kernel.org/r/mvmikk0goil.fsf@suse.de Signed-off-by: Palmer Dabbelt --- diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 93043924fe6c6..f760e4fcc052d 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -461,7 +461,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs) } if (!fp) - SET_RD(insn, regs, val.data_ulong << shift >> shift); + SET_RD(insn, regs, (long)(val.data_ulong << shift) >> shift); else if (len == 8) set_f64_rd(insn, regs, val.data_u64); else