From: Robin Dapp Date: Tue, 14 Nov 2023 13:11:09 +0000 (+0100) Subject: RISC-V: Disallow 64-bit indexed loads and stores for rv32gcv. X-Git-Tag: basepoints/gcc-15~4516 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=b3677563cd3ebc20c186650ff94171d321a52b30;p=thirdparty%2Fgcc.git RISC-V: Disallow 64-bit indexed loads and stores for rv32gcv. We currently allow 64-bit indices/offsets for vector indexed loads and stores even on rv32 but we should not. This patch adjusts the iterators as well as the insn conditions to reflect the RVV spec. It also fixes an oversight in the VLS modes of the demote iterator that was found while testing the patch. gcc/ChangeLog: * config/riscv/riscv-v.cc (gather_scatter_valid_offset_mode_p): Add check for XLEN == 32. * config/riscv/vector-iterators.md: Change VLS part of the demote iterator to 2x elements modes * config/riscv/vector.md: Adjust iterators and insn conditions. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-1.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-1.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-10.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-10.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-11.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-11.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-12.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-12.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-2.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-2.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-3.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-3.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-4.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-4.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-5.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-5.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-6.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-6.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-7.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-7.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-8.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-8.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-9.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-9.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-1.c: Adjust include. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-10.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-11.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-5.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-6.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-7.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-8.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-9.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-1.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-1.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-10.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-10.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-11.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-11.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-2.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-2.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-3.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-3.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-4.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-4.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-5.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-5.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-6.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-6.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-7.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-7.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-8.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-8.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-9.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-9.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-1.c: Adjust include. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-10.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-11.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-5.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-6.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-7.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-8.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-9.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-1.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-1.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-10.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-10.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-2.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-2.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-3.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-3.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-4.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-4.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-5.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-5.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-6.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-6.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-7.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-7.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-8.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-8.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-9.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-9.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-1.c: Adjust include. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-10.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-5.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-6.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-7.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-8.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-9.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-1.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-1.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-10.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-10.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-3.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-2.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-4.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-4.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-5.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-5.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-6.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-6.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-7.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-7.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-8.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-8.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-9.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-9.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-2.c: Moved to... * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-2.c: ...here. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-1.c: Adjust include. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-10.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-5.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-6.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-7.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-8.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-9.c: Ditto. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-1.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-10.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-11.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-2.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-3.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-4.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-5.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-6.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-7.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-8.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-9.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-1.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-10.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-11.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-2.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-3.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-4.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-5.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-6.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-7.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-8.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-9.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-1.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-10.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-2.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-3.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-4.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-5.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-6.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-7.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-8.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-9.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-1.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-10.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-3.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-4.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-5.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-6.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-7.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-8.c: New test. * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-9.c: New test. --- diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index f0ddfd99e913..541dffba07b1 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -4024,7 +4024,14 @@ bool gather_scatter_valid_offset_mode_p (machine_mode mode) { machine_mode new_mode; - return get_vector_mode (Pmode, GET_MODE_NUNITS (mode)).exists (&new_mode); + /* RISC-V V Spec 18.3: + The V extension supports all vector load and store instructions (Section + Vector Loads and Stores), except the V extension does not support EEW=64 + for index values when XLEN=32. */ + + if (GET_MODE_BITSIZE (GET_MODE_INNER (mode)) <= GET_MODE_BITSIZE (Pmode)) + return get_vector_mode (Pmode, GET_MODE_NUNITS (mode)).exists (&new_mode); + return false; } /* We don't have to convert the floating point to integer when the diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 469875ce67c8..40a36f9dbb11 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -319,23 +319,36 @@ (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") - RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") + (RVVM4SI "TARGET_64BIT") + (RVVM2SI "TARGET_64BIT") + (RVVM1SI "TARGET_64BIT") + (RVVMF2SI "TARGET_MIN_VLEN > 32 && TARGET_64BIT") - (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") - (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") + (RVVM4SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_64BIT") + (RVVM2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_64BIT") + (RVVM1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_64BIT") + (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_64BIT") ]) (define_mode_iterator VEEWTRUNC4 [ RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") - RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") + (RVVM2HI "TARGET_64BIT") + (RVVM1HI "TARGET_64BIT") + (RVVMF2HI "TARGET_64BIT") + (RVVMF4HI "TARGET_MIN_VLEN > 32 && TARGET_64BIT") - (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") - (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") + (RVVM2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_64BIT") + (RVVM1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_64BIT") + (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_64BIT") + (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32 && TARGET_64BIT") ]) (define_mode_iterator VEEWTRUNC8 [ - RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") + (RVVM1QI "TARGET_64BIT") + (RVVMF2QI "TARGET_64BIT") + (RVVMF4QI "TARGET_64BIT") + (RVVMF8QI "TARGET_MIN_VLEN > 32 && TARGET_64BIT") ]) (define_mode_iterator VEI16 [ @@ -793,28 +806,28 @@ (RVVMF8QI "TARGET_MIN_VLEN > 32") (RVVMF4HI "TARGET_MIN_VLEN > 32") (RVVMF2SI "TARGET_MIN_VLEN > 32") - (RVVM1DI "TARGET_VECTOR_ELEN_64") + (RVVM1DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT") ]) (define_mode_iterator RATIO32I [ RVVMF4QI RVVMF2HI RVVM1SI - (RVVM2DI "TARGET_VECTOR_ELEN_64") + (RVVM2DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT") ]) (define_mode_iterator RATIO16I [ RVVMF2QI RVVM1HI RVVM2SI - (RVVM4DI "TARGET_VECTOR_ELEN_64") + (RVVM4DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT") ]) (define_mode_iterator RATIO8I [ RVVM1QI RVVM2HI RVVM4SI - (RVVM8DI "TARGET_VECTOR_ELEN_64") + (RVVM8DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT") ]) (define_mode_iterator RATIO4I [ @@ -1421,11 +1434,123 @@ (V1024BI "riscv_vector::vls_mode_valid_p (V1024BImode) && TARGET_MIN_VLEN >= 1024") (V2048BI "riscv_vector::vls_mode_valid_p (V2048BImode) && TARGET_MIN_VLEN >= 2048") (V4096BI "riscv_vector::vls_mode_valid_p (V4096BImode) && TARGET_MIN_VLEN >= 4096")]) - + (define_mode_iterator VB [ (RVVMF64BI "TARGET_MIN_VLEN > 32") RVVMF32BI RVVMF16BI RVVMF8BI RVVMF4BI RVVMF2BI RVVM1BI ]) +;; Iterator for indexed loads and stores. We must disallow 64-bit indices on +;; XLEN=32 targets. TODO: Split iterators so more of them can be reused, i.e. +;; VI8, VI16, VI32, VI64 and then use +;; VINDEXED [VI8 VI16 VI32 (VI64 "TARGET_64BIT")]. + +(define_mode_iterator VINDEXED [ + RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") + + RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") + + RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") + + (RVVM8DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT") + (RVVM4DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT") + (RVVM2DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT") + (RVVM1DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT") + + (RVVM8HF "TARGET_ZVFH") (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH") + (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH") + (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") + + (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") + (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") + (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") + + (RVVM8DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_64BIT") + (RVVM4DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_64BIT") + (RVVM2DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_64BIT") + (RVVM1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_64BIT") + + (V1QI "riscv_vector::vls_mode_valid_p (V1QImode)") + (V2QI "riscv_vector::vls_mode_valid_p (V2QImode)") + (V4QI "riscv_vector::vls_mode_valid_p (V4QImode)") + (V8QI "riscv_vector::vls_mode_valid_p (V8QImode)") + (V16QI "riscv_vector::vls_mode_valid_p (V16QImode)") + (V32QI "riscv_vector::vls_mode_valid_p (V32QImode)") + (V64QI "riscv_vector::vls_mode_valid_p (V64QImode) && TARGET_MIN_VLEN >= 64") + (V128QI "riscv_vector::vls_mode_valid_p (V128QImode) && TARGET_MIN_VLEN >= 128") + (V256QI "riscv_vector::vls_mode_valid_p (V256QImode) && TARGET_MIN_VLEN >= 256") + (V512QI "riscv_vector::vls_mode_valid_p (V512QImode) && TARGET_MIN_VLEN >= 512") + (V1024QI "riscv_vector::vls_mode_valid_p (V1024QImode) && TARGET_MIN_VLEN >= 1024") + (V2048QI "riscv_vector::vls_mode_valid_p (V2048QImode) && TARGET_MIN_VLEN >= 2048") + (V4096QI "riscv_vector::vls_mode_valid_p (V4096QImode) && TARGET_MIN_VLEN >= 4096") + (V1HI "riscv_vector::vls_mode_valid_p (V1HImode)") + (V2HI "riscv_vector::vls_mode_valid_p (V2HImode)") + (V4HI "riscv_vector::vls_mode_valid_p (V4HImode)") + (V8HI "riscv_vector::vls_mode_valid_p (V8HImode)") + (V16HI "riscv_vector::vls_mode_valid_p (V16HImode)") + (V32HI "riscv_vector::vls_mode_valid_p (V32HImode) && TARGET_MIN_VLEN >= 64") + (V64HI "riscv_vector::vls_mode_valid_p (V64HImode) && TARGET_MIN_VLEN >= 128") + (V128HI "riscv_vector::vls_mode_valid_p (V128HImode) && TARGET_MIN_VLEN >= 256") + (V256HI "riscv_vector::vls_mode_valid_p (V256HImode) && TARGET_MIN_VLEN >= 512") + (V512HI "riscv_vector::vls_mode_valid_p (V512HImode) && TARGET_MIN_VLEN >= 1024") + (V1024HI "riscv_vector::vls_mode_valid_p (V1024HImode) && TARGET_MIN_VLEN >= 2048") + (V2048HI "riscv_vector::vls_mode_valid_p (V2048HImode) && TARGET_MIN_VLEN >= 4096") + (V1SI "riscv_vector::vls_mode_valid_p (V1SImode)") + (V2SI "riscv_vector::vls_mode_valid_p (V2SImode)") + (V4SI "riscv_vector::vls_mode_valid_p (V4SImode)") + (V8SI "riscv_vector::vls_mode_valid_p (V8SImode)") + (V16SI "riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= 64") + (V32SI "riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= 128") + (V64SI "riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= 256") + (V128SI "riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= 512") + (V256SI "riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_MIN_VLEN >= 1024") + (V512SI "riscv_vector::vls_mode_valid_p (V512SImode) && TARGET_MIN_VLEN >= 2048") + (V1024SI "riscv_vector::vls_mode_valid_p (V1024SImode) && TARGET_MIN_VLEN >= 4096") + (V1DI "riscv_vector::vls_mode_valid_p (V1DImode) && TARGET_VECTOR_ELEN_64 && TARGET_64BIT") + (V2DI "riscv_vector::vls_mode_valid_p (V2DImode) && TARGET_VECTOR_ELEN_64 && TARGET_64BIT") + (V4DI "riscv_vector::vls_mode_valid_p (V4DImode) && TARGET_VECTOR_ELEN_64 && TARGET_64BIT") + (V8DI "riscv_vector::vls_mode_valid_p (V8DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64 && TARGET_64BIT") + (V16DI "riscv_vector::vls_mode_valid_p (V16DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128 && TARGET_64BIT") + (V32DI "riscv_vector::vls_mode_valid_p (V32DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256 && TARGET_64BIT") + (V64DI "riscv_vector::vls_mode_valid_p (V64DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512 && TARGET_64BIT") + (V128DI "riscv_vector::vls_mode_valid_p (V128DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024 && TARGET_64BIT") + (V256DI "riscv_vector::vls_mode_valid_p (V256DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048 && TARGET_64BIT") + (V512DI "riscv_vector::vls_mode_valid_p (V512DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096 && TARGET_64BIT") + + (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_ZVFH") + (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_ZVFH") + (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_ZVFH") + (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_ZVFH") + (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_ZVFH") + (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 64") + (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 128") + (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 256") + (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 512") + (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024") + (V1024HF "riscv_vector::vls_mode_valid_p (V1024HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 2048") + (V2048HF "riscv_vector::vls_mode_valid_p (V2048HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 4096") + (V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_FP_32") + (V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_FP_32") + (V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_FP_32") + (V8SF "riscv_vector::vls_mode_valid_p (V8SFmode) && TARGET_VECTOR_ELEN_FP_32") + (V16SF "riscv_vector::vls_mode_valid_p (V16SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64") + (V32SF "riscv_vector::vls_mode_valid_p (V32SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128") + (V64SF "riscv_vector::vls_mode_valid_p (V64SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256") + (V128SF "riscv_vector::vls_mode_valid_p (V128SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512") + (V256SF "riscv_vector::vls_mode_valid_p (V256SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024") + (V512SF "riscv_vector::vls_mode_valid_p (V512SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048") + (V1024SF "riscv_vector::vls_mode_valid_p (V1024SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096") + (V1DF "riscv_vector::vls_mode_valid_p (V1DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_64BIT") + (V2DF "riscv_vector::vls_mode_valid_p (V2DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_64BIT") + (V4DF "riscv_vector::vls_mode_valid_p (V4DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_64BIT") + (V8DF "riscv_vector::vls_mode_valid_p (V8DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64 && TARGET_64BIT") + (V16DF "riscv_vector::vls_mode_valid_p (V16DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128 && TARGET_64BIT") + (V32DF "riscv_vector::vls_mode_valid_p (V32DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256 && TARGET_64BIT") + (V64DF "riscv_vector::vls_mode_valid_p (V64DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512 && TARGET_64BIT") + (V128DF "riscv_vector::vls_mode_valid_p (V128DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024 && TARGET_64BIT") + (V256DF "riscv_vector::vls_mode_valid_p (V256DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048 && TARGET_64BIT") + (V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096 && TARGET_64BIT") +]) + (define_mode_iterator VB_VLS [VB VLSB]) (define_mode_iterator VLS [VLSI VLSF_ZVFHMIN]) @@ -3200,30 +3325,30 @@ (define_mode_attr VDEMOTE [ (RVVM8DI "RVVM8SI") (RVVM4DI "RVVM4SI") (RVVM2DI "RVVM2SI") (RVVM1DI "RVVM1SI") - (V1DI "V1SI") - (V2DI "V2SI") - (V4DI "V4SI") - (V8DI "V8SI") - (V16DI "V16SI") - (V32DI "V32SI") - (V64DI "V64SI") - (V128DI "V128SI") - (V256DI "V256SI") - (V512DI "V512SI") + (V1DI "V2SI") + (V2DI "V4SI") + (V4DI "V8SI") + (V8DI "V16SI") + (V16DI "V32SI") + (V32DI "V64SI") + (V64DI "V128SI") + (V128DI "V256SI") + (V256DI "V512SI") + (V512DI "V1024SI") ]) (define_mode_attr VMDEMOTE [ (RVVM8DI "RVVMF4BI") (RVVM4DI "RVVMF8BI") (RVVM2DI "RVVMF16BI") (RVVM1DI "RVVMF32BI") - (V1DI "V1BI") - (V2DI "V2BI") - (V4DI "V4BI") - (V8DI "V8BI") - (V16DI "V16BI") - (V32DI "V32BI") - (V64DI "V64BI") - (V128DI "V128BI") - (V256DI "V256BI") - (V512DI "V512BI") + (V1DI "V2BI") + (V2DI "V4BI") + (V4DI "V8BI") + (V8DI "V16BI") + (V16DI "V32BI") + (V32DI "V64BI") + (V64DI "V128BI") + (V128DI "V256BI") + (V256DI "V512BI") + (V512DI "V1024BI") ]) (define_mode_attr stride_predicate [ diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index d1499d330ff0..440c5696343e 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -2201,21 +2201,21 @@ ;; DEST eew is same as SOURCE eew, DEST register can overlap SOURCE. (define_insn "@pred_indexed_load_same_eew" - [(set (match_operand:V 0 "register_operand" "=vd, vr,vd, vr") - (if_then_else:V + [(set (match_operand:VINDEXED 0 "register_operand" "=vd, vr,vd, vr") + (if_then_else:VINDEXED (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vm,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK,rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") - (match_operand 8 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vm,Wc1") + (match_operand 5 "vector_length_operand" " rK, rK,rK, rK") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (unspec:V - [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ,rJ, rJ") + (unspec:VINDEXED + [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ,rJ, rJ") (mem:BLK (scratch)) - (match_operand: 4 "register_operand" " vr, vr,vr, vr")] ORDER) - (match_operand:V 2 "vector_merge_operand" " vu, vu, 0, 0")))] + (match_operand: 4 "register_operand" " vr, vr,vr, vr")] ORDER) + (match_operand:VINDEXED 2 "vector_merge_operand" " vu, vu, 0, 0")))] "TARGET_VECTOR" "vlxei.v\t%0,(%z3),%4%p1" [(set_attr "type" "vldx") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-1.c new file mode 100644 index 000000000000..8ae5106b8a08 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-1.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX8 uint8_t +#define INDEX16 uint16_t +#define INDEX32 uint32_t +#define INDEX64 uint64_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices) \ + { \ + for (int i = 0; i < 128; ++i) \ + dest[i] += src[indices[i]]; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 8) \ + T (uint8_t, 8) \ + T (int16_t, 16) \ + T (uint16_t, 16) \ + T (_Float16, 16) \ + T (int32_t, 32) \ + T (uint32_t, 32) \ + T (float, 32) \ + T (int64_t, 64) \ + T (uint64_t, 64) \ + T (double, 64) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 11 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-10.c new file mode 100644 index 000000000000..d705c920a2b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-10.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX64 int64_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices) \ + { \ + for (int i = 0; i < 128; ++i) \ + dest[i] += src[indices[i]]; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 64) \ + T (uint8_t, 64) \ + T (int16_t, 64) \ + T (uint16_t, 64) \ + T (_Float16, 64) \ + T (int32_t, 64) \ + T (uint32_t, 64) \ + T (float, 64) \ + T (int64_t, 64) \ + T (uint64_t, 64) \ + T (double, 64) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 11 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-11.c new file mode 100644 index 000000000000..4e183cd9170f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-11.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define TEST_LOOP(DATA_TYPE) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict *src) \ + { \ + for (int i = 0; i < 128; ++i) \ + dest[i] += *src[i]; \ + } + +#define TEST_ALL(T) \ + T (int8_t) \ + T (uint8_t) \ + T (int16_t) \ + T (uint16_t) \ + T (_Float16) \ + T (int32_t) \ + T (uint32_t) \ + T (float) \ + T (int64_t) \ + T (uint64_t) \ + T (double) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 11 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-12.c similarity index 100% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-12.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-12.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-2.c new file mode 100644 index 000000000000..e4e42fef9726 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-2.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX8 int8_t +#define INDEX16 int16_t +#define INDEX32 int32_t +#define INDEX64 int64_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices) \ + { \ + for (int i = 0; i < 128; ++i) \ + dest[i] += src[indices[i]]; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 8) \ + T (uint8_t, 8) \ + T (int16_t, 16) \ + T (uint16_t, 16) \ + T (_Float16, 16) \ + T (int32_t, 32) \ + T (uint32_t, 32) \ + T (float, 32) \ + T (int64_t, 64) \ + T (uint64_t, 64) \ + T (double, 64) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 11 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-3.c new file mode 100644 index 000000000000..e385fee109d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-3.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX8 uint8_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices) \ + { \ + for (int i = 0; i < 128; ++i) \ + dest[i] += src[indices[i]]; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 8) \ + T (uint8_t, 8) \ + T (int16_t, 8) \ + T (uint16_t, 8) \ + T (_Float16, 8) \ + T (int32_t, 8) \ + T (uint32_t, 8) \ + T (float, 8) \ + T (int64_t, 8) \ + T (uint64_t, 8) \ + T (double, 8) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 11 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-4.c new file mode 100644 index 000000000000..e5cb19de42fa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-4.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX8 int8_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices) \ + { \ + for (int i = 0; i < 128; ++i) \ + dest[i] += src[indices[i]]; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 8) \ + T (uint8_t, 8) \ + T (int16_t, 8) \ + T (uint16_t, 8) \ + T (_Float16, 8) \ + T (int32_t, 8) \ + T (uint32_t, 8) \ + T (float, 8) \ + T (int64_t, 8) \ + T (uint64_t, 8) \ + T (double, 8) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 11 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-5.c new file mode 100644 index 000000000000..a437e7393ee3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-5.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX16 uint16_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices) \ + { \ + for (int i = 0; i < 128; ++i) \ + dest[i] += src[indices[i]]; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 16) \ + T (uint8_t, 16) \ + T (int16_t, 16) \ + T (uint16_t, 16) \ + T (_Float16, 16) \ + T (int32_t, 16) \ + T (uint32_t, 16) \ + T (float, 16) \ + T (int64_t, 16) \ + T (uint64_t, 16) \ + T (double, 16) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 11 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-6.c new file mode 100644 index 000000000000..487dca9928b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-6.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX16 int16_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices) \ + { \ + for (int i = 0; i < 128; ++i) \ + dest[i] += src[indices[i]]; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 16) \ + T (uint8_t, 16) \ + T (int16_t, 16) \ + T (uint16_t, 16) \ + T (_Float16, 16) \ + T (int32_t, 16) \ + T (uint32_t, 16) \ + T (float, 16) \ + T (int64_t, 16) \ + T (uint64_t, 16) \ + T (double, 16) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 11 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-7.c new file mode 100644 index 000000000000..ff91929b8e70 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-7.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX32 uint32_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices) \ + { \ + for (int i = 0; i < 128; ++i) \ + dest[i] += src[indices[i]]; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 32) \ + T (uint8_t, 32) \ + T (int16_t, 32) \ + T (uint16_t, 32) \ + T (_Float16, 32) \ + T (int32_t, 32) \ + T (uint32_t, 32) \ + T (float, 32) \ + T (int64_t, 32) \ + T (uint64_t, 32) \ + T (double, 32) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 11 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-8.c new file mode 100644 index 000000000000..81df57fcbd2a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-8.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX32 int32_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices) \ + { \ + for (int i = 0; i < 128; ++i) \ + dest[i] += src[indices[i]]; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 32) \ + T (uint8_t, 32) \ + T (int16_t, 32) \ + T (uint16_t, 32) \ + T (_Float16, 32) \ + T (int32_t, 32) \ + T (uint32_t, 32) \ + T (float, 32) \ + T (int64_t, 32) \ + T (uint64_t, 32) \ + T (double, 32) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 11 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-9.c new file mode 100644 index 000000000000..238b6bce042f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_32-9.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX64 uint64_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices) \ + { \ + for (int i = 0; i < 128; ++i) \ + dest[i] += src[indices[i]]; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 64) \ + T (uint8_t, 64) \ + T (int16_t, 64) \ + T (uint16_t, 64) \ + T (_Float16, 64) \ + T (int32_t, 64) \ + T (uint32_t, 64) \ + T (float, 64) \ + T (int64_t, 64) \ + T (uint64_t, 64) \ + T (double, 64) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 11 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-1.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-1.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-1.c index 3b26bf1dec26..eabe0124b695 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-10.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-10.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-10.c index 63949cbe02bf..ba4bc7803441 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-11.c similarity index 94% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-11.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-11.c index 8dc1da3f4b48..e75b6948ab50 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-11.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12.c new file mode 100644 index 000000000000..d8daf3fa1dbf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-12.c @@ -0,0 +1,110 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-vect-cost-model -fdump-tree-vect-details" } */ + +#include + +#define TEST_LOOP(DATA_TYPE, INDEX_TYPE) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE##_##INDEX_TYPE (DATA_TYPE *restrict y, DATA_TYPE *restrict x, \ + INDEX_TYPE *restrict index) \ + { \ + for (int i = 0; i < 100; ++i) \ + { \ + y[i * 2] = x[index[i * 2]] + 1; \ + y[i * 2 + 1] = x[index[i * 2 + 1]] + 2; \ + } \ + } + +TEST_LOOP (int8_t, int8_t) +TEST_LOOP (uint8_t, int8_t) +TEST_LOOP (int16_t, int8_t) +TEST_LOOP (uint16_t, int8_t) +TEST_LOOP (int32_t, int8_t) +TEST_LOOP (uint32_t, int8_t) +TEST_LOOP (int64_t, int8_t) +TEST_LOOP (uint64_t, int8_t) +TEST_LOOP (_Float16, int8_t) +TEST_LOOP (float, int8_t) +TEST_LOOP (double, int8_t) +TEST_LOOP (int8_t, int16_t) +TEST_LOOP (uint8_t, int16_t) +TEST_LOOP (int16_t, int16_t) +TEST_LOOP (uint16_t, int16_t) +TEST_LOOP (int32_t, int16_t) +TEST_LOOP (uint32_t, int16_t) +TEST_LOOP (int64_t, int16_t) +TEST_LOOP (uint64_t, int16_t) +TEST_LOOP (_Float16, int16_t) +TEST_LOOP (float, int16_t) +TEST_LOOP (double, int16_t) +TEST_LOOP (int8_t, int32_t) +TEST_LOOP (uint8_t, int32_t) +TEST_LOOP (int16_t, int32_t) +TEST_LOOP (uint16_t, int32_t) +TEST_LOOP (int32_t, int32_t) +TEST_LOOP (uint32_t, int32_t) +TEST_LOOP (int64_t, int32_t) +TEST_LOOP (uint64_t, int32_t) +TEST_LOOP (_Float16, int32_t) +TEST_LOOP (float, int32_t) +TEST_LOOP (double, int32_t) +TEST_LOOP (int8_t, int64_t) +TEST_LOOP (uint8_t, int64_t) +TEST_LOOP (int16_t, int64_t) +TEST_LOOP (uint16_t, int64_t) +TEST_LOOP (int32_t, int64_t) +TEST_LOOP (uint32_t, int64_t) +TEST_LOOP (int64_t, int64_t) +TEST_LOOP (uint64_t, int64_t) +TEST_LOOP (_Float16, int64_t) +TEST_LOOP (float, int64_t) +TEST_LOOP (double, int64_t) +TEST_LOOP (int8_t, uint8_t) +TEST_LOOP (uint8_t, uint8_t) +TEST_LOOP (int16_t, uint8_t) +TEST_LOOP (uint16_t, uint8_t) +TEST_LOOP (int32_t, uint8_t) +TEST_LOOP (uint32_t, uint8_t) +TEST_LOOP (int64_t, uint8_t) +TEST_LOOP (uint64_t, uint8_t) +TEST_LOOP (_Float16, uint8_t) +TEST_LOOP (float, uint8_t) +TEST_LOOP (double, uint8_t) +TEST_LOOP (int8_t, uint16_t) +TEST_LOOP (uint8_t, uint16_t) +TEST_LOOP (int16_t, uint16_t) +TEST_LOOP (uint16_t, uint16_t) +TEST_LOOP (int32_t, uint16_t) +TEST_LOOP (uint32_t, uint16_t) +TEST_LOOP (int64_t, uint16_t) +TEST_LOOP (uint64_t, uint16_t) +TEST_LOOP (_Float16, uint16_t) +TEST_LOOP (float, uint16_t) +TEST_LOOP (double, uint16_t) +TEST_LOOP (int8_t, uint32_t) +TEST_LOOP (uint8_t, uint32_t) +TEST_LOOP (int16_t, uint32_t) +TEST_LOOP (uint16_t, uint32_t) +TEST_LOOP (int32_t, uint32_t) +TEST_LOOP (uint32_t, uint32_t) +TEST_LOOP (int64_t, uint32_t) +TEST_LOOP (uint64_t, uint32_t) +TEST_LOOP (_Float16, uint32_t) +TEST_LOOP (float, uint32_t) +TEST_LOOP (double, uint32_t) +TEST_LOOP (int8_t, uint64_t) +TEST_LOOP (uint8_t, uint64_t) +TEST_LOOP (int16_t, uint64_t) +TEST_LOOP (uint16_t, uint64_t) +TEST_LOOP (int32_t, uint64_t) +TEST_LOOP (uint32_t, uint64_t) +TEST_LOOP (int64_t, uint64_t) +TEST_LOOP (uint64_t, uint64_t) +TEST_LOOP (_Float16, uint64_t) +TEST_LOOP (float, uint64_t) +TEST_LOOP (double, uint64_t) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 88 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-2.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-2.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-2.c index 89e4b40bfd87..3389bc4bb761 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-3.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-3.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-3.c index 02fd37c026dd..b23603a76e6a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-4.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-4.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-4.c index af6a76af7f88..024710344f89 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-5.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-5.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-5.c index bd9a449086ed..19ff214c062d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-6.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-6.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-6.c index 6d776af4c5c0..fd7684b5aab4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-7.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-7.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-7.c index 040300a3e2a6..9800b93a04cd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-8.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-8.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-8.c index 9223bf0057d5..4f84fe158b8b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-9.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-9.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-9.c index 2e06fe6090d4..41a7ae578e9f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_64-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-1.c index 232873ccd888..3ca1b0c6e086 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-1.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "gather_load-1.c" +#include "gather_load_64-1.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-10.c index 9696a21e3cf7..ef1517a737df 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-10.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "gather_load-10.c" +#include "gather_load_64-10.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-11.c index 459a1a8f4d71..c4355842faaf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-11.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "gather_load-11.c" +#include "gather_load_64-11.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c index 1cbf507fad16..d48d5295a066 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-12.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "gather_load-12.c" +#include "gather_load_64-12.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-2.c index 93a07e00e964..b1290ec393d9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-2.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "gather_load-2.c" +#include "gather_load_64-2.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-3.c index f318a4373e90..8b8687013ec6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-3.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "gather_load-3.c" +#include "gather_load_64-3.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-4.c index a210cdf53e26..2085474f4ac6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-4.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "gather_load-4.c" +#include "gather_load_64-4.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-5.c index ade9175e85d9..ad918131b56c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-5.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "gather_load-5.c" +#include "gather_load_64-5.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-6.c index f5bdece406d2..53b32543bad7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-6.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "gather_load-6.c" +#include "gather_load_64-6.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-7.c index 47a178362e0c..8e135a7022c8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-7.c @@ -5,7 +5,7 @@ compiles properly. */ /* { dg-additional-options "-mcmodel=medany" } */ -#include "gather_load-7.c" +#include "gather_load_64-7.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-8.c index 1ce180404d78..8f13ec67a2a9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-8.c @@ -5,7 +5,7 @@ compiles properly. */ /* { dg-additional-options "-mcmodel=medany" } */ -#include "gather_load-8.c" +#include "gather_load_64-8.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-9.c index 3c08c634823e..2e17075e548b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-9.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "gather_load-9.c" +#include "gather_load_64-9.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-1.c new file mode 100644 index 000000000000..055e392739de --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-1.c @@ -0,0 +1,41 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-schedule-insns -fdump-tree-vect-details" } */ + +#include + +#define INDEX8 uint8_t +#define INDEX16 uint16_t +#define INDEX32 uint32_t +#define INDEX64 uint64_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices, INDEX##BITS *restrict cond) \ + { \ + for (int i = 0; i < 128; ++i) \ + if (cond[i]) \ + dest[i] += src[indices[i]]; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 8) \ + T (uint8_t, 8) \ + T (int16_t, 16) \ + T (uint16_t, 16) \ + T (_Float16, 16) \ + T (int32_t, 32) \ + T (uint32_t, 32) \ + T (float, 32) \ + T (int64_t, 64) \ + T (uint64_t, 64) \ + T (double, 64) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-10.c new file mode 100644 index 000000000000..5582ca7c0b2e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-10.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-schedule-insns -fdump-tree-vect-details" } */ + +#include + +#define INDEX64 int64_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices, INDEX##BITS *restrict cond) \ + { \ + for (int i = 0; i < 128; ++i) \ + if (cond[i]) \ + dest[i] += src[indices[i]]; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 64) \ + T (uint8_t, 64) \ + T (int16_t, 64) \ + T (uint16_t, 64) \ + T (_Float16, 64) \ + T (int32_t, 64) \ + T (uint32_t, 64) \ + T (float, 64) \ + T (int64_t, 64) \ + T (uint64_t, 64) \ + T (double, 64) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-11.c similarity index 99% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-11.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-11.c index e5741812b21a..54392f4512fc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-11.c @@ -107,7 +107,7 @@ TEST_LOOP (_Float16, uint64_t) TEST_LOOP (float, uint64_t) TEST_LOOP (double, uint64_t) -/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 88 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 64 "vect" } } */ /* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ /* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ /* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-2.c new file mode 100644 index 000000000000..a2d135854bff --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-2.c @@ -0,0 +1,41 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-schedule-insns -fdump-tree-vect-details" } */ + +#include + +#define INDEX8 int8_t +#define INDEX16 int16_t +#define INDEX32 int32_t +#define INDEX64 int64_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices, INDEX##BITS *restrict cond) \ + { \ + for (int i = 0; i < 128; ++i) \ + if (cond[i]) \ + dest[i] += src[indices[i]]; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 8) \ + T (uint8_t, 8) \ + T (int16_t, 16) \ + T (uint16_t, 16) \ + T (_Float16, 16) \ + T (int32_t, 32) \ + T (uint32_t, 32) \ + T (float, 32) \ + T (int64_t, 64) \ + T (uint64_t, 64) \ + T (double, 64) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-3.c new file mode 100644 index 000000000000..66aa5c21bf0e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-3.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-schedule-insns -fdump-tree-vect-details" } */ + +#include + +#define INDEX8 uint8_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices, INDEX##BITS *restrict cond) \ + { \ + for (int i = 0; i < 128; ++i) \ + if (cond[i]) \ + dest[i] += src[indices[i]]; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 8) \ + T (uint8_t, 8) \ + T (int16_t, 8) \ + T (uint16_t, 8) \ + T (_Float16, 8) \ + T (int32_t, 8) \ + T (uint32_t, 8) \ + T (float, 8) \ + T (int64_t, 8) \ + T (uint64_t, 8) \ + T (double, 8) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-4.c new file mode 100644 index 000000000000..80c43de2f12b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-4.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-schedule-insns -fdump-tree-vect-details" } */ + +#include + +#define INDEX8 int8_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices, INDEX##BITS *restrict cond) \ + { \ + for (int i = 0; i < 128; ++i) \ + if (cond[i]) \ + dest[i] += src[indices[i]]; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 8) \ + T (uint8_t, 8) \ + T (int16_t, 8) \ + T (uint16_t, 8) \ + T (_Float16, 8) \ + T (int32_t, 8) \ + T (uint32_t, 8) \ + T (float, 8) \ + T (int64_t, 8) \ + T (uint64_t, 8) \ + T (double, 8) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-5.c new file mode 100644 index 000000000000..972f021dda0a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-5.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-schedule-insns -fdump-tree-vect-details" } */ + +#include + +#define INDEX16 uint16_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices, INDEX##BITS *restrict cond) \ + { \ + for (int i = 0; i < 128; ++i) \ + if (cond[i]) \ + dest[i] += src[indices[i]]; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 16) \ + T (uint8_t, 16) \ + T (int16_t, 16) \ + T (uint16_t, 16) \ + T (_Float16, 16) \ + T (int32_t, 16) \ + T (uint32_t, 16) \ + T (float, 16) \ + T (int64_t, 16) \ + T (uint64_t, 16) \ + T (double, 16) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-6.c new file mode 100644 index 000000000000..33114baebc7a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-6.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-schedule-insns -fdump-tree-vect-details" } */ + +#include + +#define INDEX16 int16_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices, INDEX##BITS *restrict cond) \ + { \ + for (int i = 0; i < 128; ++i) \ + if (cond[i]) \ + dest[i] += src[indices[i]]; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 16) \ + T (uint8_t, 16) \ + T (int16_t, 16) \ + T (uint16_t, 16) \ + T (_Float16, 16) \ + T (int32_t, 16) \ + T (uint32_t, 16) \ + T (float, 16) \ + T (int64_t, 16) \ + T (uint64_t, 16) \ + T (double, 16) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-7.c new file mode 100644 index 000000000000..729fce09cf9a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-7.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-schedule-insns -fdump-tree-vect-details" } */ + +#include + +#define INDEX32 uint32_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices, INDEX##BITS *restrict cond) \ + { \ + for (int i = 0; i < 128; ++i) \ + if (cond[i]) \ + dest[i] += src[indices[i]]; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 32) \ + T (uint8_t, 32) \ + T (int16_t, 32) \ + T (uint16_t, 32) \ + T (_Float16, 32) \ + T (int32_t, 32) \ + T (uint32_t, 32) \ + T (float, 32) \ + T (int64_t, 32) \ + T (uint64_t, 32) \ + T (double, 32) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-8.c new file mode 100644 index 000000000000..c6f6e88fda32 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-8.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-schedule-insns -fdump-tree-vect-details" } */ + +#include + +#define INDEX32 int32_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices, INDEX##BITS *restrict cond) \ + { \ + for (int i = 0; i < 128; ++i) \ + if (cond[i]) \ + dest[i] += src[indices[i]]; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 32) \ + T (uint8_t, 32) \ + T (int16_t, 32) \ + T (uint16_t, 32) \ + T (_Float16, 32) \ + T (int32_t, 32) \ + T (uint32_t, 32) \ + T (float, 32) \ + T (int64_t, 32) \ + T (uint64_t, 32) \ + T (double, 32) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-9.c new file mode 100644 index 000000000000..3629496e3249 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_32-9.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-schedule-insns -fdump-tree-vect-details" } */ + +#include + +#define INDEX64 uint64_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices, INDEX##BITS *restrict cond) \ + { \ + for (int i = 0; i < 128; ++i) \ + if (cond[i]) \ + dest[i] += src[indices[i]]; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 64) \ + T (uint8_t, 64) \ + T (int16_t, 64) \ + T (uint16_t, 64) \ + T (_Float16, 64) \ + T (int32_t, 64) \ + T (uint32_t, 64) \ + T (float, 64) \ + T (int64_t, 64) \ + T (uint64_t, 64) \ + T (double, 64) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-1.c similarity index 94% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-1.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-1.c index abab3b90af9b..154c53539e37 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-schedule-insns -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-schedule-insns -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-10.c similarity index 94% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-10.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-10.c index 61ab1fb00215..c0fe926287bd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-schedule-insns -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-schedule-insns -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-11.c new file mode 100644 index 000000000000..2a3827344420 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-11.c @@ -0,0 +1,114 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-schedule-insns -fdump-tree-vect-details" } */ + +#include + +#define TEST_LOOP(DATA_TYPE, INDEX_TYPE) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE##_##INDEX_TYPE (DATA_TYPE *restrict y, DATA_TYPE *restrict x, \ + INDEX_TYPE *restrict index, \ + INDEX_TYPE *restrict cond) \ + { \ + for (int i = 0; i < 100; ++i) \ + { \ + if (cond[i * 2]) \ + y[i * 2] = x[index[i * 2]] + 1; \ + if (cond[i * 2 + 1]) \ + y[i * 2 + 1] = x[index[i * 2 + 1]] + 2; \ + } \ + } + +TEST_LOOP (int8_t, int8_t) +TEST_LOOP (uint8_t, int8_t) +TEST_LOOP (int16_t, int8_t) +TEST_LOOP (uint16_t, int8_t) +TEST_LOOP (int32_t, int8_t) +TEST_LOOP (uint32_t, int8_t) +TEST_LOOP (int64_t, int8_t) +TEST_LOOP (uint64_t, int8_t) +TEST_LOOP (_Float16, int8_t) +TEST_LOOP (float, int8_t) +TEST_LOOP (double, int8_t) +TEST_LOOP (int8_t, int16_t) +TEST_LOOP (uint8_t, int16_t) +TEST_LOOP (int16_t, int16_t) +TEST_LOOP (uint16_t, int16_t) +TEST_LOOP (int32_t, int16_t) +TEST_LOOP (uint32_t, int16_t) +TEST_LOOP (int64_t, int16_t) +TEST_LOOP (uint64_t, int16_t) +TEST_LOOP (_Float16, int16_t) +TEST_LOOP (float, int16_t) +TEST_LOOP (double, int16_t) +TEST_LOOP (int8_t, int32_t) +TEST_LOOP (uint8_t, int32_t) +TEST_LOOP (int16_t, int32_t) +TEST_LOOP (uint16_t, int32_t) +TEST_LOOP (int32_t, int32_t) +TEST_LOOP (uint32_t, int32_t) +TEST_LOOP (int64_t, int32_t) +TEST_LOOP (uint64_t, int32_t) +TEST_LOOP (_Float16, int32_t) +TEST_LOOP (float, int32_t) +TEST_LOOP (double, int32_t) +TEST_LOOP (int8_t, int64_t) +TEST_LOOP (uint8_t, int64_t) +TEST_LOOP (int16_t, int64_t) +TEST_LOOP (uint16_t, int64_t) +TEST_LOOP (int32_t, int64_t) +TEST_LOOP (uint32_t, int64_t) +TEST_LOOP (int64_t, int64_t) +TEST_LOOP (uint64_t, int64_t) +TEST_LOOP (_Float16, int64_t) +TEST_LOOP (float, int64_t) +TEST_LOOP (double, int64_t) +TEST_LOOP (int8_t, uint8_t) +TEST_LOOP (uint8_t, uint8_t) +TEST_LOOP (int16_t, uint8_t) +TEST_LOOP (uint16_t, uint8_t) +TEST_LOOP (int32_t, uint8_t) +TEST_LOOP (uint32_t, uint8_t) +TEST_LOOP (int64_t, uint8_t) +TEST_LOOP (uint64_t, uint8_t) +TEST_LOOP (_Float16, uint8_t) +TEST_LOOP (float, uint8_t) +TEST_LOOP (double, uint8_t) +TEST_LOOP (int8_t, uint16_t) +TEST_LOOP (uint8_t, uint16_t) +TEST_LOOP (int16_t, uint16_t) +TEST_LOOP (uint16_t, uint16_t) +TEST_LOOP (int32_t, uint16_t) +TEST_LOOP (uint32_t, uint16_t) +TEST_LOOP (int64_t, uint16_t) +TEST_LOOP (uint64_t, uint16_t) +TEST_LOOP (_Float16, uint16_t) +TEST_LOOP (float, uint16_t) +TEST_LOOP (double, uint16_t) +TEST_LOOP (int8_t, uint32_t) +TEST_LOOP (uint8_t, uint32_t) +TEST_LOOP (int16_t, uint32_t) +TEST_LOOP (uint16_t, uint32_t) +TEST_LOOP (int32_t, uint32_t) +TEST_LOOP (uint32_t, uint32_t) +TEST_LOOP (int64_t, uint32_t) +TEST_LOOP (uint64_t, uint32_t) +TEST_LOOP (_Float16, uint32_t) +TEST_LOOP (float, uint32_t) +TEST_LOOP (double, uint32_t) +TEST_LOOP (int8_t, uint64_t) +TEST_LOOP (uint8_t, uint64_t) +TEST_LOOP (int16_t, uint64_t) +TEST_LOOP (uint16_t, uint64_t) +TEST_LOOP (int32_t, uint64_t) +TEST_LOOP (uint32_t, uint64_t) +TEST_LOOP (int64_t, uint64_t) +TEST_LOOP (uint64_t, uint64_t) +TEST_LOOP (_Float16, uint64_t) +TEST_LOOP (float, uint64_t) +TEST_LOOP (double, uint64_t) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 88 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_GATHER_LOAD" "vect" } } */ +/* { dg-final { scan-assembler-not {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-2.c similarity index 94% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-2.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-2.c index cc5f52e0c34b..b586d64da293 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-schedule-insns -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-schedule-insns -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-3.c similarity index 94% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-3.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-3.c index 311e25ea199b..11818a19e514 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-schedule-insns -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-schedule-insns -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-4.c similarity index 94% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-4.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-4.c index 9223df9c4a2b..3660198f7e58 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-schedule-insns -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-schedule-insns -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-5.c similarity index 94% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-5.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-5.c index 9ec7e60dc68a..30589741e979 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-schedule-insns -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-schedule-insns -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-6.c similarity index 94% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-6.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-6.c index ff18009fba1c..a8cc99ac86a8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-schedule-insns -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-schedule-insns -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-7.c similarity index 94% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-7.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-7.c index fd05df7b3813..9639235475fb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-schedule-insns -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-schedule-insns -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-8.c similarity index 94% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-8.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-8.c index a58c1c220422..a2526eaf72fe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-schedule-insns -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-schedule-insns -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-9.c similarity index 94% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-9.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-9.c index 36947db76ba0..0eb57440b2d5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_64-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fno-schedule-insns -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fno-schedule-insns -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-1.c index fb342859044c..913d2f7a7fe2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-1.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "mask_gather_load-1.c" +#include "mask_gather_load_64-1.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-10.c index 531f298691f4..3336a18d3404 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-10.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "mask_gather_load-10.c" +#include "mask_gather_load_64-10.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-11.c index 0ce20a8394e5..eba0be9c319d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-11.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-mcmodel=medany" } */ -#include "mask_gather_load-11.c" +#include "mask_gather_load_64-11.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-2.c index 8bb78aeaa244..50a94905a3d2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-2.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "mask_gather_load-2.c" +#include "mask_gather_load_64-2.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-3.c index 0472ed0aaeb0..ba93eb8b40a3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-3.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "mask_gather_load-3.c" +#include "mask_gather_load_64-3.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-4.c index 4fab81af2803..d96fc13eda0e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-4.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "mask_gather_load-4.c" +#include "mask_gather_load_64-4.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-5.c index 8db1ea11fd24..05fdae37540f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-5.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "mask_gather_load-5.c" +#include "mask_gather_load_64-5.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-6.c index d58bc80394c4..175ce086bb10 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-6.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "mask_gather_load-6.c" +#include "mask_gather_load_64-6.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-7.c index cc495718b115..5a82541e9ba7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-7.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-mcmodel=medany" } */ -#include "mask_gather_load-7.c" +#include "mask_gather_load_64-7.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-8.c index 47459855135a..4195f26886f1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-8.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-mcmodel=medany" } */ -#include "mask_gather_load-8.c" +#include "mask_gather_load_64-8.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-9.c index 32924f0df704..686d0a5119d4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_gather_load_run-9.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "mask_gather_load-9.c" +#include "mask_gather_load_64-9.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-1.c new file mode 100644 index 000000000000..5b4277654162 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-1.c @@ -0,0 +1,41 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX8 uint8_t +#define INDEX16 uint16_t +#define INDEX32 uint32_t +#define INDEX64 uint64_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices, INDEX##BITS *restrict cond) \ + { \ + for (int i = 0; i < 128; ++i) \ + if (cond[i]) \ + dest[indices[i]] = src[i] + 1; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 8) \ + T (uint8_t, 8) \ + T (int16_t, 16) \ + T (uint16_t, 16) \ + T (_Float16, 16) \ + T (int32_t, 32) \ + T (uint32_t, 32) \ + T (float, 32) \ + T (int64_t, 64) \ + T (uint64_t, 64) \ + T (double, 64) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-10.c new file mode 100644 index 000000000000..d96c96dab2be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-10.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX64 int64_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices, INDEX##BITS *restrict cond) \ + { \ + for (int i = 0; i < 128; ++i) \ + if (cond[i]) \ + dest[indices[i]] = src[i] + 1; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 64) \ + T (uint8_t, 64) \ + T (int16_t, 64) \ + T (uint16_t, 64) \ + T (_Float16, 64) \ + T (int32_t, 64) \ + T (uint32_t, 64) \ + T (float, 64) \ + T (int64_t, 64) \ + T (uint64_t, 64) \ + T (double, 64) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-2.c new file mode 100644 index 000000000000..ca939831d26b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-2.c @@ -0,0 +1,41 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX8 int8_t +#define INDEX16 int16_t +#define INDEX32 int32_t +#define INDEX64 int64_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices, INDEX##BITS *restrict cond) \ + { \ + for (int i = 0; i < 128; ++i) \ + if (cond[i]) \ + dest[indices[i]] = src[i] + 1; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 8) \ + T (uint8_t, 8) \ + T (int16_t, 16) \ + T (uint16_t, 16) \ + T (_Float16, 16) \ + T (int32_t, 32) \ + T (uint32_t, 32) \ + T (float, 32) \ + T (int64_t, 64) \ + T (uint64_t, 64) \ + T (double, 64) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-3.c new file mode 100644 index 000000000000..60f3a66c8add --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-3.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX8 uint8_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices, INDEX##BITS *restrict cond) \ + { \ + for (int i = 0; i < 128; ++i) \ + if (cond[i]) \ + dest[indices[i]] = src[i] + 1; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 8) \ + T (uint8_t, 8) \ + T (int16_t, 8) \ + T (uint16_t, 8) \ + T (_Float16, 8) \ + T (int32_t, 8) \ + T (uint32_t, 8) \ + T (float, 8) \ + T (int64_t, 8) \ + T (uint64_t, 8) \ + T (double, 8) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-4.c new file mode 100644 index 000000000000..36f316df9ade --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-4.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX8 int8_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices, INDEX##BITS *restrict cond) \ + { \ + for (int i = 0; i < 128; ++i) \ + if (cond[i]) \ + dest[indices[i]] = src[i] + 1; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 8) \ + T (uint8_t, 8) \ + T (int16_t, 8) \ + T (uint16_t, 8) \ + T (_Float16, 8) \ + T (int32_t, 8) \ + T (uint32_t, 8) \ + T (float, 8) \ + T (int64_t, 8) \ + T (uint64_t, 8) \ + T (double, 8) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-5.c new file mode 100644 index 000000000000..df58b3dedbc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-5.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX16 uint16_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices, INDEX##BITS *restrict cond) \ + { \ + for (int i = 0; i < 128; ++i) \ + if (cond[i]) \ + dest[indices[i]] = src[i] + 1; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 16) \ + T (uint8_t, 16) \ + T (int16_t, 16) \ + T (uint16_t, 16) \ + T (_Float16, 16) \ + T (int32_t, 16) \ + T (uint32_t, 16) \ + T (float, 16) \ + T (int64_t, 16) \ + T (uint64_t, 16) \ + T (double, 16) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-6.c new file mode 100644 index 000000000000..c2da72ae4a22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-6.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX16 int16_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices, INDEX##BITS *restrict cond) \ + { \ + for (int i = 0; i < 128; ++i) \ + if (cond[i]) \ + dest[indices[i]] = src[i] + 1; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 16) \ + T (uint8_t, 16) \ + T (int16_t, 16) \ + T (uint16_t, 16) \ + T (_Float16, 16) \ + T (int32_t, 16) \ + T (uint32_t, 16) \ + T (float, 16) \ + T (int64_t, 16) \ + T (uint64_t, 16) \ + T (double, 16) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-7.c new file mode 100644 index 000000000000..e6bdd366a96b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-7.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX32 uint32_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices, INDEX##BITS *restrict cond) \ + { \ + for (int i = 0; i < 128; ++i) \ + if (cond[i]) \ + dest[indices[i]] = src[i] + 1; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 32) \ + T (uint8_t, 32) \ + T (int16_t, 32) \ + T (uint16_t, 32) \ + T (_Float16, 32) \ + T (int32_t, 32) \ + T (uint32_t, 32) \ + T (float, 32) \ + T (int64_t, 32) \ + T (uint64_t, 32) \ + T (double, 32) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-8.c new file mode 100644 index 000000000000..3ae681dbea55 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-8.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX32 int32_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices, INDEX##BITS *restrict cond) \ + { \ + for (int i = 0; i < 128; ++i) \ + if (cond[i]) \ + dest[indices[i]] = src[i] + 1; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 32) \ + T (uint8_t, 32) \ + T (int16_t, 32) \ + T (uint16_t, 32) \ + T (_Float16, 32) \ + T (int32_t, 32) \ + T (uint32_t, 32) \ + T (float, 32) \ + T (int64_t, 32) \ + T (uint64_t, 32) \ + T (double, 32) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-9.c new file mode 100644 index 000000000000..be5077f86149 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_32-9.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* For some reason we exceed + the default code model's +-2 GiB limits. We should investigate why and + add a proper description here. For now just make sure the test case + compiles properly. */ +/* { dg-additional-options "-mcmodel=medany" } */ + +#include + +#define INDEX64 uint64_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices, INDEX##BITS *restrict cond) \ + { \ + for (int i = 0; i < 128; ++i) \ + if (cond[i]) \ + dest[indices[i]] = src[i] + 1; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 64) \ + T (uint8_t, 64) \ + T (int16_t, 64) \ + T (uint16_t, 64) \ + T (_Float16, 64) \ + T (int32_t, 64) \ + T (uint32_t, 64) \ + T (float, 64) \ + T (int64_t, 64) \ + T (uint64_t, 64) \ + T (double, 64) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-1.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-1.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-1.c index 0099ed357c48..27c982aa3544 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-10.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-10.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-10.c index 089ec487c478..93f33696a201 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-2.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-2.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-2.c index 57a1acec0995..cbb22507ad35 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-3.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-3.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-3.c index ba89eb35db2c..93a84056b922 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-4.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-4.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-4.c index 2d6499fea56e..c5816e06fddf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-5.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-5.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-5.c index f55db716cd9c..c140d05b15e4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-6.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-6.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-6.c index a7ec2796834f..41a03d31b707 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-7.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-7.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-7.c index b7bd3f415d57..f29ae25e8cc2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-8.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-8.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-8.c index f2ab86519bdc..8d72d98fb491 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-9.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-9.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-9.c index 42ce1c5364fe..dfd9412376d7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_64-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ /* For some reason we exceed the default code model's +-2 GiB limits. We should investigate why and add a proper description here. For now just make sure the test case diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-1.c index cf89555aca37..077bf827df2b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-1.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "mask_scatter_store-1.c" +#include "mask_scatter_store_64-1.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-10.c index 6e5dc5dc0a7c..a1e8df1b71f9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-10.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "mask_scatter_store-10.c" +#include "mask_scatter_store_64-10.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-2.c index 197b44364320..5ee271748832 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-2.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "mask_scatter_store-2.c" +#include "mask_scatter_store_64-2.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-3.c index 81059e4f7dee..b77fb634163b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-3.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "mask_scatter_store-3.c" +#include "mask_scatter_store_64-3.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-4.c index a50b6d2e44e5..0a8b4a5ba537 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-4.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "mask_scatter_store-4.c" +#include "mask_scatter_store_64-4.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-5.c index 645e3a57a6b1..8eca62bcdfab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-5.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "mask_scatter_store-5.c" +#include "mask_scatter_store_64-5.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-6.c index 52032ba1b362..4bcaf426cfe4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-6.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "mask_scatter_store-6.c" +#include "mask_scatter_store_64-6.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-7.c index 38b05958042f..7e4b1d8076be 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-7.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-mcmodel=medany" } */ -#include "mask_scatter_store-7.c" +#include "mask_scatter_store_64-7.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-8.c index fcb311067b0c..0189aa8ea45b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-8.c @@ -5,7 +5,7 @@ compiles properly. */ /* { dg-additional-options "-mcmodel=medany" } */ -#include "mask_scatter_store-8.c" +#include "mask_scatter_store_64-8.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-9.c index c120e681f732..e2a3a8ca4070 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-9.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "mask_scatter_store-9.c" +#include "mask_scatter_store_64-9.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-1.c new file mode 100644 index 000000000000..4ad244b8e83a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-1.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX8 uint8_t +#define INDEX16 uint16_t +#define INDEX32 uint32_t +#define INDEX64 uint64_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices) \ + { \ + for (int i = 0; i < 128; ++i) \ + dest[indices[i]] = src[i] + 1; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 8) \ + T (uint8_t, 8) \ + T (int16_t, 16) \ + T (uint16_t, 16) \ + T (_Float16, 16) \ + T (int32_t, 32) \ + T (uint32_t, 32) \ + T (float, 32) \ + T (int64_t, 64) \ + T (uint64_t, 64) \ + T (double, 64) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 11 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-10.c new file mode 100644 index 000000000000..a44cbc18b684 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-10.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX64 int64_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices) \ + { \ + for (int i = 0; i < 128; ++i) \ + dest[indices[i]] = src[i] + 1; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 64) \ + T (uint8_t, 64) \ + T (int16_t, 64) \ + T (uint16_t, 64) \ + T (_Float16, 64) \ + T (int32_t, 64) \ + T (uint32_t, 64) \ + T (float, 64) \ + T (int64_t, 64) \ + T (uint64_t, 64) \ + T (double, 64) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 11 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-2.c new file mode 100644 index 000000000000..35e970124692 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-2.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX8 uint8_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices) \ + { \ + for (int i = 0; i < 128; ++i) \ + dest[indices[i]] = src[i] + 1; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 8) \ + T (uint8_t, 8) \ + T (int16_t, 8) \ + T (uint16_t, 8) \ + T (_Float16, 8) \ + T (int32_t, 8) \ + T (uint32_t, 8) \ + T (float, 8) \ + T (int64_t, 8) \ + T (uint64_t, 8) \ + T (double, 8) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 11 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-4.c new file mode 100644 index 000000000000..fb72b092b7cf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-4.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX8 int8_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices) \ + { \ + for (int i = 0; i < 128; ++i) \ + dest[indices[i]] = src[i] + 1; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 8) \ + T (uint8_t, 8) \ + T (int16_t, 8) \ + T (uint16_t, 8) \ + T (_Float16, 8) \ + T (int32_t, 8) \ + T (uint32_t, 8) \ + T (float, 8) \ + T (int64_t, 8) \ + T (uint64_t, 8) \ + T (double, 8) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 11 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-5.c new file mode 100644 index 000000000000..7b562bd94a9e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-5.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX16 uint16_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices) \ + { \ + for (int i = 0; i < 128; ++i) \ + dest[indices[i]] = src[i] + 1; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 16) \ + T (uint8_t, 16) \ + T (int16_t, 16) \ + T (uint16_t, 16) \ + T (_Float16, 16) \ + T (int32_t, 16) \ + T (uint32_t, 16) \ + T (float, 16) \ + T (int64_t, 16) \ + T (uint64_t, 16) \ + T (double, 16) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 11 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-6.c new file mode 100644 index 000000000000..67ea0e005f17 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-6.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX16 int16_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices) \ + { \ + for (int i = 0; i < 128; ++i) \ + dest[indices[i]] = src[i] + 1; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 16) \ + T (uint8_t, 16) \ + T (int16_t, 16) \ + T (uint16_t, 16) \ + T (_Float16, 16) \ + T (int32_t, 16) \ + T (uint32_t, 16) \ + T (float, 16) \ + T (int64_t, 16) \ + T (uint64_t, 16) \ + T (double, 16) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 11 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-7.c new file mode 100644 index 000000000000..76f84850b2b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-7.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX32 uint32_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices) \ + { \ + for (int i = 0; i < 128; ++i) \ + dest[indices[i]] = src[i] + 1; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 32) \ + T (uint8_t, 32) \ + T (int16_t, 32) \ + T (uint16_t, 32) \ + T (_Float16, 32) \ + T (int32_t, 32) \ + T (uint32_t, 32) \ + T (float, 32) \ + T (int64_t, 32) \ + T (uint64_t, 32) \ + T (double, 32) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 11 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-8.c new file mode 100644 index 000000000000..e6e49019fb17 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-8.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX32 int32_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices) \ + { \ + for (int i = 0; i < 128; ++i) \ + dest[indices[i]] = src[i] + 1; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 32) \ + T (uint8_t, 32) \ + T (int16_t, 32) \ + T (uint16_t, 32) \ + T (_Float16, 32) \ + T (int32_t, 32) \ + T (uint32_t, 32) \ + T (float, 32) \ + T (int64_t, 32) \ + T (uint64_t, 32) \ + T (double, 32) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 11 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-9.c new file mode 100644 index 000000000000..81eb93525984 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_32-9.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ + +#include + +#define INDEX64 uint64_t + +#define TEST_LOOP(DATA_TYPE, BITS) \ + void __attribute__ ((noinline, noclone)) \ + f_##DATA_TYPE (DATA_TYPE *restrict dest, DATA_TYPE *restrict src, \ + INDEX##BITS *restrict indices) \ + { \ + for (int i = 0; i < 128; ++i) \ + dest[indices[i]] = src[i] + 1; \ + } + +#define TEST_ALL(T) \ + T (int8_t, 64) \ + T (uint8_t, 64) \ + T (int16_t, 64) \ + T (uint16_t, 64) \ + T (_Float16, 64) \ + T (int32_t, 64) \ + T (uint32_t, 64) \ + T (float, 64) \ + T (int64_t, 64) \ + T (uint64_t, 64) \ + T (double, 64) + +TEST_ALL (TEST_LOOP) + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 11 "vect" } } */ +/* { dg-final { scan-tree-dump " \.MASK_LEN_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-tree-dump-not " \.MASK_SCATTER_STORE" "vect" } } */ +/* { dg-final { scan-assembler-not {vluxei64\.v} } } */ +/* { dg-final { scan-assembler-not {vsuxei64\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-1.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-1.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-1.c index 28c4bae01c33..343a3658396c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-10.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-10.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-10.c index 2cd3e7245aaf..76b0b075ba38 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-10.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-2.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-2.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-2.c index ee44f415e8b3..7eb881989b3f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-3.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-3.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-3.c index 899b05f96ffc..47e8ce3e1868 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-4.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-4.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-4.c index ff6d90ce404a..5c51741e8929 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-5.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-5.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-5.c index 212bd2d9d241..cc0b2fe15c47 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-5.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-6.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-6.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-6.c index 4b6b39df814e..3408cbd88d66 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-7.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-7.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-7.c index 2415c69a3b0f..f45c9bc67277 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-7.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-8.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-8.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-8.c index 4c2fcb144289..64fe30548cb6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-9.c similarity index 95% rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-9.c rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-9.c index 0f4f94cc800f..bd1538db0456 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_64-9.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d -fdump-tree-vect-details" } */ +/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -fdump-tree-vect-details" } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-1.c index 91edba70626f..ec1e02045127 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-1.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "scatter_store-1.c" +#include "scatter_store_64-1.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-10.c index 40e34c698d26..d61a37af539d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-10.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "scatter_store-10.c" +#include "scatter_store_64-10.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-2.c index 721c6f6210b1..c1c32008d15e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-2.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-mcmodel=medany" } */ -#include "scatter_store-2.c" +#include "scatter_store_64-2.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-3.c index 8d268a6d1747..8234f84820a9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-3.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "scatter_store-3.c" +#include "scatter_store_64-3.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-4.c index 3931a81cb17e..b137e1d35cf6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-4.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "scatter_store-4.c" +#include "scatter_store_64-4.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-5.c index ff306301457c..1290f871765e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-5.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "scatter_store-5.c" +#include "scatter_store_64-5.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-6.c index a30c47da723b..79b1ea73c8f2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-6.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ -#include "scatter_store-6.c" +#include "scatter_store_64-6.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-7.c index 94ab40470bf7..c204e7cdfcf7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-7.c @@ -5,7 +5,7 @@ compiles properly. */ /* { dg-additional-options "-mcmodel=medany" } */ -#include "scatter_store-7.c" +#include "scatter_store_64-7.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-8.c index 16c1e17d9be7..1dafabafff74 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-8.c @@ -5,7 +5,7 @@ compiles properly. */ /* { dg-additional-options "-mcmodel=medany" } */ -#include "scatter_store-8.c" +#include "scatter_store_64-8.c" #include int diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-9.c index a91b500b3c75..1b37cac71e18 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-9.c @@ -1,7 +1,7 @@ /* { dg-do run { target { riscv_v } } } */ /* { dg-additional-options "-mcmodel=medany" } */ -#include "scatter_store-9.c" +#include "scatter_store_64-9.c" #include int