From: Vineet Gupta Date: Fri, 1 Jan 2016 13:18:40 +0000 (+0530) Subject: ARC: [dts] Add clk feeding into timers to DTs X-Git-Tag: v4.7-rc1~123^2~29 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=b3d6aba8bd92c20b7748ccd82b6fab8ea5081066;p=thirdparty%2Flinux.git ARC: [dts] Add clk feeding into timers to DTs This allows us to introduce timers in DT in next commit The core clk frequency hack in AXS103 platform is also extended, where the core clk feeding into timers is updated in-place in FDT. Cc: Daniel Lezcano Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Vineet Gupta --- diff --git a/arch/arc/boot/dts/axc001.dtsi b/arch/arc/boot/dts/axc001.dtsi index e7a83d19c5a37..40bcecfc36870 100644 --- a/arch/arc/boot/dts/axc001.dtsi +++ b/arch/arc/boot/dts/axc001.dtsi @@ -26,6 +26,12 @@ ranges = <0x00000000 0xf0000000 0x10000000>; + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <750000000>; + }; + core_intc: arc700-intc@cpu { compatible = "snps,arc700-intc"; interrupt-controller; diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi index b0e3ccdf8fc79..cabe0deeb2d88 100644 --- a/arch/arc/boot/dts/axc003.dtsi +++ b/arch/arc/boot/dts/axc003.dtsi @@ -25,6 +25,12 @@ ranges = <0x00000000 0xf0000000 0x10000000>; + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <90000000>; + }; + core_intc: archs-intc@cpu { compatible = "snps,archs-intc"; interrupt-controller; diff --git a/arch/arc/boot/dts/axc003_idu.dtsi b/arch/arc/boot/dts/axc003_idu.dtsi index f87ae409c8ed2..8955881db794e 100644 --- a/arch/arc/boot/dts/axc003_idu.dtsi +++ b/arch/arc/boot/dts/axc003_idu.dtsi @@ -25,6 +25,12 @@ ranges = <0x00000000 0xf0000000 0x10000000>; + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <90000000>; + }; + core_intc: archs-intc@cpu { compatible = "snps,archs-intc"; interrupt-controller; diff --git a/arch/arc/boot/dts/nsim_700.dts b/arch/arc/boot/dts/nsim_700.dts index 987921f711c17..5d5e373e0ebc5 100644 --- a/arch/arc/boot/dts/nsim_700.dts +++ b/arch/arc/boot/dts/nsim_700.dts @@ -32,6 +32,12 @@ /* child and parent address space 1:1 mapped */ ranges; + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <80000000>; + }; + core_intc: interrupt-controller { compatible = "snps,arc700-intc"; interrupt-controller; diff --git a/arch/arc/boot/dts/nsim_hs.dts b/arch/arc/boot/dts/nsim_hs.dts index d2f60f826bd2f..bf05fe5f67b07 100644 --- a/arch/arc/boot/dts/nsim_hs.dts +++ b/arch/arc/boot/dts/nsim_hs.dts @@ -39,6 +39,12 @@ bus addr, parent bus addr, size */ ranges = <0x80000000 0x0 0x80000000 0x80000000>; + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <80000000>; + }; + core_intc: core-interrupt-controller { compatible = "snps,archs-intc"; interrupt-controller; diff --git a/arch/arc/boot/dts/nsim_hs_idu.dts b/arch/arc/boot/dts/nsim_hs_idu.dts index cc82781727a1e..99eabe1a2bf6f 100644 --- a/arch/arc/boot/dts/nsim_hs_idu.dts +++ b/arch/arc/boot/dts/nsim_hs_idu.dts @@ -29,6 +29,12 @@ /* child and parent address space 1:1 mapped */ ranges; + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <80000000>; + }; + core_intc: core-interrupt-controller { compatible = "snps,archs-intc"; interrupt-controller; diff --git a/arch/arc/boot/dts/nsimosci.dts b/arch/arc/boot/dts/nsimosci.dts index d5a6dd9084a81..b5b060adce8a6 100644 --- a/arch/arc/boot/dts/nsimosci.dts +++ b/arch/arc/boot/dts/nsimosci.dts @@ -35,6 +35,12 @@ /* child and parent address space 1:1 mapped */ ranges; + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <20000000>; + }; + core_intc: interrupt-controller { compatible = "snps,arc700-intc"; interrupt-controller; diff --git a/arch/arc/boot/dts/nsimosci_hs.dts b/arch/arc/boot/dts/nsimosci_hs.dts index 983f6915d4aee..325e73090a181 100644 --- a/arch/arc/boot/dts/nsimosci_hs.dts +++ b/arch/arc/boot/dts/nsimosci_hs.dts @@ -35,6 +35,12 @@ /* child and parent address space 1:1 mapped */ ranges; + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <20000000>; + }; + core_intc: core-interrupt-controller { compatible = "snps,archs-intc"; interrupt-controller; diff --git a/arch/arc/boot/dts/nsimosci_hs_idu.dts b/arch/arc/boot/dts/nsimosci_hs_idu.dts index fd675303f7923..ee03d71265816 100644 --- a/arch/arc/boot/dts/nsimosci_hs_idu.dts +++ b/arch/arc/boot/dts/nsimosci_hs_idu.dts @@ -33,6 +33,12 @@ /* child and parent address space 1:1 mapped */ ranges; + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <5000000>; + }; + core_intc: core-interrupt-controller { compatible = "snps,archs-intc"; interrupt-controller; diff --git a/arch/arc/boot/dts/vdk_axc003.dtsi b/arch/arc/boot/dts/vdk_axc003.dtsi index 035759ee62a51..ad4ee43bd2ac7 100644 --- a/arch/arc/boot/dts/vdk_axc003.dtsi +++ b/arch/arc/boot/dts/vdk_axc003.dtsi @@ -25,6 +25,12 @@ ranges = <0x00000000 0xf0000000 0x10000000>; + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + core_intc: archs-intc@cpu { compatible = "snps,archs-intc"; interrupt-controller; diff --git a/arch/arc/boot/dts/vdk_axc003_idu.dtsi b/arch/arc/boot/dts/vdk_axc003_idu.dtsi index 90e18f4048890..a3cb6263c581e 100644 --- a/arch/arc/boot/dts/vdk_axc003_idu.dtsi +++ b/arch/arc/boot/dts/vdk_axc003_idu.dtsi @@ -26,6 +26,12 @@ ranges = <0x00000000 0xf0000000 0x10000000>; + core_clk: core_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + core_intc: archs-intc@cpu { compatible = "snps,archs-intc"; interrupt-controller; diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c index 8e7f50a8b8577..f90fac271d166 100644 --- a/arch/arc/plat-axs10x/axs10x.c +++ b/arch/arc/plat-axs10x/axs10x.c @@ -14,7 +14,9 @@ * */ +#include #include +#include #include #include @@ -389,7 +391,12 @@ axs103_set_freq(unsigned int id, unsigned int fd, unsigned int od) static void __init axs103_early_init(void) { - u32 freq = arc_get_core_freq(), orig = freq; + int offset = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk"); + const struct fdt_property *prop = fdt_get_property(initial_boot_params, + offset, + "clock-frequency", + NULL); + u32 freq = be32_to_cpu(*(u32*)(prop->data)) / 1000000, orig = freq; /* * AXS103 configurations for SMP/QUAD configurations share device tree @@ -438,8 +445,13 @@ static void __init axs103_early_init(void) } pr_info("Freq is %dMHz\n", freq); + + /* Patching .dtb in-place with new core clock value */ if (freq != orig ) { arc_set_core_freq(freq * 1000000); + freq = cpu_to_be32(freq * 1000000); + fdt_setprop_inplace(initial_boot_params, offset, + "clock-frequency", &freq, sizeof(freq)); } /* Memory maps already config in pre-bootloader */