From: drh <drh@noemail.net>
Date: Tue, 24 Dec 2019 21:42:22 +0000 (+0000)
Subject: Fix a minor performance regression from check-in [401c9d30e06191d9]
X-Git-Tag: version-3.31.0~152
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=b44fec68a53b88612d1d0954eecaa638674764a4;p=thirdparty%2Fsqlite.git

Fix a minor performance regression from check-in [401c9d30e06191d9]

FossilOrigin-Name: 76f54ee86777cbf530654323c953388ef64d0608516722d2522be6c859fa1382
---

diff --git a/manifest b/manifest
index 7f3882aa04..405691aeec 100644
--- a/manifest
+++ b/manifest
@@ -1,5 +1,5 @@
-C Backout\sthe\searly\sVTable\scursor\sclose\schange\sfrom\syesterday,\sas\sYongheng\sand\nRui\shave\sfound\sa\stest\scase\sfor\swhich\sit\sfails.\s\sThe\snew\stest\scase\sis\sadded\nto\sfuzzcheck.
-D 2019-12-24T21:01:37.072
+C Fix\sa\sminor\sperformance\sregression\sfrom\scheck-in\s[401c9d30e06191d9]
+D 2019-12-24T21:42:22.593
 F .fossil-settings/empty-dirs dbb81e8fc0401ac46a1491ab34a7f2c7c0452f2f06b54ebb845d024ca8283ef1
 F .fossil-settings/ignore-glob 35175cdfcf539b2318cb04a9901442804be81cd677d8b889fcc9149c21f239ea
 F LICENSE.md df5091916dbb40e6e9686186587125e1b2ff51f022cc334e886c19a0e9982724
@@ -599,7 +599,7 @@ F src/upsert.c b445315c8958d8f17ec3297d06842e61dacaad0633ccaec1e4e160de7e562212
 F src/utf.c 2f0fac345c7660d5c5bd3df9e9d8d33d4c27f366bcfb09e07443064d751a0507
 F src/util.c 2c92bc706bbdb1c45a25180291e7e05a56e297aa5dd7b2bcd2b1c47e8bb05b17
 F src/vacuum.c 82dcec9e7b1afa980288718ad11bc499651c722d7b9f32933c4d694d91cb6ebf
-F src/vdbe.c 8691c41f61e27f2f36c3c6559ab5aa32a7d552c4fedf1d618f24dd7a58670a8b
+F src/vdbe.c 8b0f3445b75be6aa381a961a3206decf6e169c5b5625349fcb7e287e9deffa14
 F src/vdbe.h 3f068f00b23aebf392df142312ab5874588371c6d83e60d953f6d6b6453491c5
 F src/vdbeInt.h 1ccaf470287e2d153b16cf7b0274d436db2c2f74cdf14afd1a0ff4cb51548ae6
 F src/vdbeapi.c 1252d80c548711e47a6d84dae88ed4e95d3fbb4e7bd0eaa1347299af7efddf02
@@ -1852,8 +1852,7 @@ F vsixtest/vsixtest.tcl 6a9a6ab600c25a91a7acc6293828957a386a8a93
 F vsixtest/vsixtest.vcxproj.data 2ed517e100c66dc455b492e1a33350c1b20fbcdc
 F vsixtest/vsixtest.vcxproj.filters 37e51ffedcdb064aad6ff33b6148725226cd608e
 F vsixtest/vsixtest_TemporaryKey.pfx e5b1b036facdb453873e7084e1cae9102ccc67a0
-P bae060f382e4386c0793db4aa280fe9cd4893307d17a1801a17218ae4dc031c2
-Q -eb95dac7f6482c36853a23234c5ce7af37c7beed8e3675d6a49c4d3a8307e076
-R 056e130351576a95134652be2c0d73eb
+P ddb10f0374e66886d0681937b14cf0b4f100f03d3955b45b6c508dc6d9e36976
+R 5b1079c8a384ce37450b3fecba55c04d
 U drh
-Z 0627f3ed229bfb4c9422500dce5b2813
+Z b050346f80259aa216b8caa58ba47eb4
diff --git a/manifest.uuid b/manifest.uuid
index d75c569f0c..7fc9e7916d 100644
--- a/manifest.uuid
+++ b/manifest.uuid
@@ -1 +1 @@
-ddb10f0374e66886d0681937b14cf0b4f100f03d3955b45b6c508dc6d9e36976
\ No newline at end of file
+76f54ee86777cbf530654323c953388ef64d0608516722d2522be6c859fa1382
\ No newline at end of file
diff --git a/src/vdbe.c b/src/vdbe.c
index 05e26e57da..d1416028b2 100644
--- a/src/vdbe.c
+++ b/src/vdbe.c
@@ -2052,11 +2052,9 @@ case OP_Ge: {             /* same as TK_GE, jump, in1, in3 */
         sqlite3VdbeMemStringify(pIn1, encoding, 1);
         testcase( (flags1&MEM_Dyn) != (pIn1->flags&MEM_Dyn) );
         flags1 = (pIn1->flags & ~MEM_TypeMask) | (flags1 & MEM_TypeMask);
+        if( pIn1==pIn3 ) flags3 = flags1 | MEM_Str;
       }
-      if( (flags3 & MEM_Str)==0
-       && (flags3&(MEM_Int|MEM_Real|MEM_IntReal))!=0
-       && pIn1!=pIn3
-      ){
+      if( (flags3 & MEM_Str)==0 && (flags3&(MEM_Int|MEM_Real|MEM_IntReal))!=0 ){
         testcase( pIn3->flags & MEM_Int );
         testcase( pIn3->flags & MEM_Real );
         testcase( pIn3->flags & MEM_IntReal );
@@ -2089,10 +2087,10 @@ compare_op:
   }
 
   /* Undo any changes made by applyAffinity() to the input registers. */
-  assert( (pIn1->flags & MEM_Dyn) == (flags1 & MEM_Dyn) );
-  pIn1->flags = flags1;
   assert( (pIn3->flags & MEM_Dyn) == (flags3 & MEM_Dyn) );
   pIn3->flags = flags3;
+  assert( (pIn1->flags & MEM_Dyn) == (flags1 & MEM_Dyn) );
+  pIn1->flags = flags1;
 
   if( pOp->p5 & SQLITE_STOREP2 ){
     pOut = &aMem[pOp->p2];