From: gerald <gerald@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Sun, 5 Feb 2017 11:09:18 +0000 (+0000)
Subject: 	* doc/extend.texi (x86 specific memory model extensions for
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=b5b43f09a44e61693c9123278ebc52d3e70672d7;p=thirdparty%2Fgcc.git

	* doc/extend.texi (x86 specific memory model extensions for
	transactional memory): Simplify a phrase.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@245189 138bc75d-0d04-0410-961f-82ee72b054a4
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9e751381511d..e0d251dbcdc3 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2017-02-05  Gerald Pfeifer  <gerald@pfeifer.com>
+
+	* doc/extend.texi (x86 specific memory model extensions for
+	transactional memory): Simplify a phrase.
+
 2017-02-05  Eric Botcazou  <ebotcazou@adacore.com>
 
 	PR target/79353
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 20eba822d545..24e505387360 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -10103,7 +10103,7 @@ after addition, conditional jump on carry etc.
 @section x86-Specific Memory Model Extensions for Transactional Memory
 
 The x86 architecture supports additional memory ordering flags
-to mark lock critical sections for hardware lock elision. 
+to mark critical sections for hardware lock elision. 
 These must be specified in addition to an existing memory order to
 atomic intrinsics.