From: Richard Henderson <richard.henderson@linaro.org>
Date: Fri, 4 Jul 2025 14:20:40 +0000 (-0600)
Subject: target/arm: Enable PSEL for SVE2p1
X-Git-Tag: v10.1.0-rc0~29^2~30
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=b61f4530535a483688e76a925f6203fa22e332e8;p=thirdparty%2Fqemu.git

target/arm: Enable PSEL for SVE2p1

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250704142112.1018902-78-richard.henderson@linaro.org
This instruction is present in both SME(1) and SVE2.1 extensions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---

diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index 62d3e2efd69..cb60b533e9f 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -7273,7 +7273,7 @@ static bool trans_PSEL(DisasContext *s, arg_psel *a)
     TCGv_i64 tmp, didx, dbit;
     TCGv_ptr ptr;
 
-    if (!dc_isar_feature(aa64_sme, s)) {
+    if (!dc_isar_feature(aa64_sme_or_sve2p1, s)) {
         return false;
     }
     if (!sve_access_check(s)) {