From: Imre Deak Date: Wed, 30 Oct 2024 19:23:13 +0000 (+0200) Subject: drm/i915/adlp+/dp_mst: Align master transcoder disabling with spec wrt. DP2 config X-Git-Tag: v6.14-rc1~174^2~12^2~156 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=b63937da16d332fb805f9dcde8b57ea2a767f18e;p=thirdparty%2Fkernel%2Flinux.git drm/i915/adlp+/dp_mst: Align master transcoder disabling with spec wrt. DP2 config On ADLP+ during modeset disabling, disable the DP2 configuration for MST master transcoders as required by the specification. Bspec: 55424, 54128, 65448, 68849 Reviewed-by: Luca Coelho Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20241030192313.4030617-6-imre.deak@intel.com --- diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 3198353bbb01d..769bd1f26db28 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3097,6 +3097,8 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); + intel_ddi_config_transcoder_dp2(old_crtc_state, false); + /* * From TGL spec: "If single stream or multi-stream master transcoder: * Configure Transcoder Clock select to direct no clock to the