From: Tao Zhou Date: Thu, 3 Apr 2025 03:39:49 +0000 (+0800) Subject: drm/amdgpu: add loop bits for NPS2 page retirement X-Git-Tag: v6.16-rc1~144^2~10^2~347 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=b695dd3bb8e806916ba64a62fae918c60004cc4d;p=thirdparty%2Fkernel%2Flinux.git drm/amdgpu: add loop bits for NPS2 page retirement Support NPS2 RAS. Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c index 0e404c0749753..da00d6b3b6a38 100644 --- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c @@ -220,6 +220,13 @@ static int umc_v12_0_convert_error_address(struct amdgpu_device *adev, nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); /* other nps modes are taken as nps1 */ + if (nps == AMDGPU_NPS2_PARTITION_MODE) { + loop_bits[0] = UMC_V12_0_PA_CH5_BIT; + loop_bits[1] = UMC_V12_0_PA_C2_BIT; + loop_bits[2] = UMC_V12_0_PA_B1_BIT; + loop_bits[3] = UMC_V12_0_PA_R12_BIT; + } + if (nps == AMDGPU_NPS4_PARTITION_MODE) { loop_bits[0] = UMC_V12_0_PA_CH4_BIT; loop_bits[1] = UMC_V12_0_PA_CH5_BIT; @@ -517,6 +524,9 @@ static int umc_v12_0_update_ecc_status(struct amdgpu_device *adev, if (adev->gmc.gmc_funcs->query_mem_partition_mode) nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); + + if (nps == AMDGPU_NPS2_PARTITION_MODE) + shift_bit = UMC_V12_0_PA_B1_BIT; if (nps == AMDGPU_NPS4_PARTITION_MODE) shift_bit = UMC_V12_0_PA_B0_BIT; diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h index 9298018d938f7..056bbc0383120 100644 --- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h +++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.h @@ -65,12 +65,14 @@ /* row bits in SOC physical address */ #define UMC_V12_0_PA_R0_BIT 22 #define UMC_V12_0_PA_R11_BIT 33 +#define UMC_V12_0_PA_R12_BIT 34 #define UMC_V12_0_PA_R13_BIT 35 /* channel bit in SOC physical address */ #define UMC_V12_0_PA_CH4_BIT 12 #define UMC_V12_0_PA_CH5_BIT 13 /* bank bit in SOC physical address */ #define UMC_V12_0_PA_B0_BIT 19 +#define UMC_V12_0_PA_B1_BIT 20 /* row bits in MCA address */ #define UMC_V12_0_MA_R0_BIT 10