From: Sasha Levin Date: Tue, 6 Aug 2019 21:32:05 +0000 (-0400) Subject: fixes for 4.4 X-Git-Tag: v5.2.8~37 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=b6b0f712c86473481c50c57111a8ce51e50b0770;p=thirdparty%2Fkernel%2Fstable-queue.git fixes for 4.4 Signed-off-by: Sasha Levin --- diff --git a/queue-4.4/arm64-cpufeature-fix-ctr_el0-field-definitions.patch b/queue-4.4/arm64-cpufeature-fix-ctr_el0-field-definitions.patch new file mode 100644 index 00000000000..81f448749bf --- /dev/null +++ b/queue-4.4/arm64-cpufeature-fix-ctr_el0-field-definitions.patch @@ -0,0 +1,51 @@ +From 8f073bcadacf1a567420960e78aa990ee7e9ebc9 Mon Sep 17 00:00:00 2001 +From: Will Deacon +Date: Mon, 5 Aug 2019 18:13:07 +0100 +Subject: arm64: cpufeature: Fix CTR_EL0 field definitions + +commit be68a8aaf925aaf35574260bf820bb09d2f9e07f upstream. + +Our field definitions for CTR_EL0 suffer from a number of problems: + + - The IDC and DIC fields are missing, which causes us to enable CTR + trapping on CPUs with either of these returning non-zero values. + + - The ERG is FTR_LOWER_SAFE, whereas it should be treated like CWG as + FTR_HIGHER_SAFE so that applications can use it to avoid false sharing. + + - [nit] A RES1 field is described as "RAO" + +This patch updates the CTR_EL0 field definitions to fix these issues. + +Cc: # 4.4.y only +Cc: Shanker Donthineni +Signed-off-by: Will Deacon +Signed-off-by: Will Deacon +Signed-off-by: Sasha Levin +--- + arch/arm64/kernel/cpufeature.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c +index c1eddc07d9968..fff0bf2f889e1 100644 +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -126,10 +126,12 @@ static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { + }; + + static struct arm64_ftr_bits ftr_ctr[] = { +- U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */ +- ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 28, 3, 0), ++ U_ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ ++ ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 30, 1, 0), ++ U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 29, 1, 1), /* DIC */ ++ U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 1, 1), /* IDC */ + U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */ +- U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */ ++ U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 20, 4, 0), /* ERG */ + U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */ + /* + * Linux can handle differing I-cache policies. Userspace JITs will +-- +2.20.1 + diff --git a/queue-4.4/arm64-cpufeature-fix-feature-comparison-for-ctr_el0..patch b/queue-4.4/arm64-cpufeature-fix-feature-comparison-for-ctr_el0..patch new file mode 100644 index 00000000000..16d28997df3 --- /dev/null +++ b/queue-4.4/arm64-cpufeature-fix-feature-comparison-for-ctr_el0..patch @@ -0,0 +1,74 @@ +From f21e9bdd0b52e58a05da337abe34bfd195b791c0 Mon Sep 17 00:00:00 2001 +From: Will Deacon +Date: Mon, 5 Aug 2019 18:13:08 +0100 +Subject: arm64: cpufeature: Fix feature comparison for CTR_EL0.{CWG,ERG} + +commit 147b9635e6347104b91f48ca9dca61eb0fbf2a54 upstream. + +If CTR_EL0.{CWG,ERG} are 0b0000 then they must be interpreted to have +their architecturally maximum values, which defeats the use of +FTR_HIGHER_SAFE when sanitising CPU ID registers on heterogeneous +machines. + +Introduce FTR_HIGHER_OR_ZERO_SAFE so that these fields effectively +saturate at zero. + +Fixes: 3c739b571084 ("arm64: Keep track of CPU feature registers") +Cc: # 4.4.y only +Reviewed-by: Suzuki K Poulose +Acked-by: Mark Rutland +Signed-off-by: Will Deacon +Signed-off-by: Catalin Marinas +Signed-off-by: Sasha Levin +--- + arch/arm64/include/asm/cpufeature.h | 7 ++++--- + arch/arm64/kernel/cpufeature.c | 8 ++++++-- + 2 files changed, 10 insertions(+), 5 deletions(-) + +diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h +index ad83c245781c3..0a66f8241f185 100644 +--- a/arch/arm64/include/asm/cpufeature.h ++++ b/arch/arm64/include/asm/cpufeature.h +@@ -41,9 +41,10 @@ + + /* CPU feature register tracking */ + enum ftr_type { +- FTR_EXACT, /* Use a predefined safe value */ +- FTR_LOWER_SAFE, /* Smaller value is safe */ +- FTR_HIGHER_SAFE,/* Bigger value is safe */ ++ FTR_EXACT, /* Use a predefined safe value */ ++ FTR_LOWER_SAFE, /* Smaller value is safe */ ++ FTR_HIGHER_SAFE, /* Bigger value is safe */ ++ FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */ + }; + + #define FTR_STRICT true /* SANITY check strict matching required */ +diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c +index fff0bf2f889e1..062484d344509 100644 +--- a/arch/arm64/kernel/cpufeature.c ++++ b/arch/arm64/kernel/cpufeature.c +@@ -130,8 +130,8 @@ static struct arm64_ftr_bits ftr_ctr[] = { + ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, 30, 1, 0), + U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 29, 1, 1), /* DIC */ + U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 28, 1, 1), /* IDC */ +- U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */ +- U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_SAFE, 20, 4, 0), /* ERG */ ++ U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 24, 4, 0), /* CWG */ ++ U_ARM64_FTR_BITS(FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 20, 4, 0), /* ERG */ + U_ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */ + /* + * Linux can handle differing I-cache policies. Userspace JITs will +@@ -341,6 +341,10 @@ static s64 arm64_ftr_safe_value(struct arm64_ftr_bits *ftrp, s64 new, s64 cur) + case FTR_LOWER_SAFE: + ret = new < cur ? new : cur; + break; ++ case FTR_HIGHER_OR_ZERO_SAFE: ++ if (!cur || !new) ++ break; ++ /* Fallthrough */ + case FTR_HIGHER_SAFE: + ret = new > cur ? new : cur; + break; +-- +2.20.1 + diff --git a/queue-4.4/series b/queue-4.4/series new file mode 100644 index 00000000000..ff0e2a29cb0 --- /dev/null +++ b/queue-4.4/series @@ -0,0 +1,2 @@ +arm64-cpufeature-fix-ctr_el0-field-definitions.patch +arm64-cpufeature-fix-feature-comparison-for-ctr_el0..patch