From: Greg Kroah-Hartman Date: Mon, 30 Jul 2018 12:22:12 +0000 (+0200) Subject: drop some more patches X-Git-Tag: v4.17.12~8 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=b6b4e7f0286126f083894123dbb8b8d7b08b2260;p=thirdparty%2Fkernel%2Fstable-queue.git drop some more patches --- diff --git a/queue-4.14/drm-tilcdc-fix-setting-clock-divider-for-omap-l138.patch b/queue-4.14/drm-tilcdc-fix-setting-clock-divider-for-omap-l138.patch deleted file mode 100644 index cfdbbb9b56e..00000000000 --- a/queue-4.14/drm-tilcdc-fix-setting-clock-divider-for-omap-l138.patch +++ /dev/null @@ -1,41 +0,0 @@ -From foo@baz Sat Jul 28 10:25:26 CEST 2018 -From: David Lechner -Date: Wed, 14 Mar 2018 17:58:45 -0500 -Subject: drm/tilcdc: Fix setting clock divider for omap-l138 - -From: David Lechner - -[ Upstream commit a88ad3ded15daa0389106779c60b8a5e76d4b20a ] - -This fixes setting the clock divider on the TI OMAP-L138 LCDK board. - -The clock drivers for OMAP-L138 are being covernted to the common clock -framework. When this happens, clk_set_rate() will no longer return an -error. However, on this SoC, the clock rate cannot actually be changed -because the clock has to maintain a fixed ratio to the ARM clock. So -after attempting to set the clock rate, we need to check to see if the -new rate is actually close enough. If not, then follow the previous -error path to adjust the divider in LCDC IP block to compensate for not -being able to change the parent clock rate. - -Tested working on a TI OMAP-L138 LCDK board. - -Signed-off-by: David Lechner -Signed-off-by: Jyri Sarha -Signed-off-by: Sasha Levin -Signed-off-by: Greg Kroah-Hartman ---- - drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c -+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c -@@ -246,7 +246,7 @@ static void tilcdc_crtc_set_clk(struct d - - ret = clk_set_rate(priv->clk, req_rate * clkdiv); - clk_rate = clk_get_rate(priv->clk); -- if (ret < 0) { -+ if (ret < 0 || tilcdc_pclk_diff(req_rate, clk_rate) > 5) { - /* - * If we fail to set the clock rate (some architectures don't - * use the common clock framework yet and may not implement diff --git a/queue-4.14/series b/queue-4.14/series index 1e4d9e962b9..c3e1e42f901 100644 --- a/queue-4.14/series +++ b/queue-4.14/series @@ -152,7 +152,6 @@ libata-fix-command-retry-decision.patch acpi-lpss-only-call-pwm_add_table-for-bay-trail-pwm-if-pmic-hrv-is-2.patch media-media-device-fix-ioctl-function-types.patch media-saa7164-fix-driver-name-in-debug-output.patch -drm-tilcdc-fix-setting-clock-divider-for-omap-l138.patch mtd-rawnand-fsl_ifc-fix-fsl-nand-driver-to-read-all-onfi-parameter-pages.patch brcmfmac-add-support-for-bcm43364-wireless-chipset.patch s390-cpum_sf-add-data-entry-sizes-to-sampling-trailer-entry.patch diff --git a/queue-4.17/clk-davinci-psc-da830-fix-usb0-48mhz-phy-clock-registration.patch b/queue-4.17/clk-davinci-psc-da830-fix-usb0-48mhz-phy-clock-registration.patch deleted file mode 100644 index 5714dc65dd4..00000000000 --- a/queue-4.17/clk-davinci-psc-da830-fix-usb0-48mhz-phy-clock-registration.patch +++ /dev/null @@ -1,37 +0,0 @@ -From foo@baz Sat Jul 28 10:14:30 CEST 2018 -From: Sekhar Nori -Date: Mon, 7 May 2018 17:04:57 +0530 -Subject: clk: davinci: psc-da830: fix USB0 48MHz PHY clock registration - -From: Sekhar Nori - -[ Upstream commit a714dceb721407c2a5d2887938f37e34ed00669c ] - -USB0 48MHz PHY clock registration fails on DA830 because the -da8xx-cfgchip clock driver cannot get a reference to USB0 -LPSC clock. - -The USB0 LPSC needs to be enabled during PHY clock enable. Setup -the clock lookup correctly to fix this. - -Signed-off-by: Sekhar Nori -Reviewed-by: David Lechner -Signed-off-by: Stephen Boyd -Signed-off-by: Sasha Levin -Signed-off-by: Greg Kroah-Hartman ---- - drivers/clk/davinci/psc-da830.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - ---- a/drivers/clk/davinci/psc-da830.c -+++ b/drivers/clk/davinci/psc-da830.c -@@ -55,7 +55,8 @@ const struct davinci_psc_init_data da830 - .psc_init = &da830_psc0_init, - }; - --LPSC_CLKDEV2(usb0_clkdev, NULL, "musb-da8xx", -+LPSC_CLKDEV3(usb0_clkdev, "fck", "da830-usb-phy-clks", -+ NULL, "musb-da8xx", - NULL, "cppi41-dmaengine"); - LPSC_CLKDEV1(usb1_clkdev, NULL, "ohci-da8xx"); - /* REVISIT: gpio-davinci.c should be modified to drop con_id */ diff --git a/queue-4.17/drm-tilcdc-fix-setting-clock-divider-for-omap-l138.patch b/queue-4.17/drm-tilcdc-fix-setting-clock-divider-for-omap-l138.patch deleted file mode 100644 index 79b8b06fa0e..00000000000 --- a/queue-4.17/drm-tilcdc-fix-setting-clock-divider-for-omap-l138.patch +++ /dev/null @@ -1,41 +0,0 @@ -From foo@baz Sat Jul 28 10:14:30 CEST 2018 -From: David Lechner -Date: Wed, 14 Mar 2018 17:58:45 -0500 -Subject: drm/tilcdc: Fix setting clock divider for omap-l138 - -From: David Lechner - -[ Upstream commit a88ad3ded15daa0389106779c60b8a5e76d4b20a ] - -This fixes setting the clock divider on the TI OMAP-L138 LCDK board. - -The clock drivers for OMAP-L138 are being covernted to the common clock -framework. When this happens, clk_set_rate() will no longer return an -error. However, on this SoC, the clock rate cannot actually be changed -because the clock has to maintain a fixed ratio to the ARM clock. So -after attempting to set the clock rate, we need to check to see if the -new rate is actually close enough. If not, then follow the previous -error path to adjust the divider in LCDC IP block to compensate for not -being able to change the parent clock rate. - -Tested working on a TI OMAP-L138 LCDK board. - -Signed-off-by: David Lechner -Signed-off-by: Jyri Sarha -Signed-off-by: Sasha Levin -Signed-off-by: Greg Kroah-Hartman ---- - drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c -+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c -@@ -224,7 +224,7 @@ static void tilcdc_crtc_set_clk(struct d - - ret = clk_set_rate(priv->clk, req_rate * clkdiv); - clk_rate = clk_get_rate(priv->clk); -- if (ret < 0) { -+ if (ret < 0 || tilcdc_pclk_diff(req_rate, clk_rate) > 5) { - /* - * If we fail to set the clock rate (some architectures don't - * use the common clock framework yet and may not implement diff --git a/queue-4.17/series b/queue-4.17/series index db75b8abc8b..e463000d0d4 100644 --- a/queue-4.17/series +++ b/queue-4.17/series @@ -176,7 +176,6 @@ media-staging-atomisp-comment-out-several-unused-sensor-resolutions.patch arm64-cmpwait-clear-event-register-before-arming-exclusive-monitor.patch hid-hid-plantronics-re-resend-update-to-map-button-for-ptt-products.patch arm64-dts-renesas-salvator-common-use-audio-graph-card-for-sound.patch -clk-davinci-psc-da830-fix-usb0-48mhz-phy-clock-registration.patch drm-amd-display-remove-need-of-modeset-flag-for-overlay-planes-v2.patch drm-radeon-fix-mode_valid-s-return-type.patch drm-amdgpu-remove-vram-from-shared-bo-domains.patch @@ -203,7 +202,6 @@ media-media-device-fix-ioctl-function-types.patch media-saa7164-fix-driver-name-in-debug-output.patch media-renesas-ceu-set-mbus_fmt-on-subdev-operations.patch media-em28xx-fix-dualhd-broken-second-tuner.patch -drm-tilcdc-fix-setting-clock-divider-for-omap-l138.patch mtd-rawnand-fsl_ifc-fix-fsl-nand-driver-to-read-all-onfi-parameter-pages.patch brcmfmac-add-support-for-bcm43364-wireless-chipset.patch s390-cpum_sf-add-data-entry-sizes-to-sampling-trailer-entry.patch