From: Weiwei Li <liweiwei@iscas.ac.cn>
Date: Fri, 4 Feb 2022 02:26:55 +0000 (+0800)
Subject: target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE
X-Git-Tag: v7.0.0-rc0~51^2~4
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=b6ecc63c569bb88c0fcadf79fb92bf4b88aefea8;p=thirdparty%2Fqemu.git

target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE

For non-leaf PTEs, the D, A, and U bits are reserved for future standard use.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220204022658.18097-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 7df4569526a..25ebc767255 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -937,6 +937,9 @@ restart:
             return TRANSLATE_FAIL;
         } else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
             /* Inner PTE, continue walking */
+            if (pte & (PTE_D | PTE_A | PTE_U)) {
+                return TRANSLATE_FAIL;
+            }
             base = ppn << PGSHIFT;
         } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
             /* Reserved leaf PTE flags: PTE_W */