From: Ricky CX Wu Date: Tue, 24 Sep 2024 09:44:29 +0000 (+0800) Subject: ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode X-Git-Tag: v6.14-rc1~103^2^2~34 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=b7b71409c9b9ec4607563e87f695bfccd7e7e350;p=thirdparty%2Fkernel%2Flinux.git ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode Revise quad mode to dual mode to keep the write protect feature for the SPI flash because the WP pin is the same pin with IO2 pin in quad mode. Signed-off-by: Ricky CX Wu Signed-off-by: Delphine CC Chiu Link: https://patch.msgid.link/20240924094430.272074-2-Delphine_CC_Chiu@wiwynn.com Signed-off-by: Andrew Jeffery --- diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts index b31ee5d6294ec..0ae00e07d1b4e 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts @@ -130,7 +130,8 @@ status = "okay"; m25p,fast-read; label = "bmc"; - spi-rx-bus-width = <4>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; spi-max-frequency = <50000000>; #include "openbmc-flash-layout-64.dtsi" }; @@ -138,7 +139,8 @@ status = "okay"; m25p,fast-read; label = "bmc2"; - spi-rx-bus-width = <4>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; spi-max-frequency = <50000000>; }; };