From: Marek Vasut Date: Tue, 12 Nov 2024 01:37:35 +0000 (+0100) Subject: clk: imx: pll14xx: Add 208 MHz and 416 MHz entries for PLL1416x X-Git-Tag: v6.14-rc1~150^2~2^5^2~4 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=b7f67545ca9fa13f6e12debd68a92c1c664e2e3b;p=thirdparty%2Fkernel%2Flinux.git clk: imx: pll14xx: Add 208 MHz and 416 MHz entries for PLL1416x The PLL1416x is used to implement SYS_PLL3 on i.MX8MP and can be used to drive CLKOUTn clock. Add 208 MHz and 416 MHz entries to the PLL so they can be generated by the PLL and used to produce e.g. 13 MHz or 26 MHz on CLKOUTn output. Signed-off-by: Marek Vasut Reviewed-by: Peng Fan Link: https://lore.kernel.org/r/20241112013805.333798-1-marex@denx.de Signed-off-by: Abel Vesa --- diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index d63564dbb12ca..f290981ea13bd 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -56,7 +56,9 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = { PLL_1416X_RATE(700000000U, 350, 3, 2), PLL_1416X_RATE(640000000U, 320, 3, 2), PLL_1416X_RATE(600000000U, 300, 3, 2), + PLL_1416X_RATE(416000000U, 208, 3, 2), PLL_1416X_RATE(320000000U, 160, 3, 2), + PLL_1416X_RATE(208000000U, 208, 3, 3), }; static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {