From: Paul Barker Date: Wed, 20 Mar 2024 08:28:30 +0000 (+0000) Subject: clk: renesas: r9a07g043: Mark mod_clks and resets arrays as const X-Git-Tag: v6.10-rc1~112^2~2^3~2^2~3 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=b8ae9d344d09b73361493054fbde15b9f5ebe91a;p=thirdparty%2Fkernel%2Flinux.git clk: renesas: r9a07g043: Mark mod_clks and resets arrays as const The r9a07g043_mod_clks and r9a07g043_resets arrays describe the module clocks and reset signals (respectively) in this SoC and do not change at runtime. Signed-off-by: Paul Barker Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240320082831.9666-1-paul.barker.ct@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index 33532673d25d7..e36d2ec2c0f54 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -149,7 +149,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { #endif }; -static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { +static const struct rzg2l_mod_clk r9a07g043_mod_clks[] = { #ifdef CONFIG_ARM64 DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1, 0x514, 0), @@ -282,7 +282,7 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x5ac, 0), }; -static struct rzg2l_reset r9a07g043_resets[] = { +static const struct rzg2l_reset r9a07g043_resets[] = { #ifdef CONFIG_ARM64 DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0), DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),