From: Greg Kroah-Hartman Date: Tue, 26 Feb 2013 18:33:29 +0000 (-0800) Subject: 3.8-stable patches X-Git-Tag: v3.7.10~16 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=b97ec09fce3a7890ae5d135e464ad394818067f0;p=thirdparty%2Fkernel%2Fstable-queue.git 3.8-stable patches added patches: drm-i915-add-missing-n-to-uts_release-in-the-error_state.patch drm-i915-disable-shared-panel-fitter-for-pipe.patch drm-i915-fix-cagf-for-hsw.patch drm-i915-fix-rc6vids-encode-decode.patch drm-i915-handle-untiled-planes-when-computing-their-offsets.patch drm-i915-inverted-brightness-quirk-for-acer-aspire-4736z.patch drm-i915-set-i9xx-sdvo-clock-limits-according-to-specifications.patch drm-i915-use-has_l3_gpu_cache-in-i915_gem_l3_remap.patch drm-i915-write-backlight-harder.patch --- diff --git a/queue-3.8/drm-i915-add-missing-n-to-uts_release-in-the-error_state.patch b/queue-3.8/drm-i915-add-missing-n-to-uts_release-in-the-error_state.patch new file mode 100644 index 00000000000..c24e24ab701 --- /dev/null +++ b/queue-3.8/drm-i915-add-missing-n-to-uts_release-in-the-error_state.patch @@ -0,0 +1,36 @@ +From fdfa175d0a9cfa2082ce24e67e284e5acbba452a Mon Sep 17 00:00:00 2001 +From: Jani Nikula +Date: Thu, 14 Feb 2013 11:23:35 +0200 +Subject: drm/i915: add missing \n to UTS_RELEASE in the error_state + +From: Jani Nikula + +commit fdfa175d0a9cfa2082ce24e67e284e5acbba452a upstream. + +Amending +commit 4518f611ba21ba165ea3714055938a8984a44ff9 +Author: Daniel Vetter +Date: Wed Jan 23 16:16:35 2013 +0100 + + drm/i915: dump UTS_RELEASE into the error_state + +Signed-off-by: Jani Nikula +Reviewed-by: Chris Wilson +Signed-off-by: Daniel Vetter +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/i915_debugfs.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/i915_debugfs.c ++++ b/drivers/gpu/drm/i915/i915_debugfs.c +@@ -691,7 +691,7 @@ static int i915_error_state(struct seq_f + + seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, + error->time.tv_usec); +- seq_printf(m, "Kernel: " UTS_RELEASE); ++ seq_printf(m, "Kernel: " UTS_RELEASE "\n"); + seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device); + seq_printf(m, "EIR: 0x%08x\n", error->eir); + seq_printf(m, "IER: 0x%08x\n", error->ier); diff --git a/queue-3.8/drm-i915-disable-shared-panel-fitter-for-pipe.patch b/queue-3.8/drm-i915-disable-shared-panel-fitter-for-pipe.patch new file mode 100644 index 00000000000..b8905f81740 --- /dev/null +++ b/queue-3.8/drm-i915-disable-shared-panel-fitter-for-pipe.patch @@ -0,0 +1,51 @@ +From 24a1f16de97c4cf0029d9acd04be06db32208726 Mon Sep 17 00:00:00 2001 +From: Mika Kuoppala +Date: Fri, 8 Feb 2013 16:35:37 +0200 +Subject: drm/i915: disable shared panel fitter for pipe + +From: Mika Kuoppala + +commit 24a1f16de97c4cf0029d9acd04be06db32208726 upstream. + +If encoder is switched off by BIOS, but the panel fitter is left on, +we never try to turn off the panel fitter and leave it still attached +to the pipe - which can cause blurry output elsewhere. + +Based on work by Chris Wilson + +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58867 +Signed-off-by: Mika Kuoppala +Tested-by: Andreas Sturmlechner +[danvet: Remove the redundant HAS_PCH_SPLIT check and add a tiny +comment.] +Signed-off-by: Daniel Vetter +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_display.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/drivers/gpu/drm/i915/intel_display.c ++++ b/drivers/gpu/drm/i915/intel_display.c +@@ -3686,6 +3686,7 @@ static void i9xx_crtc_disable(struct drm + struct intel_encoder *encoder; + int pipe = intel_crtc->pipe; + int plane = intel_crtc->plane; ++ u32 pctl; + + + if (!intel_crtc->active) +@@ -3705,6 +3706,13 @@ static void i9xx_crtc_disable(struct drm + + intel_disable_plane(dev_priv, plane, pipe); + intel_disable_pipe(dev_priv, pipe); ++ ++ /* Disable pannel fitter if it is on this pipe. */ ++ pctl = I915_READ(PFIT_CONTROL); ++ if ((pctl & PFIT_ENABLE) && ++ ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe) ++ I915_WRITE(PFIT_CONTROL, 0); ++ + intel_disable_pll(dev_priv, pipe); + + intel_crtc->active = false; diff --git a/queue-3.8/drm-i915-fix-cagf-for-hsw.patch b/queue-3.8/drm-i915-fix-cagf-for-hsw.patch new file mode 100644 index 00000000000..20df6b4403a --- /dev/null +++ b/queue-3.8/drm-i915-fix-cagf-for-hsw.patch @@ -0,0 +1,69 @@ +From f82855d342b6c8483c56e6d2e200a71731509a39 Mon Sep 17 00:00:00 2001 +From: Ben Widawsky +Date: Tue, 29 Jan 2013 12:00:15 -0800 +Subject: drm/i915: Fix CAGF for HSW + +From: Ben Widawsky + +commit f82855d342b6c8483c56e6d2e200a71731509a39 upstream. + +The shift changed, hurray. + +Reported-by: Kenneth Graunke +Cc: Paulo Zanoni +Reviewed-by: Paulo Zanoni +Tested-by: Paulo Zanoni +Signed-off-by: Ben Widawsky +Signed-off-by: Daniel Vetter +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/i915_debugfs.c | 10 +++++++--- + drivers/gpu/drm/i915/i915_reg.h | 2 ++ + 2 files changed, 9 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/i915/i915_debugfs.c ++++ b/drivers/gpu/drm/i915/i915_debugfs.c +@@ -888,7 +888,7 @@ static int i915_cur_delayinfo(struct seq + u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); + u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); + u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); +- u32 rpstat; ++ u32 rpstat, cagf; + u32 rpupei, rpcurup, rpprevup; + u32 rpdownei, rpcurdown, rpprevdown; + int max_freq; +@@ -907,6 +907,11 @@ static int i915_cur_delayinfo(struct seq + rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI); + rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); + rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); ++ if (IS_HASWELL(dev)) ++ cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; ++ else ++ cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; ++ cagf *= GT_FREQUENCY_MULTIPLIER; + + gen6_gt_force_wake_put(dev_priv); + mutex_unlock(&dev->struct_mutex); +@@ -919,8 +924,7 @@ static int i915_cur_delayinfo(struct seq + gt_perf_status & 0xff); + seq_printf(m, "Render p-state limit: %d\n", + rp_state_limits & 0xff); +- seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >> +- GEN6_CAGF_SHIFT) * GT_FREQUENCY_MULTIPLIER); ++ seq_printf(m, "CAGF: %dMHz\n", cagf); + seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & + GEN6_CURICONT_MASK); + seq_printf(m, "RP CUR UP: %dus\n", rpcurup & +--- a/drivers/gpu/drm/i915/i915_reg.h ++++ b/drivers/gpu/drm/i915/i915_reg.h +@@ -4211,7 +4211,9 @@ + #define GEN6_RP_INTERRUPT_LIMITS 0xA014 + #define GEN6_RPSTAT1 0xA01C + #define GEN6_CAGF_SHIFT 8 ++#define HSW_CAGF_SHIFT 7 + #define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT) ++#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT) + #define GEN6_RP_CONTROL 0xA024 + #define GEN6_RP_MEDIA_TURBO (1<<11) + #define GEN6_RP_MEDIA_MODE_MASK (3<<9) diff --git a/queue-3.8/drm-i915-fix-rc6vids-encode-decode.patch b/queue-3.8/drm-i915-fix-rc6vids-encode-decode.patch new file mode 100644 index 00000000000..30e59c4fdb0 --- /dev/null +++ b/queue-3.8/drm-i915-fix-rc6vids-encode-decode.patch @@ -0,0 +1,44 @@ +From 7083e05072b88d503d257b6f012ce56367f3ac97 Mon Sep 17 00:00:00 2001 +From: Ben Widawsky +Date: Fri, 1 Feb 2013 16:41:14 -0800 +Subject: drm/i915: Fix RC6VIDS encode/decode + +From: Ben Widawsky + +commit 7083e05072b88d503d257b6f012ce56367f3ac97 upstream. + +The RC6 VIDS has a linear ramp starting at 250mv, which means any values +below 250 are invalid. The old buggy macros tried to adjust for this to +be more flexible, but there is no need. As Dan pointed out the ENCODE +only ever has one value. The only invalid value for decode is an input +of 0 which means something is really wonky, and the cases where DECODE +are used either don't matter (debug values), or would be implicitly +correct (the check for less than 450). + +This patch makes simpler, easier to read macros which are actually +correct. Maybe this patch can actually fix some bugs now. + +Thanks to Dan for catching this. /me hides + +Reported-by: Dan Carpenter +Signed-off-by: Ben Widawsky +Signed-off-by: Daniel Vetter +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/i915_reg.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/i915/i915_reg.h ++++ b/drivers/gpu/drm/i915/i915_reg.h +@@ -4282,8 +4282,8 @@ + #define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9 + #define GEN6_PCODE_WRITE_RC6VIDS 0x4 + #define GEN6_PCODE_READ_RC6VIDS 0x5 +-#define GEN6_ENCODE_RC6_VID(mv) (((mv) / 5) - 245) < 0 ?: 0 +-#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) > 0 ? ((vids) * 5) + 245 : 0) ++#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) ++#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) + #define GEN6_PCODE_DATA 0x138128 + #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 + diff --git a/queue-3.8/drm-i915-handle-untiled-planes-when-computing-their-offsets.patch b/queue-3.8/drm-i915-handle-untiled-planes-when-computing-their-offsets.patch new file mode 100644 index 00000000000..f24c834ef52 --- /dev/null +++ b/queue-3.8/drm-i915-handle-untiled-planes-when-computing-their-offsets.patch @@ -0,0 +1,147 @@ +From bc752862170c135d6c09fb22d79eeb451023568e Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Thu, 21 Feb 2013 20:04:31 +0000 +Subject: drm/i915: Handle untiled planes when computing their offsets + +From: Chris Wilson + +commit bc752862170c135d6c09fb22d79eeb451023568e upstream. + +We trim the fb to fit the CRTC by computing the offset of that CRTC to +its nearest tile_row origin. This allows us to use framebuffers that are +larger than the CRTC limits without additional work. + +However, we failed to compute the offset for a linear framebuffer +correctly as we treated its x-advance in whole tiles (instead of the +linear increment expected), leaving the CRTC misaligned with its +contents. + +Fixes regression from commit c2c75131244507c93f812862fdbd4f3a37139401 +Author: Daniel Vetter +Date: Thu Jul 5 12:17:30 2012 +0200 + + drm/i915: adjust framebuffer base address on gen4+ + +v2: Adjust relative x-coordinate after linear alignment (vsyrjala) +v3: Repaint with pokadots (vsyrjala) + +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61152 +Signed-off-by: Chris Wilson +Cc: Daniel Vetter +Reviewed-by: Ville Syrjälä +Signed-off-by: Daniel Vetter +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_display.c | 41 ++++++++++++++++++++++------------- + drivers/gpu/drm/i915/intel_drv.h | 7 +++-- + drivers/gpu/drm/i915/intel_sprite.c | 8 +++--- + 3 files changed, 34 insertions(+), 22 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_display.c ++++ b/drivers/gpu/drm/i915/intel_display.c +@@ -2017,18 +2017,29 @@ void intel_unpin_fb_obj(struct drm_i915_ + + /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel + * is assumed to be a power-of-two. */ +-unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y, +- unsigned int bpp, +- unsigned int pitch) ++unsigned long intel_gen4_compute_page_offset(int *x, int *y, ++ unsigned int tiling_mode, ++ unsigned int cpp, ++ unsigned int pitch) + { +- int tile_rows, tiles; ++ if (tiling_mode != I915_TILING_NONE) { ++ unsigned int tile_rows, tiles; + +- tile_rows = *y / 8; +- *y %= 8; +- tiles = *x / (512/bpp); +- *x %= 512/bpp; ++ tile_rows = *y / 8; ++ *y %= 8; + +- return tile_rows * pitch * 8 + tiles * 4096; ++ tiles = *x / (512/cpp); ++ *x %= 512/cpp; ++ ++ return tile_rows * pitch * 8 + tiles * 4096; ++ } else { ++ unsigned int offset; ++ ++ offset = *y * pitch + *x * cpp; ++ *y = 0; ++ *x = (offset & 4095) / cpp; ++ return offset & -4096; ++ } + } + + static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, +@@ -2105,9 +2116,9 @@ static int i9xx_update_plane(struct drm_ + + if (INTEL_INFO(dev)->gen >= 4) { + intel_crtc->dspaddr_offset = +- intel_gen4_compute_offset_xtiled(&x, &y, +- fb->bits_per_pixel / 8, +- fb->pitches[0]); ++ intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, ++ fb->bits_per_pixel / 8, ++ fb->pitches[0]); + linear_offset -= intel_crtc->dspaddr_offset; + } else { + intel_crtc->dspaddr_offset = linear_offset; +@@ -2198,9 +2209,9 @@ static int ironlake_update_plane(struct + + linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); + intel_crtc->dspaddr_offset = +- intel_gen4_compute_offset_xtiled(&x, &y, +- fb->bits_per_pixel / 8, +- fb->pitches[0]); ++ intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, ++ fb->bits_per_pixel / 8, ++ fb->pitches[0]); + linear_offset -= intel_crtc->dspaddr_offset; + + DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", +--- a/drivers/gpu/drm/i915/intel_drv.h ++++ b/drivers/gpu/drm/i915/intel_drv.h +@@ -627,9 +627,10 @@ extern void intel_update_sprite_watermar + extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe, + struct drm_display_mode *mode); + +-extern unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y, +- unsigned int bpp, +- unsigned int pitch); ++extern unsigned long intel_gen4_compute_page_offset(int *x, int *y, ++ unsigned int tiling_mode, ++ unsigned int bpp, ++ unsigned int pitch); + + extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data, + struct drm_file *file_priv); +--- a/drivers/gpu/drm/i915/intel_sprite.c ++++ b/drivers/gpu/drm/i915/intel_sprite.c +@@ -122,8 +122,8 @@ ivb_update_plane(struct drm_plane *plane + + linear_offset = y * fb->pitches[0] + x * pixel_size; + sprsurf_offset = +- intel_gen4_compute_offset_xtiled(&x, &y, +- pixel_size, fb->pitches[0]); ++ intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, ++ pixel_size, fb->pitches[0]); + linear_offset -= sprsurf_offset; + + /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET +@@ -287,8 +287,8 @@ ilk_update_plane(struct drm_plane *plane + + linear_offset = y * fb->pitches[0] + x * pixel_size; + dvssurf_offset = +- intel_gen4_compute_offset_xtiled(&x, &y, +- pixel_size, fb->pitches[0]); ++ intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, ++ pixel_size, fb->pitches[0]); + linear_offset -= dvssurf_offset; + + if (obj->tiling_mode != I915_TILING_NONE) diff --git a/queue-3.8/drm-i915-inverted-brightness-quirk-for-acer-aspire-4736z.patch b/queue-3.8/drm-i915-inverted-brightness-quirk-for-acer-aspire-4736z.patch new file mode 100644 index 00000000000..c4d9f3d6bb5 --- /dev/null +++ b/queue-3.8/drm-i915-inverted-brightness-quirk-for-acer-aspire-4736z.patch @@ -0,0 +1,31 @@ +From ac4199e0f047546aa40172785e26c82b54bbe811 Mon Sep 17 00:00:00 2001 +From: Daniel Vetter +Date: Fri, 15 Feb 2013 18:35:30 +0100 +Subject: drm/i915: inverted brightness quirk for Acer Aspire 4736Z + +From: Daniel Vetter + +commit ac4199e0f047546aa40172785e26c82b54bbe811 upstream. + +Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=53881 +Cc: Jani Nikula +Tested-by: Jani Monoses +Signed-off-by: Daniel Vetter +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_display.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/gpu/drm/i915/intel_display.c ++++ b/drivers/gpu/drm/i915/intel_display.c +@@ -8890,6 +8890,9 @@ static struct intel_quirk intel_quirks[] + + /* Acer Aspire 5734Z must invert backlight brightness */ + { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, ++ ++ /* Acer Aspire 4736Z */ ++ { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, + }; + + static void intel_init_quirks(struct drm_device *dev) diff --git a/queue-3.8/drm-i915-set-i9xx-sdvo-clock-limits-according-to-specifications.patch b/queue-3.8/drm-i915-set-i9xx-sdvo-clock-limits-according-to-specifications.patch new file mode 100644 index 00000000000..86886a18f42 --- /dev/null +++ b/queue-3.8/drm-i915-set-i9xx-sdvo-clock-limits-according-to-specifications.patch @@ -0,0 +1,36 @@ +From 4f7dfb6788dd022446847fbbfbe45e13bedb5be2 Mon Sep 17 00:00:00 2001 +From: Patrik Jakobsson +Date: Wed, 13 Feb 2013 22:20:22 +0100 +Subject: drm/i915: Set i9xx sdvo clock limits according to specifications + +From: Patrik Jakobsson + +commit 4f7dfb6788dd022446847fbbfbe45e13bedb5be2 upstream. + +The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9. +Since we do all calculations based on them being register values (which are +subtracted by 2) we need to specify them accordingly. + +Signed-off-by: Patrik Jakobsson +Reviewed-by: Chris Wilson +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56359 +Signed-off-by: Daniel Vetter +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_display.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_display.c ++++ b/drivers/gpu/drm/i915/intel_display.c +@@ -154,8 +154,8 @@ static const intel_limit_t intel_limits_ + .vco = { .min = 1400000, .max = 2800000 }, + .n = { .min = 1, .max = 6 }, + .m = { .min = 70, .max = 120 }, +- .m1 = { .min = 10, .max = 22 }, +- .m2 = { .min = 5, .max = 9 }, ++ .m1 = { .min = 8, .max = 18 }, ++ .m2 = { .min = 3, .max = 7 }, + .p = { .min = 5, .max = 80 }, + .p1 = { .min = 1, .max = 8 }, + .p2 = { .dot_limit = 200000, diff --git a/queue-3.8/drm-i915-use-has_l3_gpu_cache-in-i915_gem_l3_remap.patch b/queue-3.8/drm-i915-use-has_l3_gpu_cache-in-i915_gem_l3_remap.patch new file mode 100644 index 00000000000..49273f25867 --- /dev/null +++ b/queue-3.8/drm-i915-use-has_l3_gpu_cache-in-i915_gem_l3_remap.patch @@ -0,0 +1,33 @@ +From eb32e4584d8e9d6cbec20550d4f91396de2cdb55 Mon Sep 17 00:00:00 2001 +From: Daniel Vetter +Date: Thu, 14 Feb 2013 19:46:07 +0100 +Subject: drm/i915: Use HAS_L3_GPU_CACHE in i915_gem_l3_remap + +From: Daniel Vetter + +commit eb32e4584d8e9d6cbec20550d4f91396de2cdb55 upstream. + +Yet another remnant ... this might explain why l3 remapping didn't +really work on HSW. + +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57441 +Spotted-by: Ville Syrjälä +Reviewed-by: Ben Widawsky +Signed-off-by: Daniel Vetter +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/i915_gem.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/i915_gem.c ++++ b/drivers/gpu/drm/i915/i915_gem.c +@@ -3845,7 +3845,7 @@ void i915_gem_l3_remap(struct drm_device + u32 misccpctl; + int i; + +- if (!IS_IVYBRIDGE(dev)) ++ if (!HAS_L3_GPU_CACHE(dev)) + return; + + if (!dev_priv->l3_parity.remap_info) diff --git a/queue-3.8/drm-i915-write-backlight-harder.patch b/queue-3.8/drm-i915-write-backlight-harder.patch new file mode 100644 index 00000000000..567297b1572 --- /dev/null +++ b/queue-3.8/drm-i915-write-backlight-harder.patch @@ -0,0 +1,66 @@ +From cf0a6584aa6d382f802f2c3cacac23ccbccde0cd Mon Sep 17 00:00:00 2001 +From: Daniel Vetter +Date: Wed, 6 Feb 2013 11:24:41 +0100 +Subject: drm/i915: write backlight harder + +From: Daniel Vetter + +commit cf0a6584aa6d382f802f2c3cacac23ccbccde0cd upstream. + +770c12312ad617172b1a65b911d3e6564fc5aca8 is the first bad commit +commit 770c12312ad617172b1a65b911d3e6564fc5aca8 +Author: Takashi Iwai +Date: Sat Aug 11 08:56:42 2012 +0200 + + drm/i915: Fix blank panel at reopening lid + +changed the register write sequence for restoring the backlight, which +helped prevent non-working backlights on some machines. Turns out that +the original sequence was the right thing to do for a different set of +machines. Worse, setting the backlight level _after_ enabling it seems +to reset it somehow. So we need to make that one conditional upon the +backlight having been reset to zero, and add the old one back. + +Cargo-culting at it's best, but it seems to work. + +Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=47941 +Cc: Takashi Iwai +Reviewed-by: Jani Nikula +Acked-by: Takashi Iwai +Signed-off-by: Daniel Vetter +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_panel.c | 13 ++++++++----- + 1 file changed, 8 insertions(+), 5 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_panel.c ++++ b/drivers/gpu/drm/i915/intel_panel.c +@@ -321,6 +321,9 @@ void intel_panel_enable_backlight(struct + if (dev_priv->backlight_level == 0) + dev_priv->backlight_level = intel_panel_get_max_backlight(dev); + ++ dev_priv->backlight_enabled = true; ++ intel_panel_actually_set_backlight(dev, dev_priv->backlight_level); ++ + if (INTEL_INFO(dev)->gen >= 4) { + uint32_t reg, tmp; + +@@ -356,12 +359,12 @@ void intel_panel_enable_backlight(struct + } + + set_level: +- /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1. +- * BLC_PWM_CPU_CTL may be cleared to zero automatically when these +- * registers are set. ++ /* Check the current backlight level and try to set again if it's zero. ++ * On some machines, BLC_PWM_CPU_CTL is cleared to zero automatically ++ * when BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1 are written. + */ +- dev_priv->backlight_enabled = true; +- intel_panel_actually_set_backlight(dev, dev_priv->backlight_level); ++ if (!intel_panel_get_backlight(dev)) ++ intel_panel_actually_set_backlight(dev, dev_priv->backlight_level); + } + + static void intel_panel_init_backlight(struct drm_device *dev) diff --git a/queue-3.8/series b/queue-3.8/series index 2a318b60201..52645be76d5 100644 --- a/queue-3.8/series +++ b/queue-3.8/series @@ -80,3 +80,12 @@ get-rid-of-unprotected-dereferencing-of-mnt-mnt_ns.patch drm-i915-preserve-the-ddi-link-reversal-configuration.patch drm-i915-preserve-the-fdi-line-reversal-override-bit-on-cpt.patch drm-i915-only-run-idle-processing-from-i915_gem_retire_requests_worker.patch +drm-i915-fix-cagf-for-hsw.patch +drm-i915-fix-rc6vids-encode-decode.patch +drm-i915-write-backlight-harder.patch +drm-i915-disable-shared-panel-fitter-for-pipe.patch +drm-i915-set-i9xx-sdvo-clock-limits-according-to-specifications.patch +drm-i915-add-missing-n-to-uts_release-in-the-error_state.patch +drm-i915-use-has_l3_gpu_cache-in-i915_gem_l3_remap.patch +drm-i915-inverted-brightness-quirk-for-acer-aspire-4736z.patch +drm-i915-handle-untiled-planes-when-computing-their-offsets.patch