From: Kito Cheng <kito.cheng@sifive.com>
Date: Wed, 22 Mar 2023 10:47:52 +0000 (+0800)
Subject: RISC-V: Add riscv_vector target check
X-Git-Tag: basepoints/gcc-14~388
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ba31f9a3c8fa9405a9a58094d6dc83bab0823786;p=thirdparty%2Fgcc.git

RISC-V: Add riscv_vector target check

Add target check funciton to ensure vector extension can be used.

gcc/testsuite/ChangeLog:

	* lib/target-supports.exp (check_effective_target_riscv_vector):
	New.
---

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 5e4a73af0de3..932aa5b2d667 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -1759,6 +1759,18 @@ proc check_linker_plugin_available { } {
   } "-flto -fuse-linker-plugin"]
 }
 
+# Return 1 if the target has RISC-V vector extension, 0 otherwise.
+# Cache the result.
+
+proc check_effective_target_riscv_vector { } {
+    # Check that we are compiling for v by checking the __riscv_v marco.
+    return [check_no_compiler_messages riscv_vector assembly {
+       #if !defined(__riscv_v)
+       #error "__riscv_v not defined!"
+       #endif
+    }]
+}
+
 # Return 1 if the target is RV32, 0 otherwise.  Cache the result.
 
 proc check_effective_target_rv32 { } {