From: Robert Hoo Date: Fri, 12 Jan 2024 06:00:41 +0000 (+0800) Subject: target/i386: add support for LAM in CPUID enumeration X-Git-Tag: v9.1.0-rc0~98^2~19 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ba6780905943696d790cc880c8e5684b51f027fe;p=thirdparty%2Fqemu.git target/i386: add support for LAM in CPUID enumeration Linear Address Masking (LAM) is a new Intel CPU feature, which allows software to use of the untranslated address bits for metadata. The bit definition: CPUID.(EAX=7,ECX=1):EAX[26] Add CPUID definition for LAM. Note LAM feature is not supported for TCG of target-i386, LAM CPIUD bit will not be added to TCG_7_1_EAX_FEATURES. More info can be found in Intel ISE Chapter "LINEAR ADDRESS MASKING(LAM)" https://cdrdv2.intel.com/v1/dl/getContent/671368 Signed-off-by: Robert Hoo Co-developed-by: Binbin Wu Signed-off-by: Binbin Wu Tested-by: Xuelian Guo Reviewed-by: Xiaoyao Li Reviewed-by: Zhao Liu Message-ID: <20240112060042.19925-2-binbin.wu@linux.intel.com> Signed-off-by: Paolo Bonzini --- diff --git a/target/i386/cpu.c b/target/i386/cpu.c index cfe7c92d6bc..de1ad7270cf 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -969,7 +969,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "fsrc", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "amx-fp16", NULL, "avx-ifma", - NULL, NULL, NULL, NULL, + NULL, NULL, "lam", NULL, NULL, NULL, NULL, NULL, }, .cpuid = { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ccccb62fc35..107f263429a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -927,6 +927,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, #define CPUID_7_1_EAX_AMX_FP16 (1U << 21) /* Support for VPMADD52[H,L]UQ */ #define CPUID_7_1_EAX_AVX_IFMA (1U << 23) +/* Linear Address Masking */ +#define CPUID_7_1_EAX_LAM (1U << 26) /* Support for VPDPB[SU,UU,SS]D[,S] */ #define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4)