From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Date: Fri, 23 Feb 2024 15:42:11 +0000 (+0100)
Subject: 6.6-stable patches
X-Git-Tag: v4.19.308~103
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=bb52cfaca44de4b4577572f112bd79f3402c4e04;p=thirdparty%2Fkernel%2Fstable-queue.git

6.6-stable patches

added patches:
	pci-dwc-fix-a-64bit-bug-in-dw_pcie_ep_raise_msix_irq.patch
---

diff --git a/queue-6.6/pci-dwc-fix-a-64bit-bug-in-dw_pcie_ep_raise_msix_irq.patch b/queue-6.6/pci-dwc-fix-a-64bit-bug-in-dw_pcie_ep_raise_msix_irq.patch
new file mode 100644
index 00000000000..332584c0dbd
--- /dev/null
+++ b/queue-6.6/pci-dwc-fix-a-64bit-bug-in-dw_pcie_ep_raise_msix_irq.patch
@@ -0,0 +1,50 @@
+From cbc98e30eb470a924d2fd59ae693d5480b3d263d Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@linaro.org>
+Date: Fri, 26 Jan 2024 11:40:37 +0300
+Subject: PCI: dwc: Fix a 64bit bug in dw_pcie_ep_raise_msix_irq()
+
+From: Dan Carpenter <dan.carpenter@linaro.org>
+
+commit b5d1b4b46f856da1473c7ba9a5cdfcb55c9b2478 upstream.
+
+The "msg_addr" variable is u64.  However, the "aligned_offset" is an
+unsigned int.  This means that when the code does:
+
+  msg_addr &= ~aligned_offset;
+
+it will unintentionally zero out the high 32 bits.  Use ALIGN_DOWN() to do
+the alignment instead.
+
+Fixes: 2217fffcd63f ("PCI: dwc: endpoint: Fix dw_pcie_ep_raise_msix_irq() alignment support")
+Link: https://lore.kernel.org/r/af59c7ad-ab93-40f7-ad4a-7ac0b14d37f5@moroto.mountain
+Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Niklas Cassel <cassel@kernel.org>
+Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
+Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Cc: <stable@vger.kernel.org>
+Signed-off-by: Niklas Cassel <cassel@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/pci/controller/dwc/pcie-designware-ep.c |    3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
++++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
+@@ -6,6 +6,7 @@
+  * Author: Kishon Vijay Abraham I <kishon@ti.com>
+  */
+ 
++#include <linux/align.h>
+ #include <linux/of.h>
+ #include <linux/platform_device.h>
+ 
+@@ -598,7 +599,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_
+ 	}
+ 
+ 	aligned_offset = msg_addr & (epc->mem->window.page_size - 1);
+-	msg_addr &= ~aligned_offset;
++	msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size);
+ 	ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr,
+ 				  epc->mem->window.page_size);
+ 	if (ret)
diff --git a/queue-6.6/series b/queue-6.6/series
index c955e85b992..79321cd8276 100644
--- a/queue-6.6/series
+++ b/queue-6.6/series
@@ -1 +1,2 @@
 sched-rt-disallow-writing-invalid-values-to-sched_rt_period_us.patch
+pci-dwc-fix-a-64bit-bug-in-dw_pcie_ep_raise_msix_irq.patch