From: Greg Kroah-Hartman Date: Mon, 8 May 2023 08:26:32 +0000 (+0200) Subject: drop some dts changes from 6.2 that were not needed. X-Git-Tag: v5.15.111~28 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=bb6edf1c08c0ab2a51a1ac88443e373bf56c11c2;p=thirdparty%2Fkernel%2Fstable-queue.git drop some dts changes from 6.2 that were not needed. --- diff --git a/queue-6.2/arm64-dts-qcom-ipq6018-add-remove-some-newlines.patch b/queue-6.2/arm64-dts-qcom-ipq6018-add-remove-some-newlines.patch index f4b54b9bcdc..eb20ebc4998 100644 --- a/queue-6.2/arm64-dts-qcom-ipq6018-add-remove-some-newlines.patch +++ b/queue-6.2/arm64-dts-qcom-ipq6018-add-remove-some-newlines.patch @@ -18,14 +18,12 @@ Link: https://lore.kernel.org/r/20230102094642.74254-5-konrad.dybcio@linaro.org Stable-dep-of: 75a6e1fdb351 ("arm64: dts: qcom: ipq6018: Fix the PCI I/O port range") Signed-off-by: Sasha Levin --- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 ++++++++++++-------------- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) -diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -index 8937b10748f3e..0d9074b3b1a26 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -102,26 +102,31 @@ +@@ -96,26 +96,31 @@ opp-microvolt = <725000>; clock-latency-ns = <200000>; }; @@ -67,7 +65,7 @@ index 8937b10748f3e..0d9074b3b1a26 100644 }; psci: psci { -@@ -734,24 +738,18 @@ +@@ -437,24 +441,18 @@ phys = <&pcie_phy0>; phy-names = "pciephy"; @@ -98,6 +96,3 @@ index 8937b10748f3e..0d9074b3b1a26 100644 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, <&gcc GCC_PCIE0_AXI_M_CLK>, --- -2.39.2 - diff --git a/queue-6.2/arm64-dts-qcom-ipq6018-fix-the-pci-i-o-port-range.patch b/queue-6.2/arm64-dts-qcom-ipq6018-fix-the-pci-i-o-port-range.patch index a2a08f0a7cb..2da02ba2a6b 100644 --- a/queue-6.2/arm64-dts-qcom-ipq6018-fix-the-pci-i-o-port-range.patch +++ b/queue-6.2/arm64-dts-qcom-ipq6018-fix-the-pci-i-o-port-range.patch @@ -22,14 +22,12 @@ Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-7-manivannan.sadhasivam@linaro.org Signed-off-by: Sasha Levin --- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++-- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -index 0d9074b3b1a26..8a5eb027caba3 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -738,8 +738,8 @@ +@@ -441,8 +441,8 @@ phys = <&pcie_phy0>; phy-names = "pciephy"; @@ -40,6 +38,3 @@ index 0d9074b3b1a26..8a5eb027caba3 100644 interrupts = ; interrupt-names = "msi"; --- -2.39.2 - diff --git a/queue-6.2/arm64-dts-qcom-ipq6018-fix-up-indentation.patch b/queue-6.2/arm64-dts-qcom-ipq6018-fix-up-indentation.patch deleted file mode 100644 index 7d86d1a24c5..00000000000 --- a/queue-6.2/arm64-dts-qcom-ipq6018-fix-up-indentation.patch +++ /dev/null @@ -1,121 +0,0 @@ -From 3aaccc4657608c128d4897da6f03de426db70fcb Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 2 Jan 2023 10:46:27 +0100 -Subject: arm64: dts: qcom: ipq6018: Fix up indentation - -From: Konrad Dybcio - -[ Upstream commit c2596b717e9d96ae57c45481acfbafe9d3d54e56 ] - -The dwc3 subnode was indented using spaces for some reason and other -properties were not exactly properly indented. Fix it. - -Signed-off-by: Konrad Dybcio -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20230102094642.74254-3-konrad.dybcio@linaro.org -Stable-dep-of: 75a6e1fdb351 ("arm64: dts: qcom: ipq6018: Fix the PCI I/O port range") -Signed-off-by: Sasha Levin ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 44 +++++++++++++-------------- - 1 file changed, 22 insertions(+), 22 deletions(-) - -diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -index 6f12c1a8f90f3..d1c02efc2ea9f 100644 ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -201,8 +201,8 @@ - compatible = "qcom,crypto-v5.1"; - reg = <0x0 0x0073a000 0x0 0x6000>; - clocks = <&gcc GCC_CRYPTO_AHB_CLK>, -- <&gcc GCC_CRYPTO_AXI_CLK>, -- <&gcc GCC_CRYPTO_CLK>; -+ <&gcc GCC_CRYPTO_AXI_CLK>, -+ <&gcc GCC_CRYPTO_CLK>; - clock-names = "iface", "bus", "core"; - dmas = <&cryptobam 2>, <&cryptobam 3>; - dma-names = "rx", "tx"; -@@ -272,7 +272,7 @@ - reg = <0x0 0x078b1000 0x0 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, -- <&gcc GCC_BLSP1_AHB_CLK>; -+ <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - status = "disabled"; - }; -@@ -285,7 +285,7 @@ - interrupts = ; - spi-max-frequency = <50000000>; - clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, -- <&gcc GCC_BLSP1_AHB_CLK>; -+ <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 12>, <&blsp_dma 13>; - dma-names = "tx", "rx"; -@@ -300,7 +300,7 @@ - interrupts = ; - spi-max-frequency = <50000000>; - clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, -- <&gcc GCC_BLSP1_AHB_CLK>; -+ <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - dmas = <&blsp_dma 14>, <&blsp_dma 15>; - dma-names = "tx", "rx"; -@@ -358,8 +358,8 @@ - clock-names = "core", "aon"; - - dmas = <&qpic_bam 0>, -- <&qpic_bam 1>, -- <&qpic_bam 2>; -+ <&qpic_bam 1>, -+ <&qpic_bam 2>; - dma-names = "tx", "rx", "cmd"; - pinctrl-0 = <&qpic_pins>; - pinctrl-names = "default"; -@@ -372,10 +372,10 @@ - #size-cells = <2>; - interrupt-controller; - #interrupt-cells = <0x3>; -- reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ -- <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ -- <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ -- <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ -+ reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ -+ <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ -+ <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ -+ <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ - interrupts = ; - ranges = <0 0 0 0xb00a000 0 0xffd>; - -@@ -663,17 +663,17 @@ - status = "disabled"; - - dwc_1: usb@7000000 { -- compatible = "snps,dwc3"; -- reg = <0x0 0x07000000 0x0 0xcd00>; -- interrupts = ; -- phys = <&qusb_phy_1>; -- phy-names = "usb2-phy"; -- tx-fifo-resize; -- snps,is-utmi-l1-suspend; -- snps,hird-threshold = /bits/ 8 <0x0>; -- snps,dis_u2_susphy_quirk; -- snps,dis_u3_susphy_quirk; -- dr_mode = "host"; -+ compatible = "snps,dwc3"; -+ reg = <0x0 0x07000000 0x0 0xcd00>; -+ interrupts = ; -+ phys = <&qusb_phy_1>; -+ phy-names = "usb2-phy"; -+ tx-fifo-resize; -+ snps,is-utmi-l1-suspend; -+ snps,hird-threshold = /bits/ 8 <0x0>; -+ snps,dis_u2_susphy_quirk; -+ snps,dis_u3_susphy_quirk; -+ dr_mode = "host"; - }; - }; - --- -2.39.2 - diff --git a/queue-6.2/arm64-dts-qcom-ipq6018-pad-addresses-to-8-hex-digits.patch b/queue-6.2/arm64-dts-qcom-ipq6018-pad-addresses-to-8-hex-digits.patch deleted file mode 100644 index 6373e7101d2..00000000000 --- a/queue-6.2/arm64-dts-qcom-ipq6018-pad-addresses-to-8-hex-digits.patch +++ /dev/null @@ -1,114 +0,0 @@ -From cb8bdd111958d1f23c6d67f316c1779e00bc41f5 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 2 Jan 2023 10:46:26 +0100 -Subject: arm64: dts: qcom: ipq6018: Pad addresses to 8 hex digits - -From: Konrad Dybcio - -[ Upstream commit 647380e41520c7dbd651ebf0d9fd7dfa4928f42d ] - -Some addresses were 7-hex-digits long, or less. Fix that. - -Signed-off-by: Konrad Dybcio -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20230102094642.74254-2-konrad.dybcio@linaro.org -Stable-dep-of: 75a6e1fdb351 ("arm64: dts: qcom: ipq6018: Fix the PCI I/O port range") -Signed-off-by: Sasha Levin ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 24 ++++++++++++------------ - 1 file changed, 12 insertions(+), 12 deletions(-) - -diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -index 2ceae73a6069e..6f12c1a8f90f3 100644 ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -146,7 +146,7 @@ - ranges; - - rpm_msg_ram: memory@60000 { -- reg = <0x0 0x60000 0x0 0x6000>; -+ reg = <0x0 0x00060000 0x0 0x6000>; - no-map; - }; - -@@ -181,7 +181,7 @@ - - prng: qrng@e1000 { - compatible = "qcom,prng-ee"; -- reg = <0x0 0xe3000 0x0 0x1000>; -+ reg = <0x0 0x000e3000 0x0 0x1000>; - clocks = <&gcc GCC_PRNG_AHB_CLK>; - clock-names = "core"; - }; -@@ -388,7 +388,7 @@ - - pcie_phy: phy@84000 { - compatible = "qcom,ipq6018-qmp-pcie-phy"; -- reg = <0x0 0x84000 0x0 0x1bc>; /* Serdes PLL */ -+ reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */ - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; -@@ -404,10 +404,10 @@ - "common"; - - pcie_phy0: phy@84200 { -- reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */ -- <0x0 0x84400 0x0 0x200>, /* Serdes Rx */ -- <0x0 0x84800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */ -- <0x0 0x84c00 0x0 0xf4>; /* pcs_misc */ -+ reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */ -+ <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */ -+ <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */ -+ <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */ - #phy-cells = <0>; - - clocks = <&gcc GCC_PCIE0_PIPE_CLK>; -@@ -623,7 +623,7 @@ - #address-cells = <1>; - #size-cells = <0>; - compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio"; -- reg = <0x0 0x90000 0x0 0x64>; -+ reg = <0x0 0x00090000 0x0 0x64>; - clocks = <&gcc GCC_MDIO_AHB_CLK>; - clock-names = "gcc_mdio_ahb_clk"; - status = "disabled"; -@@ -631,7 +631,7 @@ - - qusb_phy_1: qusb@59000 { - compatible = "qcom,ipq6018-qusb2-phy"; -- reg = <0x0 0x059000 0x0 0x180>; -+ reg = <0x0 0x00059000 0x0 0x180>; - #phy-cells = <0>; - - clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, -@@ -664,7 +664,7 @@ - - dwc_1: usb@7000000 { - compatible = "snps,dwc3"; -- reg = <0x0 0x7000000 0x0 0xcd00>; -+ reg = <0x0 0x07000000 0x0 0xcd00>; - interrupts = ; - phys = <&qusb_phy_1>; - phy-names = "usb2-phy"; -@@ -679,7 +679,7 @@ - - ssphy_0: ssphy@78000 { - compatible = "qcom,ipq6018-qmp-usb3-phy"; -- reg = <0x0 0x78000 0x0 0x1c4>; -+ reg = <0x0 0x00078000 0x0 0x1c4>; - #address-cells = <2>; - #size-cells = <2>; - ranges; -@@ -708,7 +708,7 @@ - - qusb_phy_0: qusb@79000 { - compatible = "qcom,ipq6018-qusb2-phy"; -- reg = <0x0 0x079000 0x0 0x180>; -+ reg = <0x0 0x00079000 0x0 0x180>; - #phy-cells = <0>; - - clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, --- -2.39.2 - diff --git a/queue-6.2/arm64-dts-qcom-ipq6018-sort-nodes-properly.patch b/queue-6.2/arm64-dts-qcom-ipq6018-sort-nodes-properly.patch deleted file mode 100644 index 3c5887a4b19..00000000000 --- a/queue-6.2/arm64-dts-qcom-ipq6018-sort-nodes-properly.patch +++ /dev/null @@ -1,662 +0,0 @@ -From e7d34526700faa04598d1421569f6d54b380d1f8 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 2 Jan 2023 10:46:28 +0100 -Subject: arm64: dts: qcom: ipq6018: Sort nodes properly - -From: Konrad Dybcio - -[ Upstream commit 2c6e322a41c5e1ca45be50b9d5fbcda62dc23a0d ] - -Order nodes by unit address if one exists and alphabetically otherwise. - -Signed-off-by: Konrad Dybcio -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20230102094642.74254-4-konrad.dybcio@linaro.org -Stable-dep-of: 75a6e1fdb351 ("arm64: dts: qcom: ipq6018: Fix the PCI I/O port range") -Signed-off-by: Sasha Levin ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 562 +++++++++++++------------- - 1 file changed, 281 insertions(+), 281 deletions(-) - -diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -index d1c02efc2ea9f..8937b10748f3e 100644 ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -87,6 +87,12 @@ - }; - }; - -+ firmware { -+ scm { -+ compatible = "qcom,scm-ipq6018", "qcom,scm"; -+ }; -+ }; -+ - cpu_opp_table: opp-table-cpu { - compatible = "operating-points-v2"; - opp-shared; -@@ -123,12 +129,6 @@ - }; - }; - -- firmware { -- scm { -- compatible = "qcom,scm-ipq6018", "qcom,scm"; -- }; -- }; -- - pmuv8: pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; -+ qcom,rpm-msg-ram = <&rpm_msg_ram>; -+ mboxes = <&apcs_glb 0>; -+ -+ rpm_requests: glink-channel { -+ compatible = "qcom,rpm-ipq6018"; -+ qcom,glink-channels = "rpm_requests"; -+ -+ regulators { -+ compatible = "qcom,rpm-mp5496-regulators"; -+ -+ ipq6018_s2: s2 { -+ regulator-min-microvolt = <725000>; -+ regulator-max-microvolt = <1062500>; -+ regulator-always-on; -+ }; -+ }; -+ }; -+ }; -+ - smem { - compatible = "qcom,smem"; - memory-region = <&smem_region>; -@@ -179,6 +201,102 @@ - dma-ranges; - compatible = "simple-bus"; - -+ qusb_phy_1: qusb@59000 { -+ compatible = "qcom,ipq6018-qusb2-phy"; -+ reg = <0x0 0x00059000 0x0 0x180>; -+ #phy-cells = <0>; -+ -+ clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, -+ <&xo>; -+ clock-names = "cfg_ahb", "ref"; -+ -+ resets = <&gcc GCC_QUSB2_1_PHY_BCR>; -+ status = "disabled"; -+ }; -+ -+ ssphy_0: ssphy@78000 { -+ compatible = "qcom,ipq6018-qmp-usb3-phy"; -+ reg = <0x0 0x00078000 0x0 0x1c4>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ clocks = <&gcc GCC_USB0_AUX_CLK>, -+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>; -+ clock-names = "aux", "cfg_ahb", "ref"; -+ -+ resets = <&gcc GCC_USB0_PHY_BCR>, -+ <&gcc GCC_USB3PHY_0_PHY_BCR>; -+ reset-names = "phy","common"; -+ status = "disabled"; -+ -+ usb0_ssphy: phy@78200 { -+ reg = <0x0 0x00078200 0x0 0x130>, /* Tx */ -+ <0x0 0x00078400 0x0 0x200>, /* Rx */ -+ <0x0 0x00078800 0x0 0x1f8>, /* PCS */ -+ <0x0 0x00078600 0x0 0x044>; /* PCS misc */ -+ #phy-cells = <0>; -+ #clock-cells = <0>; -+ clocks = <&gcc GCC_USB0_PIPE_CLK>; -+ clock-names = "pipe0"; -+ clock-output-names = "gcc_usb0_pipe_clk_src"; -+ }; -+ }; -+ -+ qusb_phy_0: qusb@79000 { -+ compatible = "qcom,ipq6018-qusb2-phy"; -+ reg = <0x0 0x00079000 0x0 0x180>; -+ #phy-cells = <0>; -+ -+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, -+ <&xo>; -+ clock-names = "cfg_ahb", "ref"; -+ -+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>; -+ status = "disabled"; -+ }; -+ -+ pcie_phy: phy@84000 { -+ compatible = "qcom,ipq6018-qmp-pcie-phy"; -+ reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */ -+ status = "disabled"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ clocks = <&gcc GCC_PCIE0_AUX_CLK>, -+ <&gcc GCC_PCIE0_AHB_CLK>; -+ clock-names = "aux", "cfg_ahb"; -+ -+ resets = <&gcc GCC_PCIE0_PHY_BCR>, -+ <&gcc GCC_PCIE0PHY_PHY_BCR>; -+ reset-names = "phy", -+ "common"; -+ -+ pcie_phy0: phy@84200 { -+ reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */ -+ <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */ -+ <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */ -+ <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */ -+ #phy-cells = <0>; -+ -+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>; -+ clock-names = "pipe0"; -+ clock-output-names = "gcc_pcie0_pipe_clk_src"; -+ #clock-cells = <0>; -+ }; -+ }; -+ -+ mdio: mdio@90000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio"; -+ reg = <0x0 0x00090000 0x0 0x64>; -+ clocks = <&gcc GCC_MDIO_AHB_CLK>; -+ clock-names = "gcc_mdio_ahb_clk"; -+ status = "disabled"; -+ }; -+ - prng: qrng@e1000 { - compatible = "qcom,prng-ee"; - reg = <0x0 0x000e3000 0x0 0x1000>; -@@ -257,6 +375,41 @@ - reg = <0x0 0x01937000 0x0 0x21000>; - }; - -+ usb2: usb@70f8800 { -+ compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; -+ reg = <0x0 0x070F8800 0x0 0x400>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ clocks = <&gcc GCC_USB1_MASTER_CLK>, -+ <&gcc GCC_USB1_SLEEP_CLK>, -+ <&gcc GCC_USB1_MOCK_UTMI_CLK>; -+ clock-names = "core", -+ "sleep", -+ "mock_utmi"; -+ -+ assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, -+ <&gcc GCC_USB1_MOCK_UTMI_CLK>; -+ assigned-clock-rates = <133330000>, -+ <24000000>; -+ resets = <&gcc GCC_USB1_BCR>; -+ status = "disabled"; -+ -+ dwc_1: usb@7000000 { -+ compatible = "snps,dwc3"; -+ reg = <0x0 0x07000000 0x0 0xcd00>; -+ interrupts = ; -+ phys = <&qusb_phy_1>; -+ phy-names = "usb2-phy"; -+ tx-fifo-resize; -+ snps,is-utmi-l1-suspend; -+ snps,hird-threshold = /bits/ 8 <0x0>; -+ snps,dis_u2_susphy_quirk; -+ snps,dis_u3_susphy_quirk; -+ dr_mode = "host"; -+ }; -+ }; -+ - blsp_dma: dma-controller@7884000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x0 0x07884000 0x0 0x2b000>; -@@ -366,6 +519,49 @@ - status = "disabled"; - }; - -+ usb3: usb@8af8800 { -+ compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; -+ reg = <0x0 0x08af8800 0x0 0x400>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, -+ <&gcc GCC_USB0_MASTER_CLK>, -+ <&gcc GCC_USB0_SLEEP_CLK>, -+ <&gcc GCC_USB0_MOCK_UTMI_CLK>; -+ clock-names = "cfg_noc", -+ "core", -+ "sleep", -+ "mock_utmi"; -+ -+ assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, -+ <&gcc GCC_USB0_MASTER_CLK>, -+ <&gcc GCC_USB0_MOCK_UTMI_CLK>; -+ assigned-clock-rates = <133330000>, -+ <133330000>, -+ <20000000>; -+ -+ resets = <&gcc GCC_USB0_BCR>; -+ status = "disabled"; -+ -+ dwc_0: usb@8a00000 { -+ compatible = "snps,dwc3"; -+ reg = <0x0 0x08a00000 0x0 0xcd00>; -+ interrupts = ; -+ phys = <&qusb_phy_0>, <&usb0_ssphy>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ clocks = <&xo>; -+ clock-names = "ref"; -+ tx-fifo-resize; -+ snps,is-utmi-l1-suspend; -+ snps,hird-threshold = /bits/ 8 <0x0>; -+ snps,dis_u2_susphy_quirk; -+ snps,dis_u3_susphy_quirk; -+ dr_mode = "host"; -+ }; -+ }; -+ - intc: interrupt-controller@b000000 { - compatible = "qcom,msm-qgic2"; - #address-cells = <2>; -@@ -386,130 +582,29 @@ - }; - }; - -- pcie_phy: phy@84000 { -- compatible = "qcom,ipq6018-qmp-pcie-phy"; -- reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */ -- status = "disabled"; -- #address-cells = <2>; -- #size-cells = <2>; -- ranges; -- -- clocks = <&gcc GCC_PCIE0_AUX_CLK>, -- <&gcc GCC_PCIE0_AHB_CLK>; -- clock-names = "aux", "cfg_ahb"; -- -- resets = <&gcc GCC_PCIE0_PHY_BCR>, -- <&gcc GCC_PCIE0PHY_PHY_BCR>; -- reset-names = "phy", -- "common"; -+ watchdog@b017000 { -+ compatible = "qcom,kpss-wdt"; -+ interrupts = ; -+ reg = <0x0 0x0b017000 0x0 0x40>; -+ clocks = <&sleep_clk>; -+ timeout-sec = <10>; -+ }; - -- pcie_phy0: phy@84200 { -- reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */ -- <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */ -- <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */ -- <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */ -- #phy-cells = <0>; -+ apcs_glb: mailbox@b111000 { -+ compatible = "qcom,ipq6018-apcs-apps-global"; -+ reg = <0x0 0x0b111000 0x0 0x1000>; -+ #clock-cells = <1>; -+ clocks = <&a53pll>, <&xo>; -+ clock-names = "pll", "xo"; -+ #mbox-cells = <1>; -+ }; - -- clocks = <&gcc GCC_PCIE0_PIPE_CLK>; -- clock-names = "pipe0"; -- clock-output-names = "gcc_pcie0_pipe_clk_src"; -- #clock-cells = <0>; -- }; -- }; -- -- pcie0: pci@20000000 { -- compatible = "qcom,pcie-ipq6018"; -- reg = <0x0 0x20000000 0x0 0xf1d>, -- <0x0 0x20000f20 0x0 0xa8>, -- <0x0 0x20001000 0x0 0x1000>, -- <0x0 0x80000 0x0 0x4000>, -- <0x0 0x20100000 0x0 0x1000>; -- reg-names = "dbi", "elbi", "atu", "parf", "config"; -- -- device_type = "pci"; -- linux,pci-domain = <0>; -- bus-range = <0x00 0xff>; -- num-lanes = <1>; -- max-link-speed = <3>; -- #address-cells = <3>; -- #size-cells = <2>; -- -- phys = <&pcie_phy0>; -- phy-names = "pciephy"; -- -- ranges = <0x81000000 0 0x20200000 0 0x20200000 -- 0 0x10000>, /* downstream I/O */ -- <0x82000000 0 0x20220000 0 0x20220000 -- 0 0xfde0000>; /* non-prefetchable memory */ -- -- interrupts = ; -- interrupt-names = "msi"; -- -- #interrupt-cells = <1>; -- interrupt-map-mask = <0 0 0 0x7>; -- interrupt-map = <0 0 0 1 &intc 0 75 -- IRQ_TYPE_LEVEL_HIGH>, /* int_a */ -- <0 0 0 2 &intc 0 78 -- IRQ_TYPE_LEVEL_HIGH>, /* int_b */ -- <0 0 0 3 &intc 0 79 -- IRQ_TYPE_LEVEL_HIGH>, /* int_c */ -- <0 0 0 4 &intc 0 83 -- IRQ_TYPE_LEVEL_HIGH>; /* int_d */ -- -- clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, -- <&gcc GCC_PCIE0_AXI_M_CLK>, -- <&gcc GCC_PCIE0_AXI_S_CLK>, -- <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, -- <&gcc PCIE0_RCHNG_CLK>; -- clock-names = "iface", -- "axi_m", -- "axi_s", -- "axi_bridge", -- "rchng"; -- -- resets = <&gcc GCC_PCIE0_PIPE_ARES>, -- <&gcc GCC_PCIE0_SLEEP_ARES>, -- <&gcc GCC_PCIE0_CORE_STICKY_ARES>, -- <&gcc GCC_PCIE0_AXI_MASTER_ARES>, -- <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, -- <&gcc GCC_PCIE0_AHB_ARES>, -- <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, -- <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; -- reset-names = "pipe", -- "sleep", -- "sticky", -- "axi_m", -- "axi_s", -- "ahb", -- "axi_m_sticky", -- "axi_s_sticky"; -- -- status = "disabled"; -- }; -- -- watchdog@b017000 { -- compatible = "qcom,kpss-wdt"; -- interrupts = ; -- reg = <0x0 0x0b017000 0x0 0x40>; -- clocks = <&sleep_clk>; -- timeout-sec = <10>; -- }; -- -- apcs_glb: mailbox@b111000 { -- compatible = "qcom,ipq6018-apcs-apps-global"; -- reg = <0x0 0x0b111000 0x0 0x1000>; -- #clock-cells = <1>; -- clocks = <&a53pll>, <&xo>; -- clock-names = "pll", "xo"; -- #mbox-cells = <1>; -- }; -- -- a53pll: clock@b116000 { -- compatible = "qcom,ipq6018-a53pll"; -- reg = <0x0 0x0b116000 0x0 0x40>; -- #clock-cells = <0>; -- clocks = <&xo>; -- clock-names = "xo"; -+ a53pll: clock@b116000 { -+ compatible = "qcom,ipq6018-a53pll"; -+ reg = <0x0 0x0b116000 0x0 0x40>; -+ #clock-cells = <0>; -+ clocks = <&xo>; -+ clock-names = "xo"; - }; - - timer@b120000 { -@@ -619,147 +714,74 @@ - }; - }; - -- mdio: mdio@90000 { -- #address-cells = <1>; -- #size-cells = <0>; -- compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio"; -- reg = <0x0 0x00090000 0x0 0x64>; -- clocks = <&gcc GCC_MDIO_AHB_CLK>; -- clock-names = "gcc_mdio_ahb_clk"; -- status = "disabled"; -- }; -- -- qusb_phy_1: qusb@59000 { -- compatible = "qcom,ipq6018-qusb2-phy"; -- reg = <0x0 0x00059000 0x0 0x180>; -- #phy-cells = <0>; -- -- clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, -- <&xo>; -- clock-names = "cfg_ahb", "ref"; -- -- resets = <&gcc GCC_QUSB2_1_PHY_BCR>; -- status = "disabled"; -- }; -- -- usb2: usb@70f8800 { -- compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; -- reg = <0x0 0x070F8800 0x0 0x400>; -- #address-cells = <2>; -- #size-cells = <2>; -- ranges; -- clocks = <&gcc GCC_USB1_MASTER_CLK>, -- <&gcc GCC_USB1_SLEEP_CLK>, -- <&gcc GCC_USB1_MOCK_UTMI_CLK>; -- clock-names = "core", -- "sleep", -- "mock_utmi"; -- -- assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, -- <&gcc GCC_USB1_MOCK_UTMI_CLK>; -- assigned-clock-rates = <133330000>, -- <24000000>; -- resets = <&gcc GCC_USB1_BCR>; -- status = "disabled"; -- -- dwc_1: usb@7000000 { -- compatible = "snps,dwc3"; -- reg = <0x0 0x07000000 0x0 0xcd00>; -- interrupts = ; -- phys = <&qusb_phy_1>; -- phy-names = "usb2-phy"; -- tx-fifo-resize; -- snps,is-utmi-l1-suspend; -- snps,hird-threshold = /bits/ 8 <0x0>; -- snps,dis_u2_susphy_quirk; -- snps,dis_u3_susphy_quirk; -- dr_mode = "host"; -- }; -- }; -+ pcie0: pci@20000000 { -+ compatible = "qcom,pcie-ipq6018"; -+ reg = <0x0 0x20000000 0x0 0xf1d>, -+ <0x0 0x20000f20 0x0 0xa8>, -+ <0x0 0x20001000 0x0 0x1000>, -+ <0x0 0x80000 0x0 0x4000>, -+ <0x0 0x20100000 0x0 0x1000>; -+ reg-names = "dbi", "elbi", "atu", "parf", "config"; - -- ssphy_0: ssphy@78000 { -- compatible = "qcom,ipq6018-qmp-usb3-phy"; -- reg = <0x0 0x00078000 0x0 0x1c4>; -- #address-cells = <2>; -+ device_type = "pci"; -+ linux,pci-domain = <0>; -+ bus-range = <0x00 0xff>; -+ num-lanes = <1>; -+ max-link-speed = <3>; -+ #address-cells = <3>; - #size-cells = <2>; -- ranges; -- -- clocks = <&gcc GCC_USB0_AUX_CLK>, -- <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>; -- clock-names = "aux", "cfg_ahb", "ref"; -- -- resets = <&gcc GCC_USB0_PHY_BCR>, -- <&gcc GCC_USB3PHY_0_PHY_BCR>; -- reset-names = "phy","common"; -- status = "disabled"; -- -- usb0_ssphy: phy@78200 { -- reg = <0x0 0x00078200 0x0 0x130>, /* Tx */ -- <0x0 0x00078400 0x0 0x200>, /* Rx */ -- <0x0 0x00078800 0x0 0x1f8>, /* PCS */ -- <0x0 0x00078600 0x0 0x044>; /* PCS misc */ -- #phy-cells = <0>; -- #clock-cells = <0>; -- clocks = <&gcc GCC_USB0_PIPE_CLK>; -- clock-names = "pipe0"; -- clock-output-names = "gcc_usb0_pipe_clk_src"; -- }; -- }; - -- qusb_phy_0: qusb@79000 { -- compatible = "qcom,ipq6018-qusb2-phy"; -- reg = <0x0 0x00079000 0x0 0x180>; -- #phy-cells = <0>; -+ phys = <&pcie_phy0>; -+ phy-names = "pciephy"; - -- clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, -- <&xo>; -- clock-names = "cfg_ahb", "ref"; -+ ranges = <0x81000000 0 0x20200000 0 0x20200000 -+ 0 0x10000>, /* downstream I/O */ -+ <0x82000000 0 0x20220000 0 0x20220000 -+ 0 0xfde0000>; /* non-prefetchable memory */ - -- resets = <&gcc GCC_QUSB2_0_PHY_BCR>; -- status = "disabled"; -- }; -+ interrupts = ; -+ interrupt-names = "msi"; - -- usb3: usb@8af8800 { -- compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; -- reg = <0x0 0x8af8800 0x0 0x400>; -- #address-cells = <2>; -- #size-cells = <2>; -- ranges; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &intc 0 75 -+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */ -+ <0 0 0 2 &intc 0 78 -+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */ -+ <0 0 0 3 &intc 0 79 -+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ -+ <0 0 0 4 &intc 0 83 -+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - -- clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, -- <&gcc GCC_USB0_MASTER_CLK>, -- <&gcc GCC_USB0_SLEEP_CLK>, -- <&gcc GCC_USB0_MOCK_UTMI_CLK>; -- clock-names = "cfg_noc", -- "core", -- "sleep", -- "mock_utmi"; -+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, -+ <&gcc GCC_PCIE0_AXI_M_CLK>, -+ <&gcc GCC_PCIE0_AXI_S_CLK>, -+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, -+ <&gcc PCIE0_RCHNG_CLK>; -+ clock-names = "iface", -+ "axi_m", -+ "axi_s", -+ "axi_bridge", -+ "rchng"; - -- assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, -- <&gcc GCC_USB0_MASTER_CLK>, -- <&gcc GCC_USB0_MOCK_UTMI_CLK>; -- assigned-clock-rates = <133330000>, -- <133330000>, -- <20000000>; -+ resets = <&gcc GCC_PCIE0_PIPE_ARES>, -+ <&gcc GCC_PCIE0_SLEEP_ARES>, -+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>, -+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>, -+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, -+ <&gcc GCC_PCIE0_AHB_ARES>, -+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, -+ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; -+ reset-names = "pipe", -+ "sleep", -+ "sticky", -+ "axi_m", -+ "axi_s", -+ "ahb", -+ "axi_m_sticky", -+ "axi_s_sticky"; - -- resets = <&gcc GCC_USB0_BCR>; - status = "disabled"; -- -- dwc_0: usb@8a00000 { -- compatible = "snps,dwc3"; -- reg = <0x0 0x8a00000 0x0 0xcd00>; -- interrupts = ; -- phys = <&qusb_phy_0>, <&usb0_ssphy>; -- phy-names = "usb2-phy", "usb3-phy"; -- clocks = <&xo>; -- clock-names = "ref"; -- tx-fifo-resize; -- snps,is-utmi-l1-suspend; -- snps,hird-threshold = /bits/ 8 <0x0>; -- snps,dis_u2_susphy_quirk; -- snps,dis_u3_susphy_quirk; -- dr_mode = "host"; -- }; - }; - }; - -@@ -794,26 +816,4 @@ - #interrupt-cells = <2>; - }; - }; -- -- rpm-glink { -- compatible = "qcom,glink-rpm"; -- interrupts = ; -- qcom,rpm-msg-ram = <&rpm_msg_ram>; -- mboxes = <&apcs_glb 0>; -- -- rpm_requests: glink-channel { -- compatible = "qcom,rpm-ipq6018"; -- qcom,glink-channels = "rpm_requests"; -- -- regulators { -- compatible = "qcom,rpm-mp5496-regulators"; -- -- ipq6018_s2: s2 { -- regulator-min-microvolt = <725000>; -- regulator-max-microvolt = <1062500>; -- regulator-always-on; -- }; -- }; -- }; -- }; - }; --- -2.39.2 - diff --git a/queue-6.2/arm64-dts-qcom-ipq6018-use-lowercase-hex.patch b/queue-6.2/arm64-dts-qcom-ipq6018-use-lowercase-hex.patch deleted file mode 100644 index 15b5770146f..00000000000 --- a/queue-6.2/arm64-dts-qcom-ipq6018-use-lowercase-hex.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 953ff3becaee3fb9a4e3e7c81dd687b6481d7f4a Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 12 Dec 2022 12:10:29 +0100 -Subject: arm64: dts: qcom: ipq6018: Use lowercase hex - -From: Konrad Dybcio - -[ Upstream commit 0431dba3733bf52dacf7382e7b0c1b4c0b59e88d ] - -Use lowercase hex, as that's the preferred and overwhermingly present -style. - -Signed-off-by: Konrad Dybcio -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20221212111037.98160-2-konrad.dybcio@linaro.org -Stable-dep-of: 75a6e1fdb351 ("arm64: dts: qcom: ipq6018: Fix the PCI I/O port range") -Signed-off-by: Sasha Levin ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -index 5d453f11acd98..2ceae73a6069e 100644 ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -679,7 +679,7 @@ - - ssphy_0: ssphy@78000 { - compatible = "qcom,ipq6018-qmp-usb3-phy"; -- reg = <0x0 0x78000 0x0 0x1C4>; -+ reg = <0x0 0x78000 0x0 0x1c4>; - #address-cells = <2>; - #size-cells = <2>; - ranges; -@@ -696,7 +696,7 @@ - usb0_ssphy: phy@78200 { - reg = <0x0 0x00078200 0x0 0x130>, /* Tx */ - <0x0 0x00078400 0x0 0x200>, /* Rx */ -- <0x0 0x00078800 0x0 0x1F8>, /* PCS */ -+ <0x0 0x00078800 0x0 0x1f8>, /* PCS */ - <0x0 0x00078600 0x0 0x044>; /* PCS misc */ - #phy-cells = <0>; - #clock-cells = <0>; -@@ -721,7 +721,7 @@ - - usb3: usb@8af8800 { - compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; -- reg = <0x0 0x8AF8800 0x0 0x400>; -+ reg = <0x0 0x8af8800 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges; -@@ -747,7 +747,7 @@ - - dwc_0: usb@8a00000 { - compatible = "snps,dwc3"; -- reg = <0x0 0x8A00000 0x0 0xcd00>; -+ reg = <0x0 0x8a00000 0x0 0xcd00>; - interrupts = ; - phys = <&qusb_phy_0>, <&usb0_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; --- -2.39.2 - diff --git a/queue-6.2/arm64-dts-qcom-sdm845-align-tlmm-pin-configuration-w.patch b/queue-6.2/arm64-dts-qcom-sdm845-align-tlmm-pin-configuration-w.patch deleted file mode 100644 index 5f83f9bf120..00000000000 --- a/queue-6.2/arm64-dts-qcom-sdm845-align-tlmm-pin-configuration-w.patch +++ /dev/null @@ -1,2610 +0,0 @@ -From 6f38379a8def4eb47d5a78dc924f5d62fc2fce21 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Thu, 22 Dec 2022 16:13:18 +0100 -Subject: arm64: dts: qcom: sdm845: align TLMM pin configuration with DT schema - -From: Krzysztof Kozlowski - -[ Upstream commit d05e342882e4fb2ccd8e4b6af00b0b82e22ad325 ] - -DT schema expects TLMM pin configuration nodes to be named with -'-state' suffix and their optional children with '-pins' suffix. - -Signed-off-by: Krzysztof Kozlowski -Reviewed-by: Douglas Anderson -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20221222151319.122398-3-krzysztof.kozlowski@linaro.org -Stable-dep-of: 37f7349b56de ("arm64: dts: sdm845: Rename qspi data12 as data23") -Signed-off-by: Sasha Levin ---- - arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 397 ++++------ - arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 93 +-- - .../arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 60 +- - arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts | 2 +- - arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 77 +- - .../boot/dts/qcom/sdm845-oneplus-common.dtsi | 101 +-- - .../boot/dts/qcom/sdm845-shift-axolotl.dts | 150 ++-- - .../dts/qcom/sdm845-sony-xperia-tama.dtsi | 6 +- - .../qcom/sdm845-xiaomi-beryllium-common.dtsi | 12 +- - .../boot/dts/qcom/sdm845-xiaomi-polaris.dts | 21 +- - arch/arm64/boot/dts/qcom/sdm845.dtsi | 689 ++++++++---------- - .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 53 +- - .../boot/dts/qcom/sdm850-samsung-w737.dts | 121 +-- - 13 files changed, 701 insertions(+), 1081 deletions(-) - -diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi -index ca676e04687b0..246d9339728c2 100644 ---- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi -+++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi -@@ -995,104 +995,69 @@ ap_ts_i2c: &i2c14 { - /* PINCTRL - additions to nodes defined in sdm845.dtsi */ - - &qspi_cs0 { -- pinconf { -- pins = "gpio90"; -- bias-disable; -- }; -+ bias-disable; - }; - - &qspi_clk { -- pinconf { -- pins = "gpio95"; -- bias-disable; -- }; -+ bias-disable; - }; - - &qspi_data01 { -- pinconf { -- pins = "gpio91", "gpio92"; -- -- /* High-Z when no transfers; nice to park the lines */ -- bias-pull-up; -- }; -+ /* High-Z when no transfers; nice to park the lines */ -+ bias-pull-up; - }; - - &qup_i2c3_default { -- pinconf { -- pins = "gpio41", "gpio42"; -- drive-strength = <2>; -+ drive-strength = <2>; - -- /* Has external pullup */ -- bias-disable; -- }; -+ /* Has external pullup */ -+ bias-disable; - }; - - &qup_i2c11_default { -- pinconf { -- pins = "gpio31", "gpio32"; -- drive-strength = <2>; -+ drive-strength = <2>; - -- /* Has external pullup */ -- bias-disable; -- }; -+ /* Has external pullup */ -+ bias-disable; - }; - - &qup_i2c12_default { -- pinconf { -- pins = "gpio49", "gpio50"; -- drive-strength = <2>; -+ drive-strength = <2>; - -- /* Has external pullup */ -- bias-disable; -- }; -+ /* Has external pullup */ -+ bias-disable; - }; - - &qup_i2c14_default { -- pinconf { -- pins = "gpio33", "gpio34"; -- drive-strength = <2>; -+ drive-strength = <2>; - -- /* Has external pullup */ -- bias-disable; -- }; -+ /* Has external pullup */ -+ bias-disable; - }; - - &qup_spi0_default { -- pinconf { -- pins = "gpio0", "gpio1", "gpio2", "gpio3"; -- drive-strength = <2>; -- bias-disable; -- }; -+ drive-strength = <2>; -+ bias-disable; - }; - - &qup_spi5_default { -- pinconf { -- pins = "gpio85", "gpio86", "gpio87", "gpio88"; -- drive-strength = <2>; -- bias-disable; -- }; -+ drive-strength = <2>; -+ bias-disable; - }; - - &qup_spi10_default { -- pinconf { -- pins = "gpio53", "gpio54", "gpio55", "gpio56"; -- drive-strength = <2>; -- bias-disable; -- }; -+ drive-strength = <2>; -+ bias-disable; - }; - --&qup_uart9_default { -- pinconf-tx { -- pins = "gpio4"; -- drive-strength = <2>; -- bias-disable; -- }; -+&qup_uart9_rx { -+ drive-strength = <2>; -+ bias-pull-up; -+}; - -- pinconf-rx { -- pins = "gpio5"; -- drive-strength = <2>; -- bias-pull-up; -- }; -+&qup_uart9_tx { -+ drive-strength = <2>; -+ bias-disable; - }; - - /* PINCTRL - board-specific pinctrl */ -@@ -1180,243 +1145,153 @@ ap_ts_i2c: &i2c14 { - output-low; - }; - -- ap_edp_bklten: ap-edp-bklten { -- pinmux { -- pins = "gpio37"; -- function = "gpio"; -- }; -- -- pinconf { -- pins = "gpio37"; -- drive-strength = <2>; -- bias-disable; -- }; -+ ap_edp_bklten: ap-edp-bklten-state { -+ pins = "gpio37"; -+ function = "gpio"; -+ drive-strength = <2>; -+ bias-disable; - }; - -- bios_flash_wp_r_l: bios-flash-wp-r-l { -- pinmux { -- pins = "gpio128"; -- function = "gpio"; -- input-enable; -- }; -- -- pinconf { -- pins = "gpio128"; -- bias-disable; -- }; -+ bios_flash_wp_r_l: bios-flash-wp-r-l-state { -+ pins = "gpio128"; -+ function = "gpio"; -+ input-enable; -+ bias-disable; - }; - -- ec_ap_int_l: ec-ap-int-l { -- pinmux { -- pins = "gpio122"; -- function = "gpio"; -- input-enable; -- }; -- -- pinconf { -- pins = "gpio122"; -- bias-pull-up; -- }; -+ ec_ap_int_l: ec-ap-int-l-state { -+ pins = "gpio122"; -+ function = "gpio"; -+ input-enable; -+ bias-pull-up; - }; - -- edp_brij_en: edp-brij-en { -- pinmux { -- pins = "gpio102"; -- function = "gpio"; -- }; -- -- pinconf { -- pins = "gpio102"; -- drive-strength = <2>; -- bias-disable; -- }; -+ edp_brij_en: edp-brij-en-state { -+ pins = "gpio102"; -+ function = "gpio"; -+ drive-strength = <2>; -+ bias-disable; - }; - -- edp_brij_irq: edp-brij-irq { -- pinmux { -- pins = "gpio10"; -- function = "gpio"; -- }; -- -- pinconf { -- pins = "gpio10"; -- drive-strength = <2>; -- bias-pull-down; -- }; -+ edp_brij_irq: edp-brij-irq-state { -+ pins = "gpio10"; -+ function = "gpio"; -+ drive-strength = <2>; -+ bias-pull-down; - }; - -- en_pp3300_dx_edp: en-pp3300-dx-edp { -- pinmux { -- pins = "gpio43"; -- function = "gpio"; -- }; -- -- pinconf { -- pins = "gpio43"; -- drive-strength = <2>; -- bias-disable; -- }; -+ en_pp3300_dx_edp: en-pp3300-dx-edp-state { -+ pins = "gpio43"; -+ function = "gpio"; -+ drive-strength = <2>; -+ bias-disable; - }; - -- h1_ap_int_odl: h1-ap-int-odl { -- pinmux { -- pins = "gpio129"; -- function = "gpio"; -- input-enable; -- }; -- -- pinconf { -- pins = "gpio129"; -- bias-pull-up; -- }; -+ h1_ap_int_odl: h1-ap-int-odl-state { -+ pins = "gpio129"; -+ function = "gpio"; -+ input-enable; -+ bias-pull-up; - }; - -- pen_eject_odl: pen-eject-odl { -- pinmux { -- pins = "gpio119"; -- function = "gpio"; -- bias-pull-up; -- }; -+ pen_eject_odl: pen-eject-odl-state { -+ pins = "gpio119"; -+ function = "gpio"; -+ bias-pull-up; - }; - -- pen_irq_l: pen-irq-l { -- pinmux { -- pins = "gpio24"; -- function = "gpio"; -- }; -+ pen_irq_l: pen-irq-l-state { -+ pins = "gpio24"; -+ function = "gpio"; - -- pinconf { -- pins = "gpio24"; -- -- /* Has external pullup */ -- bias-disable; -- }; -+ /* Has external pullup */ -+ bias-disable; - }; - -- pen_pdct_l: pen-pdct-l { -- pinmux { -- pins = "gpio63"; -- function = "gpio"; -- }; -- -- pinconf { -- pins = "gpio63"; -+ pen_pdct_l: pen-pdct-l-state { -+ pins = "gpio63"; -+ function = "gpio"; - -- /* Has external pullup */ -- bias-disable; -- }; -+ /* Has external pullup */ -+ bias-disable; - }; - -- pen_rst_l: pen-rst-l { -- pinmux { -- pins = "gpio23"; -- function = "gpio"; -- }; -- -- pinconf { -- pins = "gpio23"; -- bias-disable; -- drive-strength = <2>; -+ pen_rst_l: pen-rst-l-state { -+ pins = "gpio23"; -+ function = "gpio"; -+ bias-disable; -+ drive-strength = <2>; - -- /* -- * The pen driver doesn't currently support -- * driving this reset line. By specifying -- * output-high here we're relying on the fact -- * that this pin has a default pulldown at boot -- * (which makes sure the pen was in reset if it -- * was powered) and then we set it high here to -- * take it out of reset. Better would be if the -- * pen driver could control this and we could -- * remove "output-high" here. -- */ -- output-high; -- }; -+ /* -+ * The pen driver doesn't currently support -+ * driving this reset line. By specifying -+ * output-high here we're relying on the fact -+ * that this pin has a default pulldown at boot -+ * (which makes sure the pen was in reset if it -+ * was powered) and then we set it high here to -+ * take it out of reset. Better would be if the -+ * pen driver could control this and we could -+ * remove "output-high" here. -+ */ -+ output-high; - }; - -- sdc2_clk: sdc2-clk { -- pinconf { -- pins = "sdc2_clk"; -- bias-disable; -+ sdc2_clk: sdc2-clk-state { -+ pins = "sdc2_clk"; -+ bias-disable; - -- /* -- * It seems that mmc_test reports errors if drive -- * strength is not 16. -- */ -- drive-strength = <16>; -- }; -+ /* -+ * It seems that mmc_test reports errors if drive -+ * strength is not 16. -+ */ -+ drive-strength = <16>; - }; - -- sdc2_cmd: sdc2-cmd { -- pinconf { -- pins = "sdc2_cmd"; -- bias-pull-up; -- drive-strength = <16>; -- }; -+ sdc2_cmd: sdc2-cmd-state { -+ pins = "sdc2_cmd"; -+ bias-pull-up; -+ drive-strength = <16>; - }; - -- sdc2_data: sdc2-data { -- pinconf { -- pins = "sdc2_data"; -- bias-pull-up; -- drive-strength = <16>; -- }; -+ sdc2_data: sdc2-data-state { -+ pins = "sdc2_data"; -+ bias-pull-up; -+ drive-strength = <16>; - }; - -- sd_cd_odl: sd-cd-odl { -- pinmux { -- pins = "gpio44"; -- function = "gpio"; -- }; -- -- pinconf { -- pins = "gpio44"; -- bias-pull-up; -- }; -+ sd_cd_odl: sd-cd-odl-state { -+ pins = "gpio44"; -+ function = "gpio"; -+ bias-pull-up; - }; - -- ts_int_l: ts-int-l { -- pinmux { -- pins = "gpio125"; -- function = "gpio"; -- }; -- -- pinconf { -- pins = "gpio125"; -- bias-pull-up; -- }; -+ ts_int_l: ts-int-l-state { -+ pins = "gpio125"; -+ function = "gpio"; -+ bias-pull-up; - }; - -- ts_reset_l: ts-reset-l { -- pinmux { -- pins = "gpio118"; -- function = "gpio"; -- }; -- -- pinconf { -- pins = "gpio118"; -- bias-disable; -- drive-strength = <2>; -- }; -+ ts_reset_l: ts-reset-l-state { -+ pins = "gpio118"; -+ function = "gpio"; -+ bias-disable; -+ drive-strength = <2>; - }; - -- ap_suspend_l_assert: ap_suspend_l_assert { -- config { -- pins = "gpio126"; -- function = "gpio"; -- bias-disable; -- drive-strength = <2>; -- output-low; -- }; -+ ap_suspend_l_assert: ap-suspend-l-assert-state { -+ pins = "gpio126"; -+ function = "gpio"; -+ bias-disable; -+ drive-strength = <2>; -+ output-low; - }; - -- ap_suspend_l_deassert: ap_suspend_l_deassert { -- config { -- pins = "gpio126"; -- function = "gpio"; -- bias-disable; -- drive-strength = <2>; -- output-high; -- }; -+ ap_suspend_l_deassert: ap-suspend-l-deassert-state { -+ pins = "gpio126"; -+ function = "gpio"; -+ bias-disable; -+ drive-strength = <2>; -+ output-high; - }; - }; - -diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts -index 75a4645936232..8d814a139daf7 100644 ---- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts -+++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts -@@ -825,8 +825,8 @@ - }; - - &tlmm { -- cam0_default: cam0_default { -- rst { -+ cam0_default: cam0-default-state { -+ rst-pins { - pins = "gpio9"; - function = "gpio"; - -@@ -834,7 +834,7 @@ - bias-disable; - }; - -- mclk0 { -+ mclk0-pins { - pins = "gpio13"; - function = "cam_mclk"; - -@@ -843,8 +843,8 @@ - }; - }; - -- cam3_default: cam3_default { -- rst { -+ cam3_default: cam3-default-state { -+ rst-pins { - function = "gpio"; - pins = "gpio21"; - -@@ -852,7 +852,7 @@ - bias-disable; - }; - -- mclk3 { -+ mclk3-pins { - function = "cam_mclk"; - pins = "gpio16"; - -@@ -861,7 +861,7 @@ - }; - }; - -- dsi_sw_sel: dsi-sw-sel { -+ dsi_sw_sel: dsi-sw-sel-state { - pins = "gpio120"; - function = "gpio"; - -@@ -870,20 +870,20 @@ - output-high; - }; - -- lt9611_irq_pin: lt9611-irq { -+ lt9611_irq_pin: lt9611-irq-state { - pins = "gpio84"; - function = "gpio"; - bias-disable; - }; - -- pcie0_default_state: pcie0-default { -- clkreq { -+ pcie0_default_state: pcie0-default-state { -+ clkreq-pins { - pins = "gpio36"; - function = "pci_e0"; - bias-pull-up; - }; - -- reset-n { -+ reset-n-pins { - pins = "gpio35"; - function = "gpio"; - -@@ -892,7 +892,7 @@ - bias-pull-down; - }; - -- wake-n { -+ wake-n-pins { - pins = "gpio37"; - function = "gpio"; - -@@ -901,7 +901,7 @@ - }; - }; - -- pcie0_pwren_state: pcie0-pwren { -+ pcie0_pwren_state: pcie0-pwren-state { - pins = "gpio90"; - function = "gpio"; - -@@ -909,8 +909,8 @@ - bias-disable; - }; - -- pcie1_default_state: pcie1-default { -- perst-n { -+ pcie1_default_state: pcie1-default-state { -+ perst-n-pins { - pins = "gpio102"; - function = "gpio"; - -@@ -918,13 +918,13 @@ - bias-disable; - }; - -- clkreq { -+ clkreq-pins { - pins = "gpio103"; - function = "pci_e1"; - bias-pull-up; - }; - -- wake-n { -+ wake-n-pins { - pins = "gpio11"; - function = "gpio"; - -@@ -932,7 +932,7 @@ - bias-pull-up; - }; - -- reset-n { -+ reset-n-pins { - pins = "gpio75"; - function = "gpio"; - -@@ -942,8 +942,8 @@ - }; - }; - -- sdc2_default_state: sdc2-default { -- clk { -+ sdc2_default_state: sdc2-default-state { -+ clk-pins { - pins = "sdc2_clk"; - bias-disable; - -@@ -954,26 +954,26 @@ - drive-strength = <16>; - }; - -- cmd { -+ cmd-pins { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - -- data { -+ data-pins { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <10>; - }; - }; - -- sdc2_card_det_n: sd-card-det-n { -+ sdc2_card_det_n: sd-card-det-n-state { - pins = "gpio126"; - function = "gpio"; - bias-pull-up; - }; - -- wcd_intr_default: wcd_intr_default { -+ wcd_intr_default: wcd-intr-default-state { - pins = "gpio54"; - function = "gpio"; - -@@ -985,6 +985,8 @@ - - &uart3 { - label = "LS-UART0"; -+ pinctrl-0 = <&qup_uart3_4pin>; -+ - status = "disabled"; - }; - -@@ -1130,39 +1132,22 @@ - - /* PINCTRL - additions to nodes defined in sdm845.dtsi */ - &qup_spi2_default { -- pinconf { -- pins = "gpio27", "gpio28", "gpio29", "gpio30"; -- drive-strength = <16>; -- }; --}; -- --&qup_uart3_default { -- pinmux { -- pins = "gpio41", "gpio42", "gpio43", "gpio44"; -- function = "qup3"; -- }; -+ drive-strength = <16>; - }; - - &qup_i2c10_default { -- pinconf { -- pins = "gpio55", "gpio56"; -- drive-strength = <2>; -- bias-disable; -- }; -+ drive-strength = <2>; -+ bias-disable; - }; - --&qup_uart9_default { -- pinconf-tx { -- pins = "gpio4"; -- drive-strength = <2>; -- bias-disable; -- }; -+&qup_uart9_rx { -+ drive-strength = <2>; -+ bias-pull-up; -+}; - -- pinconf-rx { -- pins = "gpio5"; -- drive-strength = <2>; -- bias-pull-up; -- }; -+&qup_uart9_tx { -+ drive-strength = <2>; -+ bias-disable; - }; - - &pm8998_gpio { -@@ -1171,8 +1156,6 @@ - - /* PINCTRL - additions to nodes defined in sdm845.dtsi */ - &qup_spi0_default { -- config { -- drive-strength = <6>; -- bias-disable; -- }; -+ drive-strength = <6>; -+ bias-disable; - }; -diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi -index 943287804e1a6..539d82d2f84da 100644 ---- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi -+++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi -@@ -553,48 +553,36 @@ - &tlmm { - gpio-reserved-ranges = <28 4>, <81 4>; - -- sdc2_clk: sdc2-clk { -- pinconf { -- pins = "sdc2_clk"; -- bias-disable; -- -- /* -- * It seems that mmc_test reports errors if drive -- * strength is not 16 on clk, cmd, and data pins. -- * -- * TODO: copy-pasted from mtp, try other values -- * on these devices. -- */ -- drive-strength = <16>; -- }; -+ sdc2_clk: sdc2-clk-state { -+ pins = "sdc2_clk"; -+ bias-disable; -+ -+ /* -+ * It seems that mmc_test reports errors if drive -+ * strength is not 16 on clk, cmd, and data pins. -+ * -+ * TODO: copy-pasted from mtp, try other values -+ * on these devices. -+ */ -+ drive-strength = <16>; - }; - -- sdc2_cmd: sdc2-cmd { -- pinconf { -- pins = "sdc2_cmd"; -- bias-pull-up; -- drive-strength = <16>; -- }; -+ sdc2_cmd: sdc2-cmd-state { -+ pins = "sdc2_cmd"; -+ bias-pull-up; -+ drive-strength = <16>; - }; - -- sdc2_data: sdc2-data { -- pinconf { -- pins = "sdc2_data"; -- bias-pull-up; -- drive-strength = <16>; -- }; -+ sdc2_data: sdc2-data-state { -+ pins = "sdc2_data"; -+ bias-pull-up; -+ drive-strength = <16>; - }; - -- sd_card_det_n: sd-card-det-n { -- pinmux { -- pins = "gpio126"; -- function = "gpio"; -- }; -- -- pinconf { -- pins = "gpio126"; -- bias-pull-up; -- }; -+ sd_card_det_n: sd-card-det-n-state { -+ pins = "gpio126"; -+ function = "gpio"; -+ bias-pull-up; - }; - }; - -diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts b/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts -index 7d967a104b3eb..a12723310c8b6 100644 ---- a/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts -+++ b/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts -@@ -58,7 +58,7 @@ - }; - - &tlmm { -- thinq_key_default: thinq-key-default { -+ thinq_key_default: thinq-key-default-state { - pins = "gpio89"; - function = "gpio"; - -diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts -index de2d10e0315af..7c5478b71f8b1 100644 ---- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts -+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts -@@ -719,68 +719,49 @@ - /* PINCTRL - additions to nodes defined in sdm845.dtsi */ - - &qup_i2c10_default { -- pinconf { -- pins = "gpio55", "gpio56"; -- drive-strength = <2>; -- bias-disable; -- }; -+ drive-strength = <2>; -+ bias-disable; - }; - --&qup_uart9_default { -- pinconf-tx { -- pins = "gpio4"; -- drive-strength = <2>; -- bias-disable; -- }; -+&qup_uart9_rx { -+ drive-strength = <2>; -+ bias-pull-up; -+}; - -- pinconf-rx { -- pins = "gpio5"; -- drive-strength = <2>; -- bias-pull-up; -- }; -+&qup_uart9_tx { -+ drive-strength = <2>; -+ bias-disable; - }; - - &tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; - -- sdc2_clk: sdc2-clk { -- pinconf { -- pins = "sdc2_clk"; -- bias-disable; -+ sdc2_clk: sdc2-clk-state { -+ pins = "sdc2_clk"; -+ bias-disable; - -- /* -- * It seems that mmc_test reports errors if drive -- * strength is not 16 on clk, cmd, and data pins. -- */ -- drive-strength = <16>; -- }; -+ /* -+ * It seems that mmc_test reports errors if drive -+ * strength is not 16 on clk, cmd, and data pins. -+ */ -+ drive-strength = <16>; - }; - -- sdc2_cmd: sdc2-cmd { -- pinconf { -- pins = "sdc2_cmd"; -- bias-pull-up; -- drive-strength = <16>; -- }; -+ sdc2_cmd: sdc2-cmd-state { -+ pins = "sdc2_cmd"; -+ bias-pull-up; -+ drive-strength = <16>; - }; - -- sdc2_data: sdc2-data { -- pinconf { -- pins = "sdc2_data"; -- bias-pull-up; -- drive-strength = <16>; -- }; -+ sdc2_data: sdc2-data-state { -+ pins = "sdc2_data"; -+ bias-pull-up; -+ drive-strength = <16>; - }; - -- sd_card_det_n: sd-card-det-n { -- pinmux { -- pins = "gpio126"; -- function = "gpio"; -- }; -- -- pinconf { -- pins = "gpio126"; -- bias-pull-up; -- }; -+ sd_card_det_n: sd-card-det-n-state { -+ pins = "gpio126"; -+ function = "gpio"; -+ bias-pull-up; - }; - }; -diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi -index 42cf4dd5ea284..738c9d0b322f6 100644 ---- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi -+++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi -@@ -474,35 +474,24 @@ - status = "okay"; - }; - --&qup_i2c12_default { -- mux { -- pins = "gpio49", "gpio50"; -- function = "qup12"; -- drive-strength = <2>; -- bias-disable; -- }; -+&qup_i2c10_default { -+ drive-strength = <2>; -+ bias-disable; - }; - --&qup_i2c10_default { -- pinconf { -- pins = "gpio55", "gpio56"; -- drive-strength = <2>; -- bias-disable; -- }; -+&qup_i2c12_default { -+ drive-strength = <2>; -+ bias-disable; - }; - --&qup_uart9_default { -- pinconf-tx { -- pins = "gpio4"; -- drive-strength = <2>; -- bias-disable; -- }; -+&qup_uart9_rx { -+ drive-strength = <2>; -+ bias-pull-up; -+}; - -- pinconf-rx { -- pins = "gpio5"; -- drive-strength = <2>; -- bias-pull-up; -- }; -+&qup_uart9_tx { -+ drive-strength = <2>; -+ bias-disable; - }; - - &uart6 { -@@ -588,51 +577,41 @@ - &tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; - -- tri_state_key_default: tri_state_key_default { -- mux { -- pins = "gpio40", "gpio42", "gpio26"; -- function = "gpio"; -- drive-strength = <2>; -- bias-disable; -- }; -+ tri_state_key_default: tri-state-key-default-state { -+ pins = "gpio40", "gpio42", "gpio26"; -+ function = "gpio"; -+ drive-strength = <2>; -+ bias-disable; - }; - -- ts_default_pins: ts-int { -- mux { -- pins = "gpio99", "gpio125"; -- function = "gpio"; -- drive-strength = <16>; -- bias-pull-up; -- }; -+ ts_default_pins: ts-int-state { -+ pins = "gpio99", "gpio125"; -+ function = "gpio"; -+ drive-strength = <16>; -+ bias-pull-up; - }; - -- panel_reset_pins: panel-reset { -- mux { -- pins = "gpio6", "gpio25", "gpio26"; -- function = "gpio"; -- drive-strength = <8>; -- bias-disable; -- }; -+ panel_reset_pins: panel-reset-state { -+ pins = "gpio6", "gpio25", "gpio26"; -+ function = "gpio"; -+ drive-strength = <8>; -+ bias-disable; - }; - -- panel_te_pin: panel-te { -- mux { -- pins = "gpio10"; -- function = "mdp_vsync"; -- drive-strength = <2>; -- bias-disable; -- input-enable; -- }; -+ panel_te_pin: panel-te-state { -+ pins = "gpio10"; -+ function = "mdp_vsync"; -+ drive-strength = <2>; -+ bias-disable; -+ input-enable; - }; - -- panel_esd_pin: panel-esd { -- mux { -- pins = "gpio30"; -- function = "gpio"; -- drive-strength = <2>; -- bias-pull-down; -- input-enable; -- }; -+ panel_esd_pin: panel-esd-state { -+ pins = "gpio30"; -+ function = "gpio"; -+ drive-strength = <2>; -+ bias-pull-down; -+ input-enable; - }; - }; - -diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts -index e6191602c70a8..34a2df3fc6e58 100644 ---- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts -+++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts -@@ -554,18 +554,14 @@ - }; - }; - --&qup_uart9_default { -- pinconf-rx { -- pins = "gpio5"; -- drive-strength = <2>; -- bias-pull-up; -- }; -+&qup_uart9_rx { -+ drive-strength = <2>; -+ bias-pull-up; -+}; - -- pinconf-tx { -- pins = "gpio4"; -- drive-strength = <2>; -- bias-disable; -- }; -+&qup_uart9_tx { -+ drive-strength = <2>; -+ bias-disable; - }; - - &qupv3_id_0 { -@@ -579,110 +575,62 @@ - &tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; - -- sde_dsi_active: sde-dsi-active { -- mux { -- pins = "gpio6", "gpio11"; -- function = "gpio"; -- }; -- -- config { -- pins = "gpio6", "gpio11"; -- drive-strength = <8>; -- bias-disable; -- }; -+ sde_dsi_active: sde-dsi-active-state { -+ pins = "gpio6", "gpio11"; -+ function = "gpio"; -+ drive-strength = <8>; -+ bias-disable; - }; - -- sde_dsi_suspend: sde-dsi-suspend { -- mux { -- pins = "gpio6", "gpio11"; -- function = "gpio"; -- }; -- -- config { -- pins = "gpio6", "gpio11"; -- drive-strength = <2>; -- bias-pull-down; -- }; -+ sde_dsi_suspend: sde-dsi-suspend-state { -+ pins = "gpio6", "gpio11"; -+ function = "gpio"; -+ drive-strength = <2>; -+ bias-pull-down; - }; - -- sde_te_active: sde-te-active { -- mux { -- pins = "gpio10"; -- function = "mdp_vsync"; -- }; -- -- config { -- pins = "gpio10"; -- drive-strength = <2>; -- bias-pull-down; -- }; -+ sde_te_active: sde-te-active-state { -+ pins = "gpio10"; -+ function = "mdp_vsync"; -+ drive-strength = <2>; -+ bias-pull-down; - }; - -- sde_te_suspend: sde-te-suspend { -- mux { -- pins = "gpio10"; -- function = "mdp_vsync"; -- }; -- -- config { -- pins = "gpio10"; -- drive-strength = <2>; -- bias-pull-down; -- }; -+ sde_te_suspend: sde-te-suspend-state { -+ pins = "gpio10"; -+ function = "mdp_vsync"; -+ drive-strength = <2>; -+ bias-pull-down; - }; - -- ts_int_active: ts-int-active { -- mux { -- pins = "gpio125"; -- function = "gpio"; -- }; -- -- config { -- pins = "gpio125"; -- drive-strength = <8>; -- bias-pull-up; -- input-enable; -- }; -+ ts_int_active: ts-int-active-state { -+ pins = "gpio125"; -+ function = "gpio"; -+ drive-strength = <8>; -+ bias-pull-up; -+ input-enable; - }; - -- ts_int_suspend: ts-int-suspend { -- mux { -- pins = "gpio125"; -- function = "gpio"; -- }; -- -- config { -- pins = "gpio125"; -- drive-strength = <2>; -- bias-pull-down; -- input-enable; -- }; -+ ts_int_suspend: ts-int-suspend-state { -+ pins = "gpio125"; -+ function = "gpio"; -+ drive-strength = <2>; -+ bias-pull-down; -+ input-enable; - }; - -- ts_reset_active: ts-reset-active { -- mux { -- pins = "gpio99"; -- function = "gpio"; -- }; -- -- config { -- pins = "gpio99"; -- drive-strength = <8>; -- bias-pull-up; -- }; -+ ts_reset_active: ts-reset-active-state { -+ pins = "gpio99"; -+ function = "gpio"; -+ drive-strength = <8>; -+ bias-pull-up; - }; - -- ts_reset_suspend: ts-reset-suspend { -- mux { -- pins = "gpio99"; -- function = "gpio"; -- }; -- -- config { -- pins = "gpio99"; -- drive-strength = <2>; -- bias-pull-down; -- }; -+ ts_reset_suspend: ts-reset-suspend-state { -+ pins = "gpio99"; -+ function = "gpio"; -+ drive-strength = <2>; -+ bias-pull-down; - }; - }; - -diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi -index 87dd0fc367476..20c4e4699ac72 100644 ---- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi -+++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi -@@ -383,19 +383,19 @@ - gpio-reserved-ranges = <0 4>, <81 4>; - - sdc2_default_state: sdc2-default-state { -- clk { -+ clk-pins { - pins = "sdc2_clk"; - drive-strength = <16>; - bias-disable; - }; - -- cmd { -+ cmd-pins { - pins = "sdc2_cmd"; - drive-strength = <10>; - bias-pull-up; - }; - -- data { -+ data-pins { - pins = "sdc2_data"; - drive-strength = <10>; - bias-pull-up; -diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi -index d2866155dd870..eb761dfff8783 100644 ---- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi -+++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi -@@ -440,33 +440,33 @@ - &tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; - -- sdc2_default_state: sdc2-default { -- clk { -+ sdc2_default_state: sdc2-default-state { -+ clk-pins { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <16>; - }; - -- cmd { -+ cmd-pins { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - -- data { -+ data-pins { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <10>; - }; - }; - -- sdc2_card_det_n: sd-card-det-n { -+ sdc2_card_det_n: sd-card-det-n-state { - pins = "gpio126"; - function = "gpio"; - bias-pull-up; - }; - -- wcd_intr_default: wcd_intr_default { -+ wcd_intr_default: wcd-intr-default-state { - pins = "gpio54"; - function = "gpio"; - -diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts -index fba229d0bd108..8ca1487272820 100644 ---- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts -+++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts -@@ -565,24 +565,21 @@ - }; - - &qup_i2c14_default { -- pinconf { -- pins = "gpio33", "gpio34"; -- drive-strength = <2>; -- bias-disable; -- }; -+ drive-strength = <2>; -+ bias-disable; - }; - - &tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; - -- ts_reset_default: ts-reset-default { -+ ts_reset_default: ts-reset-default-state { - pins = "gpio99"; - function = "gpio"; - drive-strength = <16>; - output-high; - }; - -- ts_int_default: ts-int-default { -+ ts_int_default: ts-int-default-state { - pins = "gpio125"; - function = "gpio"; - bias-pull-down; -@@ -590,14 +587,14 @@ - input-enable; - }; - -- ts_reset_sleep: ts-reset-sleep { -+ ts_reset_sleep: ts-reset-sleep-state { - pins = "gpio99"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - }; - -- ts_int_sleep: ts-int-sleep { -+ ts_int_sleep: ts-int-sleep-state { - pins = "gpio125"; - function = "gpio"; - bias-pull-down; -@@ -605,21 +602,21 @@ - input-enable; - }; - -- sde_dsi_active: sde-dsi-active { -+ sde_dsi_active: sde-dsi-active-state { - pins = "gpio6", "gpio10"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; - -- sde_dsi_suspend: sde-dsi-suspend { -+ sde_dsi_suspend: sde-dsi-suspend-state { - pins = "gpio6", "gpio10"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - -- wcd_intr_default: wcd-intr-default { -+ wcd_intr_default: wcd-intr-default-state { - pins = "gpio54"; - function = "gpio"; - input-enable; -diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi -index 0b263a7da981c..481b721881cd7 100644 ---- a/arch/arm64/boot/dts/qcom/sdm845.dtsi -+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi -@@ -2641,7 +2641,7 @@ - gpio-ranges = <&tlmm 0 0 151>; - wakeup-parent = <&pdc_intc>; - -- cci0_default: cci0-default { -+ cci0_default: cci0-default-state { - /* SDA, SCL */ - pins = "gpio17", "gpio18"; - function = "cci_i2c"; -@@ -2650,7 +2650,7 @@ - drive-strength = <2>; /* 2 mA */ - }; - -- cci0_sleep: cci0-sleep { -+ cci0_sleep: cci0-sleep-state { - /* SDA, SCL */ - pins = "gpio17", "gpio18"; - function = "cci_i2c"; -@@ -2659,7 +2659,7 @@ - bias-pull-down; - }; - -- cci1_default: cci1-default { -+ cci1_default: cci1-default-state { - /* SDA, SCL */ - pins = "gpio19", "gpio20"; - function = "cci_i2c"; -@@ -2668,7 +2668,7 @@ - drive-strength = <2>; /* 2 mA */ - }; - -- cci1_sleep: cci1-sleep { -+ cci1_sleep: cci1-sleep-state { - /* SDA, SCL */ - pins = "gpio19", "gpio20"; - function = "cci_i2c"; -@@ -2677,556 +2677,497 @@ - bias-pull-down; - }; - -- qspi_clk: qspi-clk { -- pinmux { -- pins = "gpio95"; -- function = "qspi_clk"; -- }; -+ qspi_clk: qspi-clk-state { -+ pins = "gpio95"; -+ function = "qspi_clk"; - }; - -- qspi_cs0: qspi-cs0 { -- pinmux { -- pins = "gpio90"; -- function = "qspi_cs"; -- }; -+ qspi_cs0: qspi-cs0-state { -+ pins = "gpio90"; -+ function = "qspi_cs"; - }; - -- qspi_cs1: qspi-cs1 { -- pinmux { -- pins = "gpio89"; -- function = "qspi_cs"; -- }; -+ qspi_cs1: qspi-cs1-state { -+ pins = "gpio89"; -+ function = "qspi_cs"; - }; - -- qspi_data01: qspi-data01 { -- pinmux-data { -- pins = "gpio91", "gpio92"; -- function = "qspi_data"; -- }; -+ qspi_data01: qspi-data01-state { -+ pins = "gpio91", "gpio92"; -+ function = "qspi_data"; - }; - -- qspi_data12: qspi-data12 { -- pinmux-data { -- pins = "gpio93", "gpio94"; -- function = "qspi_data"; -- }; -+ qspi_data12: qspi-data12-state { -+ pins = "gpio93", "gpio94"; -+ function = "qspi_data"; - }; - -- qup_i2c0_default: qup-i2c0-default { -- pinmux { -- pins = "gpio0", "gpio1"; -- function = "qup0"; -- }; -+ qup_i2c0_default: qup-i2c0-default-state { -+ pins = "gpio0", "gpio1"; -+ function = "qup0"; - }; - -- qup_i2c1_default: qup-i2c1-default { -- pinmux { -- pins = "gpio17", "gpio18"; -- function = "qup1"; -- }; -+ qup_i2c1_default: qup-i2c1-default-state { -+ pins = "gpio17", "gpio18"; -+ function = "qup1"; - }; - -- qup_i2c2_default: qup-i2c2-default { -- pinmux { -- pins = "gpio27", "gpio28"; -- function = "qup2"; -- }; -+ qup_i2c2_default: qup-i2c2-default-state { -+ pins = "gpio27", "gpio28"; -+ function = "qup2"; - }; - -- qup_i2c3_default: qup-i2c3-default { -- pinmux { -- pins = "gpio41", "gpio42"; -- function = "qup3"; -- }; -+ qup_i2c3_default: qup-i2c3-default-state { -+ pins = "gpio41", "gpio42"; -+ function = "qup3"; - }; - -- qup_i2c4_default: qup-i2c4-default { -- pinmux { -- pins = "gpio89", "gpio90"; -- function = "qup4"; -- }; -+ qup_i2c4_default: qup-i2c4-default-state { -+ pins = "gpio89", "gpio90"; -+ function = "qup4"; - }; - -- qup_i2c5_default: qup-i2c5-default { -- pinmux { -- pins = "gpio85", "gpio86"; -- function = "qup5"; -- }; -+ qup_i2c5_default: qup-i2c5-default-state { -+ pins = "gpio85", "gpio86"; -+ function = "qup5"; - }; - -- qup_i2c6_default: qup-i2c6-default { -- pinmux { -- pins = "gpio45", "gpio46"; -- function = "qup6"; -- }; -+ qup_i2c6_default: qup-i2c6-default-state { -+ pins = "gpio45", "gpio46"; -+ function = "qup6"; - }; - -- qup_i2c7_default: qup-i2c7-default { -- pinmux { -- pins = "gpio93", "gpio94"; -- function = "qup7"; -- }; -+ qup_i2c7_default: qup-i2c7-default-state { -+ pins = "gpio93", "gpio94"; -+ function = "qup7"; - }; - -- qup_i2c8_default: qup-i2c8-default { -- pinmux { -- pins = "gpio65", "gpio66"; -- function = "qup8"; -- }; -+ qup_i2c8_default: qup-i2c8-default-state { -+ pins = "gpio65", "gpio66"; -+ function = "qup8"; - }; - -- qup_i2c9_default: qup-i2c9-default { -- pinmux { -- pins = "gpio6", "gpio7"; -- function = "qup9"; -- }; -+ qup_i2c9_default: qup-i2c9-default-state { -+ pins = "gpio6", "gpio7"; -+ function = "qup9"; - }; - -- qup_i2c10_default: qup-i2c10-default { -- pinmux { -- pins = "gpio55", "gpio56"; -- function = "qup10"; -- }; -+ qup_i2c10_default: qup-i2c10-default-state { -+ pins = "gpio55", "gpio56"; -+ function = "qup10"; - }; - -- qup_i2c11_default: qup-i2c11-default { -- pinmux { -- pins = "gpio31", "gpio32"; -- function = "qup11"; -- }; -+ qup_i2c11_default: qup-i2c11-default-state { -+ pins = "gpio31", "gpio32"; -+ function = "qup11"; - }; - -- qup_i2c12_default: qup-i2c12-default { -- pinmux { -- pins = "gpio49", "gpio50"; -- function = "qup12"; -- }; -+ qup_i2c12_default: qup-i2c12-default-state { -+ pins = "gpio49", "gpio50"; -+ function = "qup12"; - }; - -- qup_i2c13_default: qup-i2c13-default { -- pinmux { -- pins = "gpio105", "gpio106"; -- function = "qup13"; -- }; -+ qup_i2c13_default: qup-i2c13-default-state { -+ pins = "gpio105", "gpio106"; -+ function = "qup13"; - }; - -- qup_i2c14_default: qup-i2c14-default { -- pinmux { -- pins = "gpio33", "gpio34"; -- function = "qup14"; -- }; -+ qup_i2c14_default: qup-i2c14-default-state { -+ pins = "gpio33", "gpio34"; -+ function = "qup14"; - }; - -- qup_i2c15_default: qup-i2c15-default { -- pinmux { -- pins = "gpio81", "gpio82"; -- function = "qup15"; -- }; -+ qup_i2c15_default: qup-i2c15-default-state { -+ pins = "gpio81", "gpio82"; -+ function = "qup15"; - }; - -- qup_spi0_default: qup-spi0-default { -- pinmux { -- pins = "gpio0", "gpio1", -- "gpio2", "gpio3"; -- function = "qup0"; -- }; -+ qup_spi0_default: qup-spi0-default-state { -+ pins = "gpio0", "gpio1", "gpio2", "gpio3"; -+ function = "qup0"; -+ drive-strength = <6>; -+ bias-disable; -+ }; - -- config { -- pins = "gpio0", "gpio1", -- "gpio2", "gpio3"; -- drive-strength = <6>; -- bias-disable; -- }; -+ qup_spi1_default: qup-spi1-default-state { -+ pins = "gpio17", "gpio18", "gpio19", "gpio20"; -+ function = "qup1"; - }; - -- qup_spi1_default: qup-spi1-default { -- pinmux { -- pins = "gpio17", "gpio18", -- "gpio19", "gpio20"; -- function = "qup1"; -- }; -+ qup_spi2_default: qup-spi2-default-state { -+ pins = "gpio27", "gpio28", "gpio29", "gpio30"; -+ function = "qup2"; - }; - -- qup_spi2_default: qup-spi2-default { -- pinmux { -- pins = "gpio27", "gpio28", -- "gpio29", "gpio30"; -- function = "qup2"; -- }; -+ qup_spi3_default: qup-spi3-default-state { -+ pins = "gpio41", "gpio42", "gpio43", "gpio44"; -+ function = "qup3"; - }; - -- qup_spi3_default: qup-spi3-default { -- pinmux { -- pins = "gpio41", "gpio42", -- "gpio43", "gpio44"; -- function = "qup3"; -- }; -+ qup_spi4_default: qup-spi4-default-state { -+ pins = "gpio89", "gpio90", "gpio91", "gpio92"; -+ function = "qup4"; - }; - -- qup_spi4_default: qup-spi4-default { -- pinmux { -- pins = "gpio89", "gpio90", -- "gpio91", "gpio92"; -- function = "qup4"; -- }; -+ qup_spi5_default: qup-spi5-default-state { -+ pins = "gpio85", "gpio86", "gpio87", "gpio88"; -+ function = "qup5"; - }; - -- qup_spi5_default: qup-spi5-default { -- pinmux { -- pins = "gpio85", "gpio86", -- "gpio87", "gpio88"; -- function = "qup5"; -- }; -+ qup_spi6_default: qup-spi6-default-state { -+ pins = "gpio45", "gpio46", "gpio47", "gpio48"; -+ function = "qup6"; - }; - -- qup_spi6_default: qup-spi6-default { -- pinmux { -- pins = "gpio45", "gpio46", -- "gpio47", "gpio48"; -- function = "qup6"; -- }; -+ qup_spi7_default: qup-spi7-default-state { -+ pins = "gpio93", "gpio94", "gpio95", "gpio96"; -+ function = "qup7"; - }; - -- qup_spi7_default: qup-spi7-default { -- pinmux { -- pins = "gpio93", "gpio94", -- "gpio95", "gpio96"; -- function = "qup7"; -- }; -+ qup_spi8_default: qup-spi8-default-state { -+ pins = "gpio65", "gpio66", "gpio67", "gpio68"; -+ function = "qup8"; - }; - -- qup_spi8_default: qup-spi8-default { -- pinmux { -- pins = "gpio65", "gpio66", -- "gpio67", "gpio68"; -- function = "qup8"; -- }; -+ qup_spi9_default: qup-spi9-default-state { -+ pins = "gpio6", "gpio7", "gpio4", "gpio5"; -+ function = "qup9"; - }; - -- qup_spi9_default: qup-spi9-default { -- pinmux { -- pins = "gpio6", "gpio7", -- "gpio4", "gpio5"; -- function = "qup9"; -- }; -+ qup_spi10_default: qup-spi10-default-state { -+ pins = "gpio55", "gpio56", "gpio53", "gpio54"; -+ function = "qup10"; - }; - -- qup_spi10_default: qup-spi10-default { -- pinmux { -- pins = "gpio55", "gpio56", -- "gpio53", "gpio54"; -- function = "qup10"; -- }; -+ qup_spi11_default: qup-spi11-default-state { -+ pins = "gpio31", "gpio32", "gpio33", "gpio34"; -+ function = "qup11"; - }; - -- qup_spi11_default: qup-spi11-default { -- pinmux { -- pins = "gpio31", "gpio32", -- "gpio33", "gpio34"; -- function = "qup11"; -- }; -+ qup_spi12_default: qup-spi12-default-state { -+ pins = "gpio49", "gpio50", "gpio51", "gpio52"; -+ function = "qup12"; - }; - -- qup_spi12_default: qup-spi12-default { -- pinmux { -- pins = "gpio49", "gpio50", -- "gpio51", "gpio52"; -- function = "qup12"; -- }; -+ qup_spi13_default: qup-spi13-default-state { -+ pins = "gpio105", "gpio106", "gpio107", "gpio108"; -+ function = "qup13"; - }; - -- qup_spi13_default: qup-spi13-default { -- pinmux { -- pins = "gpio105", "gpio106", -- "gpio107", "gpio108"; -- function = "qup13"; -- }; -+ qup_spi14_default: qup-spi14-default-state { -+ pins = "gpio33", "gpio34", "gpio31", "gpio32"; -+ function = "qup14"; - }; - -- qup_spi14_default: qup-spi14-default { -- pinmux { -- pins = "gpio33", "gpio34", -- "gpio31", "gpio32"; -- function = "qup14"; -- }; -+ qup_spi15_default: qup-spi15-default-state { -+ pins = "gpio81", "gpio82", "gpio83", "gpio84"; -+ function = "qup15"; - }; - -- qup_spi15_default: qup-spi15-default { -- pinmux { -- pins = "gpio81", "gpio82", -- "gpio83", "gpio84"; -- function = "qup15"; -+ qup_uart0_default: qup-uart0-default-state { -+ qup_uart0_tx: tx-pins { -+ pins = "gpio2"; -+ function = "qup0"; - }; -- }; - -- qup_uart0_default: qup-uart0-default { -- pinmux { -- pins = "gpio2", "gpio3"; -+ qup_uart0_rx: rx-pins { -+ pins = "gpio3"; - function = "qup0"; - }; - }; - -- qup_uart1_default: qup-uart1-default { -- pinmux { -- pins = "gpio19", "gpio20"; -+ qup_uart1_default: qup-uart1-default-state { -+ qup_uart1_tx: tx-pins { -+ pins = "gpio19"; -+ function = "qup1"; -+ }; -+ -+ qup_uart1_rx: rx-pins { -+ pins = "gpio20"; - function = "qup1"; - }; - }; - -- qup_uart2_default: qup-uart2-default { -- pinmux { -- pins = "gpio29", "gpio30"; -+ qup_uart2_default: qup-uart2-default-state { -+ qup_uart2_tx: tx-pins { -+ pins = "gpio29"; - function = "qup2"; - }; -+ -+ qup_uart2_rx: rx-pins { -+ pins = "gpio30"; -+ function = "qup2"; -+ }; -+ }; -+ -+ qup_uart3_default: qup-uart3-default-state { -+ qup_uart3_tx: tx-pins { -+ pins = "gpio43"; -+ function = "qup3"; -+ }; -+ -+ qup_uart3_rx: rx-pins { -+ pins = "gpio44"; -+ function = "qup3"; -+ }; - }; - -- qup_uart3_default: qup-uart3-default { -- pinmux { -- pins = "gpio43", "gpio44"; -+ qup_uart3_4pin: qup-uart3-4pin-state { -+ qup_uart3_4pin_cts: cts-pins { -+ pins = "gpio41"; -+ function = "qup3"; -+ }; -+ -+ qup_uart3_4pin_rts_tx: rts-tx-pins { -+ pins = "gpio42", "gpio43"; -+ function = "qup3"; -+ }; -+ -+ qup_uart3_4pin_rx: rx-pins { -+ pins = "gpio44"; - function = "qup3"; - }; - }; - -- qup_uart4_default: qup-uart4-default { -- pinmux { -- pins = "gpio91", "gpio92"; -+ qup_uart4_default: qup-uart4-default-state { -+ qup_uart4_tx: tx-pins { -+ pins = "gpio91"; -+ function = "qup4"; -+ }; -+ -+ qup_uart4_rx: rx-pins { -+ pins = "gpio92"; - function = "qup4"; - }; - }; - -- qup_uart5_default: qup-uart5-default { -- pinmux { -- pins = "gpio87", "gpio88"; -+ qup_uart5_default: qup-uart5-default-state { -+ qup_uart5_tx: tx-pins { -+ pins = "gpio87"; -+ function = "qup5"; -+ }; -+ -+ qup_uart5_rx: rx-pins { -+ pins = "gpio88"; - function = "qup5"; - }; - }; - -- qup_uart6_default: qup-uart6-default { -- pinmux { -- pins = "gpio47", "gpio48"; -+ qup_uart6_default: qup-uart6-default-state { -+ qup_uart6_tx: tx-pins { -+ pins = "gpio47"; -+ function = "qup6"; -+ }; -+ -+ qup_uart6_rx: rx-pins { -+ pins = "gpio48"; - function = "qup6"; - }; - }; - - qup_uart6_4pin: qup-uart6-4pin-state { -- -- cts-pins { -+ qup_uart6_4pin_cts: cts-pins { - pins = "gpio45"; - function = "qup6"; - bias-pull-down; - }; - -- rts-tx-pins { -+ qup_uart6_4pin_rts_tx: rts-tx-pins { - pins = "gpio46", "gpio47"; - function = "qup6"; - drive-strength = <2>; - bias-disable; - }; - -- rx-pins { -+ qup_uart6_4pin_rx: rx-pins { - pins = "gpio48"; - function = "qup6"; - bias-pull-up; - }; - }; - -- qup_uart7_default: qup-uart7-default { -- pinmux { -- pins = "gpio95", "gpio96"; -+ qup_uart7_default: qup-uart7-default-state { -+ qup_uart7_tx: tx-pins { -+ pins = "gpio95"; - function = "qup7"; - }; -- }; - -- qup_uart8_default: qup-uart8-default { -- pinmux { -- pins = "gpio67", "gpio68"; -- function = "qup8"; -- }; -- }; -- -- qup_uart9_default: qup-uart9-default { -- pinmux { -- pins = "gpio4", "gpio5"; -- function = "qup9"; -+ qup_uart7_rx: rx-pins { -+ pins = "gpio96"; -+ function = "qup7"; - }; - }; - -- qup_uart10_default: qup-uart10-default { -- pinmux { -- pins = "gpio53", "gpio54"; -- function = "qup10"; -+ qup_uart8_default: qup-uart8-default-state { -+ qup_uart8_tx: tx-pins { -+ pins = "gpio67"; -+ function = "qup8"; - }; -- }; - -- qup_uart11_default: qup-uart11-default { -- pinmux { -- pins = "gpio33", "gpio34"; -- function = "qup11"; -+ qup_uart8_rx: rx-pins { -+ pins = "gpio68"; -+ function = "qup8"; - }; - }; - -- qup_uart12_default: qup-uart12-default { -- pinmux { -- pins = "gpio51", "gpio52"; -- function = "qup12"; -+ qup_uart9_default: qup-uart9-default-state { -+ qup_uart9_tx: tx-pins { -+ pins = "gpio4"; -+ function = "qup9"; - }; -- }; - -- qup_uart13_default: qup-uart13-default { -- pinmux { -- pins = "gpio107", "gpio108"; -- function = "qup13"; -+ qup_uart9_rx: rx-pins { -+ pins = "gpio5"; -+ function = "qup9"; - }; - }; - -- qup_uart14_default: qup-uart14-default { -- pinmux { -- pins = "gpio31", "gpio32"; -- function = "qup14"; -+ qup_uart10_default: qup-uart10-default-state { -+ qup_uart10_tx: tx-pins { -+ pins = "gpio53"; -+ function = "qup10"; - }; -- }; - -- qup_uart15_default: qup-uart15-default { -- pinmux { -- pins = "gpio83", "gpio84"; -- function = "qup15"; -+ qup_uart10_rx: rx-pins { -+ pins = "gpio54"; -+ function = "qup10"; - }; - }; - -- quat_mi2s_sleep: quat_mi2s_sleep { -- mux { -- pins = "gpio58", "gpio59"; -- function = "gpio"; -+ qup_uart11_default: qup-uart11-default-state { -+ qup_uart11_tx: tx-pins { -+ pins = "gpio33"; -+ function = "qup11"; - }; - -- config { -- pins = "gpio58", "gpio59"; -- drive-strength = <2>; -- bias-pull-down; -- input-enable; -+ qup_uart11_rx: rx-pins { -+ pins = "gpio34"; -+ function = "qup11"; - }; - }; - -- quat_mi2s_active: quat_mi2s_active { -- mux { -- pins = "gpio58", "gpio59"; -- function = "qua_mi2s"; -+ qup_uart12_default: qup-uart12-default-state { -+ qup_uart12_tx: tx-pins { -+ pins = "gpio51"; -+ function = "qup0"; - }; - -- config { -- pins = "gpio58", "gpio59"; -- drive-strength = <8>; -- bias-disable; -- output-high; -+ qup_uart12_rx: rx-pins { -+ pins = "gpio52"; -+ function = "qup0"; - }; - }; - -- quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { -- mux { -- pins = "gpio60"; -- function = "gpio"; -+ qup_uart13_default: qup-uart13-default-state { -+ qup_uart13_tx: tx-pins { -+ pins = "gpio107"; -+ function = "qup13"; - }; - -- config { -- pins = "gpio60"; -- drive-strength = <2>; -- bias-pull-down; -- input-enable; -+ qup_uart13_rx: rx-pins { -+ pins = "gpio108"; -+ function = "qup13"; - }; - }; - -- quat_mi2s_sd0_active: quat_mi2s_sd0_active { -- mux { -- pins = "gpio60"; -- function = "qua_mi2s"; -+ qup_uart14_default: qup-uart14-default-state { -+ qup_uart14_tx: tx-pins { -+ pins = "gpio31"; -+ function = "qup14"; - }; - -- config { -- pins = "gpio60"; -- drive-strength = <8>; -- bias-disable; -+ qup_uart14_rx: rx-pins { -+ pins = "gpio32"; -+ function = "qup14"; - }; - }; - -- quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { -- mux { -- pins = "gpio61"; -- function = "gpio"; -+ qup_uart15_default: qup-uart15-default-state { -+ qup_uart15_tx: tx-pins { -+ pins = "gpio83"; -+ function = "qup15"; - }; - -- config { -- pins = "gpio61"; -- drive-strength = <2>; -- bias-pull-down; -- input-enable; -+ qup_uart15_rx: rx-pins { -+ pins = "gpio84"; -+ function = "qup15"; - }; - }; - -- quat_mi2s_sd1_active: quat_mi2s_sd1_active { -- mux { -- pins = "gpio61"; -- function = "qua_mi2s"; -- }; -+ quat_mi2s_sleep: quat-mi2s-sleep-state { -+ pins = "gpio58", "gpio59"; -+ function = "gpio"; -+ drive-strength = <2>; -+ bias-pull-down; -+ input-enable; -+ }; - -- config { -- pins = "gpio61"; -- drive-strength = <8>; -- bias-disable; -- }; -+ quat_mi2s_active: quat-mi2s-active-state { -+ pins = "gpio58", "gpio59"; -+ function = "qua_mi2s"; -+ drive-strength = <8>; -+ bias-disable; -+ output-high; - }; - -- quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { -- mux { -- pins = "gpio62"; -- function = "gpio"; -- }; -+ quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state { -+ pins = "gpio60"; -+ function = "gpio"; -+ drive-strength = <2>; -+ bias-pull-down; -+ input-enable; -+ }; - -- config { -- pins = "gpio62"; -- drive-strength = <2>; -- bias-pull-down; -- input-enable; -- }; -+ quat_mi2s_sd0_active: quat-mi2s-sd0-active-state { -+ pins = "gpio60"; -+ function = "qua_mi2s"; -+ drive-strength = <8>; -+ bias-disable; - }; - -- quat_mi2s_sd2_active: quat_mi2s_sd2_active { -- mux { -- pins = "gpio62"; -- function = "qua_mi2s"; -- }; -+ quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state { -+ pins = "gpio61"; -+ function = "gpio"; -+ drive-strength = <2>; -+ bias-pull-down; -+ input-enable; -+ }; - -- config { -- pins = "gpio62"; -- drive-strength = <8>; -- bias-disable; -- }; -+ quat_mi2s_sd1_active: quat-mi2s-sd1-active-state { -+ pins = "gpio61"; -+ function = "qua_mi2s"; -+ drive-strength = <8>; -+ bias-disable; - }; - -- quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { -- mux { -- pins = "gpio63"; -- function = "gpio"; -- }; -+ quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state { -+ pins = "gpio62"; -+ function = "gpio"; -+ drive-strength = <2>; -+ bias-pull-down; -+ input-enable; -+ }; - -- config { -- pins = "gpio63"; -- drive-strength = <2>; -- bias-pull-down; -- input-enable; -- }; -+ quat_mi2s_sd2_active: quat-mi2s-sd2-active-state { -+ pins = "gpio62"; -+ function = "qua_mi2s"; -+ drive-strength = <8>; -+ bias-disable; - }; - -- quat_mi2s_sd3_active: quat_mi2s_sd3_active { -- mux { -- pins = "gpio63"; -- function = "qua_mi2s"; -- }; -+ quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state { -+ pins = "gpio63"; -+ function = "gpio"; -+ drive-strength = <2>; -+ bias-pull-down; -+ input-enable; -+ }; - -- config { -- pins = "gpio63"; -- drive-strength = <8>; -- bias-disable; -- }; -+ quat_mi2s_sd3_active: quat-mi2s-sd3-active-state { -+ pins = "gpio63"; -+ function = "qua_mi2s"; -+ drive-strength = <8>; -+ bias-disable; - }; - }; - -diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts -index f32b7445f7c96..83e4a92430fb7 100644 ---- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts -+++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts -@@ -479,41 +479,13 @@ - }; - - &qup_i2c10_default { -- pinconf { -- pins = "gpio55", "gpio56"; -- drive-strength = <2>; -- bias-disable; -- }; -+ drive-strength = <2>; -+ bias-disable; - }; - - &qup_i2c12_default { -- pinmux { -- drive-strength = <2>; -- bias-disable; -- }; --}; -- --&qup_uart6_default { -- pinmux { -- pins = "gpio45", "gpio46", "gpio47", "gpio48"; -- function = "qup6"; -- }; -- -- cts { -- pins = "gpio45"; -- bias-pull-down; -- }; -- -- rts-tx { -- pins = "gpio46", "gpio47"; -- drive-strength = <2>; -- bias-disable; -- }; -- -- rx { -- pins = "gpio48"; -- bias-pull-up; -- }; -+ drive-strength = <2>; -+ bias-disable; - }; - - &qupv3_id_0 { -@@ -621,13 +593,14 @@ - &tlmm { - gpio-reserved-ranges = <0 4>, <81 4>; - -- sn65dsi86_pin_active: sn65dsi86-enable { -+ sn65dsi86_pin_active: sn65dsi86-enable-state { - pins = "gpio96"; -+ function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - -- i2c3_hid_active: i2c2-hid-active { -+ i2c3_hid_active: i2c2-hid-active-state { - pins = "gpio37"; - function = "gpio"; - -@@ -636,7 +609,7 @@ - drive-strength = <2>; - }; - -- i2c5_hid_active: i2c5-hid-active { -+ i2c5_hid_active: i2c5-hid-active-state { - pins = "gpio125"; - function = "gpio"; - -@@ -645,7 +618,7 @@ - drive-strength = <2>; - }; - -- i2c11_hid_active: i2c11-hid-active { -+ i2c11_hid_active: i2c11-hid-active-state { - pins = "gpio92"; - function = "gpio"; - -@@ -654,7 +627,7 @@ - drive-strength = <2>; - }; - -- wcd_intr_default: wcd_intr_default { -+ wcd_intr_default: wcd-intr-default-state { - pins = "gpio54"; - function = "gpio"; - -@@ -663,7 +636,7 @@ - drive-strength = <2>; - }; - -- lid_pin_active: lid-pin { -+ lid_pin_active: lid-pin-state { - pins = "gpio124"; - function = "gpio"; - -@@ -671,7 +644,7 @@ - bias-disable; - }; - -- mode_pin_active: mode-pin { -+ mode_pin_active: mode-pin-state { - pins = "gpio95"; - function = "gpio"; - -@@ -681,6 +654,8 @@ - }; - - &uart6 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&qup_uart6_4pin>; - status = "okay"; - - bluetooth { -diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts -index daca1e0ad62ad..9215066146ffe 100644 ---- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts -+++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts -@@ -399,49 +399,18 @@ - }; - - &qup_i2c10_default { -- pinconf { -- pins = "gpio55", "gpio56"; -- drive-strength = <2>; -- bias-disable; -- }; -+ drive-strength = <2>; -+ bias-disable; - }; - - &qup_i2c11_default { -- pinconf { -- pins = "gpio31", "gpio32"; -- drive-strength = <2>; -- bias-disable; -- }; -+ drive-strength = <2>; -+ bias-disable; - }; - - &qup_i2c12_default { -- pinmux { -- drive-strength = <2>; -- bias-disable; -- }; --}; -- --&qup_uart6_default { -- pinmux { -- pins = "gpio45", "gpio46", "gpio47", "gpio48"; -- function = "qup6"; -- }; -- -- cts { -- pins = "gpio45"; -- bias-pull-down; -- }; -- -- rts-tx { -- pins = "gpio46", "gpio47"; -- drive-strength = <2>; -- bias-disable; -- }; -- -- rx { -- pins = "gpio48"; -- bias-pull-up; -- }; -+ drive-strength = <2>; -+ bias-disable; - }; - - &qupv3_id_0 { -@@ -549,59 +518,41 @@ - &tlmm { - gpio-reserved-ranges = <0 6>, <85 4>; - -- pen_irq_l: pen-irq-l { -- pinmux { -- pins = "gpio119"; -- function = "gpio"; -- }; -- -- pinconf { -- pins = "gpio119"; -- bias-disable; -- }; -+ pen_irq_l: pen-irq-l-state { -+ pins = "gpio119"; -+ function = "gpio"; -+ bias-disable; - }; - -- pen_pdct_l: pen-pdct-l { -- pinmux { -- pins = "gpio124"; -- function = "gpio"; -- }; -- -- pinconf { -- pins = "gpio124"; -- bias-disable; -- drive-strength = <2>; -- output-high; -- }; -+ pen_pdct_l: pen-pdct-l-state { -+ pins = "gpio124"; -+ function = "gpio"; -+ bias-disable; -+ drive-strength = <2>; -+ output-high; - }; - -- pen_rst_l: pen-rst-l { -- pinmux { -- pins = "gpio21"; -- function = "gpio"; -- }; -- -- pinconf { -- pins = "gpio21"; -- bias-disable; -- drive-strength = <2>; -- -- /* -- * The pen driver doesn't currently support -- * driving this reset line. By specifying -- * output-high here we're relying on the fact -- * that this pin has a default pulldown at boot -- * (which makes sure the pen was in reset if it -- * was powered) and then we set it high here to -- * take it out of reset. Better would be if the -- * pen driver could control this and we could -- * remove "output-high" here. -- */ -- output-high; -- }; -+ pen_rst_l: pen-rst-l-state { -+ pins = "gpio21"; -+ function = "gpio"; -+ bias-disable; -+ drive-strength = <2>; -+ -+ /* -+ * The pen driver doesn't currently support -+ * driving this reset line. By specifying -+ * output-high here we're relying on the fact -+ * that this pin has a default pulldown at boot -+ * (which makes sure the pen was in reset if it -+ * was powered) and then we set it high here to -+ * take it out of reset. Better would be if the -+ * pen driver could control this and we could -+ * remove "output-high" here. -+ */ -+ output-high; - }; - -- wcd_intr_default: wcd_intr_default { -+ wcd_intr_default: wcd-intr-default-state { - pins = "gpio54"; - function = "gpio"; - -@@ -612,6 +563,8 @@ - }; - - &uart6 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&qup_uart6_4pin>; - status = "okay"; - - bluetooth { --- -2.39.2 - diff --git a/queue-6.2/arm64-dts-sdm845-rename-qspi-data12-as-data23.patch b/queue-6.2/arm64-dts-sdm845-rename-qspi-data12-as-data23.patch index fecbcf3d4ae..a07cf220809 100644 --- a/queue-6.2/arm64-dts-sdm845-rename-qspi-data12-as-data23.patch +++ b/queue-6.2/arm64-dts-sdm845-rename-qspi-data12-as-data23.patch @@ -19,22 +19,17 @@ Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230323102605.3.I88528d037b7fda4e53a40f661be5ac61628691cd@changeid Signed-off-by: Sasha Levin --- - arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- + arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi -index 481b721881cd7..81ec17e7d7310 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi -@@ -2697,7 +2697,7 @@ - function = "qspi_data"; +@@ -2705,7 +2705,7 @@ + }; }; -- qspi_data12: qspi-data12-state { -+ qspi_data23: qspi-data23-state { - pins = "gpio93", "gpio94"; - function = "qspi_data"; - }; --- -2.39.2 - +- qspi_data12: qspi-data12 { ++ qspi_data23: qspi-data23 { + pinmux-data { + pins = "gpio93", "gpio94"; + function = "qspi_data"; diff --git a/queue-6.2/series b/queue-6.2/series index 9eecf8be15e..d5dc255065a 100644 --- a/queue-6.2/series +++ b/queue-6.2/series @@ -161,10 +161,6 @@ arm64-dts-qcom-sdm845-fix-the-pci-i-o-port-range.patch arm64-dts-qcom-msm8998-fix-the-pci-i-o-port-range.patch arm64-dts-qcom-sc7280-fix-the-pci-i-o-port-range.patch arm64-dts-qcom-ipq8074-fix-the-pci-i-o-port-range.patch -arm64-dts-qcom-ipq6018-use-lowercase-hex.patch -arm64-dts-qcom-ipq6018-pad-addresses-to-8-hex-digits.patch -arm64-dts-qcom-ipq6018-fix-up-indentation.patch -arm64-dts-qcom-ipq6018-sort-nodes-properly.patch arm64-dts-qcom-ipq6018-add-remove-some-newlines.patch arm64-dts-qcom-ipq6018-fix-the-pci-i-o-port-range.patch arm64-dts-qcom-msm8996-fix-the-pci-i-o-port-range.patch @@ -232,7 +228,6 @@ arm64-dts-qcom-msm8994-angler-fix-cont_splash_mem-ma.patch arm64-dts-qcom-msm8994-angler-removed-clash-with-sme.patch arm64-dts-sc7180-rename-qspi-data12-as-data23.patch arm64-dts-sc7280-rename-qspi-data12-as-data23.patch -arm64-dts-qcom-sdm845-align-tlmm-pin-configuration-w.patch arm64-dts-sdm845-rename-qspi-data12-as-data23.patch media-mtk-jpeg-fixes-jpeghw-multi-core-judgement.patch media-mtk-jpeg-fixes-jpeg-enc-dec-worker-sw-flow.patch