From: Greg Kroah-Hartman Date: Fri, 5 Dec 2014 00:14:31 +0000 (-0800) Subject: 3.17-stable patches X-Git-Tag: v3.10.62~8 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=bbb022f1c4715f23c464ea3185876c51a806b3b5;p=thirdparty%2Fkernel%2Fstable-queue.git 3.17-stable patches added patches: bitops-fix-shift-overflow-in-genmask-macros.patch --- diff --git a/queue-3.17/bitops-fix-shift-overflow-in-genmask-macros.patch b/queue-3.17/bitops-fix-shift-overflow-in-genmask-macros.patch new file mode 100644 index 00000000000..5129c6f0aa4 --- /dev/null +++ b/queue-3.17/bitops-fix-shift-overflow-in-genmask-macros.patch @@ -0,0 +1,52 @@ +From 00b4d9a14125f1e51874def2b9de6092e007412d Mon Sep 17 00:00:00 2001 +From: Maxime COQUELIN +Date: Thu, 6 Nov 2014 10:54:19 +0100 +Subject: bitops: Fix shift overflow in GENMASK macros + +From: Maxime COQUELIN + +commit 00b4d9a14125f1e51874def2b9de6092e007412d upstream. + +On some 32 bits architectures, including x86, GENMASK(31, 0) returns 0 +instead of the expected ~0UL. + +This is the same on some 64 bits architectures with GENMASK_ULL(63, 0). + +This is due to an overflow in the shift operand, 1 << 32 for GENMASK, +1 << 64 for GENMASK_ULL. + +Reported-by: Eric Paire +Suggested-by: Rasmus Villemoes +Signed-off-by: Maxime Coquelin +Signed-off-by: Peter Zijlstra (Intel) +Cc: linux@rasmusvillemoes.dk +Cc: gong.chen@linux.intel.com +Cc: John Sullivan +Cc: Linus Torvalds +Cc: Paul E. McKenney +Cc: Theodore Ts'o +Fixes: 10ef6b0dffe4 ("bitops: Introduce a more generic BITMASK macro") +Link: http://lkml.kernel.org/r/1415267659-10563-1-git-send-email-maxime.coquelin@st.com +Signed-off-by: Ingo Molnar +Signed-off-by: Greg Kroah-Hartman + +--- + include/linux/bitops.h | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +--- a/include/linux/bitops.h ++++ b/include/linux/bitops.h +@@ -18,8 +18,11 @@ + * position @h. For example + * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000. + */ +-#define GENMASK(h, l) (((U32_C(1) << ((h) - (l) + 1)) - 1) << (l)) +-#define GENMASK_ULL(h, l) (((U64_C(1) << ((h) - (l) + 1)) - 1) << (l)) ++#define GENMASK(h, l) \ ++ (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) ++ ++#define GENMASK_ULL(h, l) \ ++ (((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) + + extern unsigned int __sw_hweight8(unsigned int w); + extern unsigned int __sw_hweight16(unsigned int w); diff --git a/queue-3.17/series b/queue-3.17/series index 821fa3667d2..6627039f17f 100644 --- a/queue-3.17/series +++ b/queue-3.17/series @@ -112,3 +112,4 @@ drm-i915-ignore-surflive-and-flip-counter-when-the-gpu-gets-reset.patch drm-radeon-report-disconnected-for-lvds-edp-with-px-if-ddc-fails.patch gpu-radeon-set-flag-to-indicate-broken-64-bit-msi.patch drm-radeon-initialize-sadb-to-null-in-the-audio-code.patch +bitops-fix-shift-overflow-in-genmask-macros.patch