From: Greg Kroah-Hartman Date: Sun, 3 Apr 2022 13:40:43 +0000 (+0200) Subject: 5.10-stable patches X-Git-Tag: v5.17.2~111 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=bbf12928a76122ec4fa09b2674e9457af6f40d23;p=thirdparty%2Fkernel%2Fstable-queue.git 5.10-stable patches added patches: arm-iop32x-offset-irq-numbers-by-1.patch asoc-mediatek-mt6358-add-missing-export_symbols.patch pinctrl-nuvoton-npcm7xx-rename-ds-macro-to-dstr.patch pinctrl-nuvoton-npcm7xx-use-zu-printk-format-for-array_size.patch ubi-fix-race-condition-between-ctrl_cdev_ioctl-and-ubi_cdev_ioctl.patch watchdog-rti-wdt-add-missing-pm_runtime_disable-in-probe-function.patch --- diff --git a/queue-5.10/arm-iop32x-offset-irq-numbers-by-1.patch b/queue-5.10/arm-iop32x-offset-irq-numbers-by-1.patch new file mode 100644 index 00000000000..d85570a895a --- /dev/null +++ b/queue-5.10/arm-iop32x-offset-irq-numbers-by-1.patch @@ -0,0 +1,152 @@ +From 9d67412f24cc3a2c05f35f7c856addb07a2960ce Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Tue, 30 Nov 2021 11:16:41 +0100 +Subject: ARM: iop32x: offset IRQ numbers by 1 + +From: Arnd Bergmann + +commit 9d67412f24cc3a2c05f35f7c856addb07a2960ce upstream. + +iop32x is one of the last platforms to use IRQ 0, and this has apparently +stopped working in a 2014 cleanup without anyone noticing. This interrupt +is used for the DMA engine, so most likely this has not actually worked +in the past 7 years, but it's also not essential for using this board. + +I'm splitting out this change from my GENERIC_IRQ_MULTI_HANDLER +conversion so it can be backported if anyone cares. + +Fixes: a71b092a9c68 ("ARM: Convert handle_IRQ to use __handle_domain_irq") +Signed-off-by: Arnd Bergmann +[ardb: take +1 offset into account in mask/unmask and init as well] +Signed-off-by: Ard Biesheuvel +Tested-by: Marc Zyngier +Tested-by: Vladimir Murzin # ARMv7M +Reviewed-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm/mach-iop32x/include/mach/entry-macro.S | 2 + arch/arm/mach-iop32x/include/mach/irqs.h | 2 + arch/arm/mach-iop32x/irq.c | 6 +- + arch/arm/mach-iop32x/irqs.h | 60 ++++++++++++------------ + 4 files changed, 37 insertions(+), 33 deletions(-) + +--- a/arch/arm/mach-iop32x/include/mach/entry-macro.S ++++ b/arch/arm/mach-iop32x/include/mach/entry-macro.S +@@ -20,7 +20,7 @@ + mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC + cmp \irqstat, #0 + clzne \irqnr, \irqstat +- rsbne \irqnr, \irqnr, #31 ++ rsbne \irqnr, \irqnr, #32 + .endm + + .macro arch_ret_to_user, tmp1, tmp2 +--- a/arch/arm/mach-iop32x/include/mach/irqs.h ++++ b/arch/arm/mach-iop32x/include/mach/irqs.h +@@ -9,6 +9,6 @@ + #ifndef __IRQS_H + #define __IRQS_H + +-#define NR_IRQS 32 ++#define NR_IRQS 33 + + #endif +--- a/arch/arm/mach-iop32x/irq.c ++++ b/arch/arm/mach-iop32x/irq.c +@@ -32,14 +32,14 @@ static void intstr_write(u32 val) + static void + iop32x_irq_mask(struct irq_data *d) + { +- iop32x_mask &= ~(1 << d->irq); ++ iop32x_mask &= ~(1 << (d->irq - 1)); + intctl_write(iop32x_mask); + } + + static void + iop32x_irq_unmask(struct irq_data *d) + { +- iop32x_mask |= 1 << d->irq; ++ iop32x_mask |= 1 << (d->irq - 1); + intctl_write(iop32x_mask); + } + +@@ -65,7 +65,7 @@ void __init iop32x_init_irq(void) + machine_is_em7210()) + *IOP3XX_PCIIRSR = 0x0f; + +- for (i = 0; i < NR_IRQS; i++) { ++ for (i = 1; i < NR_IRQS; i++) { + irq_set_chip_and_handler(i, &ext_chip, handle_level_irq); + irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE); + } +--- a/arch/arm/mach-iop32x/irqs.h ++++ b/arch/arm/mach-iop32x/irqs.h +@@ -7,36 +7,40 @@ + #ifndef __IOP32X_IRQS_H + #define __IOP32X_IRQS_H + ++/* Interrupts in Linux start at 1, hardware starts at 0 */ ++ ++#define IOP_IRQ(x) ((x) + 1) ++ + /* + * IOP80321 chipset interrupts + */ +-#define IRQ_IOP32X_DMA0_EOT 0 +-#define IRQ_IOP32X_DMA0_EOC 1 +-#define IRQ_IOP32X_DMA1_EOT 2 +-#define IRQ_IOP32X_DMA1_EOC 3 +-#define IRQ_IOP32X_AA_EOT 6 +-#define IRQ_IOP32X_AA_EOC 7 +-#define IRQ_IOP32X_CORE_PMON 8 +-#define IRQ_IOP32X_TIMER0 9 +-#define IRQ_IOP32X_TIMER1 10 +-#define IRQ_IOP32X_I2C_0 11 +-#define IRQ_IOP32X_I2C_1 12 +-#define IRQ_IOP32X_MESSAGING 13 +-#define IRQ_IOP32X_ATU_BIST 14 +-#define IRQ_IOP32X_PERFMON 15 +-#define IRQ_IOP32X_CORE_PMU 16 +-#define IRQ_IOP32X_BIU_ERR 17 +-#define IRQ_IOP32X_ATU_ERR 18 +-#define IRQ_IOP32X_MCU_ERR 19 +-#define IRQ_IOP32X_DMA0_ERR 20 +-#define IRQ_IOP32X_DMA1_ERR 21 +-#define IRQ_IOP32X_AA_ERR 23 +-#define IRQ_IOP32X_MSG_ERR 24 +-#define IRQ_IOP32X_SSP 25 +-#define IRQ_IOP32X_XINT0 27 +-#define IRQ_IOP32X_XINT1 28 +-#define IRQ_IOP32X_XINT2 29 +-#define IRQ_IOP32X_XINT3 30 +-#define IRQ_IOP32X_HPI 31 ++#define IRQ_IOP32X_DMA0_EOT IOP_IRQ(0) ++#define IRQ_IOP32X_DMA0_EOC IOP_IRQ(1) ++#define IRQ_IOP32X_DMA1_EOT IOP_IRQ(2) ++#define IRQ_IOP32X_DMA1_EOC IOP_IRQ(3) ++#define IRQ_IOP32X_AA_EOT IOP_IRQ(6) ++#define IRQ_IOP32X_AA_EOC IOP_IRQ(7) ++#define IRQ_IOP32X_CORE_PMON IOP_IRQ(8) ++#define IRQ_IOP32X_TIMER0 IOP_IRQ(9) ++#define IRQ_IOP32X_TIMER1 IOP_IRQ(10) ++#define IRQ_IOP32X_I2C_0 IOP_IRQ(11) ++#define IRQ_IOP32X_I2C_1 IOP_IRQ(12) ++#define IRQ_IOP32X_MESSAGING IOP_IRQ(13) ++#define IRQ_IOP32X_ATU_BIST IOP_IRQ(14) ++#define IRQ_IOP32X_PERFMON IOP_IRQ(15) ++#define IRQ_IOP32X_CORE_PMU IOP_IRQ(16) ++#define IRQ_IOP32X_BIU_ERR IOP_IRQ(17) ++#define IRQ_IOP32X_ATU_ERR IOP_IRQ(18) ++#define IRQ_IOP32X_MCU_ERR IOP_IRQ(19) ++#define IRQ_IOP32X_DMA0_ERR IOP_IRQ(20) ++#define IRQ_IOP32X_DMA1_ERR IOP_IRQ(21) ++#define IRQ_IOP32X_AA_ERR IOP_IRQ(23) ++#define IRQ_IOP32X_MSG_ERR IOP_IRQ(24) ++#define IRQ_IOP32X_SSP IOP_IRQ(25) ++#define IRQ_IOP32X_XINT0 IOP_IRQ(27) ++#define IRQ_IOP32X_XINT1 IOP_IRQ(28) ++#define IRQ_IOP32X_XINT2 IOP_IRQ(29) ++#define IRQ_IOP32X_XINT3 IOP_IRQ(30) ++#define IRQ_IOP32X_HPI IOP_IRQ(31) + + #endif diff --git a/queue-5.10/asoc-mediatek-mt6358-add-missing-export_symbols.patch b/queue-5.10/asoc-mediatek-mt6358-add-missing-export_symbols.patch new file mode 100644 index 00000000000..8724c2d929e --- /dev/null +++ b/queue-5.10/asoc-mediatek-mt6358-add-missing-export_symbols.patch @@ -0,0 +1,60 @@ +From a7663c89f4193dbf717572e46e5a3251940dbdc8 Mon Sep 17 00:00:00 2001 +From: Jiaxin Yu +Date: Sat, 19 Mar 2022 20:03:25 +0800 +Subject: ASoC: mediatek: mt6358: add missing EXPORT_SYMBOLs + +From: Jiaxin Yu + +commit a7663c89f4193dbf717572e46e5a3251940dbdc8 upstream. + +Fixes the following build errors when mt6358 is configured as module: + +>> ERROR: modpost: "mt6358_set_mtkaif_protocol" +>> [sound/soc/mediatek/mt8186/mt8186-mt6366-rt1019-rt5682s.ko] undefined! +>> ERROR: modpost: "mt6358_set_mtkaif_protocol" +>> [sound/soc/mediatek/mt8186/mt8186-mt6366-da7219-max98357.ko] undefined! + +Fixes: 6a8d4198ca80 ("ASoC: mediatek: mt6358: add codec driver") +Signed-off-by: Jiaxin Yu +Reviewed-by: AngeloGioacchino Del Regno +Link: https://lore.kernel.org/r/20220319120325.11882-1-jiaxin.yu@mediatek.com +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman +--- + sound/soc/codecs/mt6358.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/sound/soc/codecs/mt6358.c ++++ b/sound/soc/codecs/mt6358.c +@@ -107,6 +107,7 @@ int mt6358_set_mtkaif_protocol(struct sn + priv->mtkaif_protocol = mtkaif_protocol; + return 0; + } ++EXPORT_SYMBOL_GPL(mt6358_set_mtkaif_protocol); + + static void playback_gpio_set(struct mt6358_priv *priv) + { +@@ -273,6 +274,7 @@ int mt6358_mtkaif_calibration_enable(str + 1 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT); + return 0; + } ++EXPORT_SYMBOL_GPL(mt6358_mtkaif_calibration_enable); + + int mt6358_mtkaif_calibration_disable(struct snd_soc_component *cmpnt) + { +@@ -296,6 +298,7 @@ int mt6358_mtkaif_calibration_disable(st + capture_gpio_reset(priv); + return 0; + } ++EXPORT_SYMBOL_GPL(mt6358_mtkaif_calibration_disable); + + int mt6358_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt, + int phase_1, int phase_2) +@@ -310,6 +313,7 @@ int mt6358_set_mtkaif_calibration_phase( + phase_2 << RG_AUD_PAD_TOP_PHASE_MODE2_SFT); + return 0; + } ++EXPORT_SYMBOL_GPL(mt6358_set_mtkaif_calibration_phase); + + /* dl pga gain */ + enum { diff --git a/queue-5.10/pinctrl-nuvoton-npcm7xx-rename-ds-macro-to-dstr.patch b/queue-5.10/pinctrl-nuvoton-npcm7xx-rename-ds-macro-to-dstr.patch new file mode 100644 index 00000000000..d35fc2ae3bb --- /dev/null +++ b/queue-5.10/pinctrl-nuvoton-npcm7xx-rename-ds-macro-to-dstr.patch @@ -0,0 +1,283 @@ +From 603501c16431c56f74eaef1ee1390f60a30c2187 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= +Date: Sat, 5 Feb 2022 16:53:31 +0100 +Subject: pinctrl: nuvoton: npcm7xx: Rename DS() macro to DSTR() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Jonathan Neuschäfer + +commit 603501c16431c56f74eaef1ee1390f60a30c2187 upstream. + +The name "DS" is defined in arch/x86/um/shared/sysdep/ptrace_64.h, +which results in a compiler warning when build-testing on ARCH=um. +Rename this driver's "DS" macro to DSTR so avoid this collision. + +Reported-by: kernel test robot +Fixes: 3b588e43ee5c7 ("pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver") +Signed-off-by: Jonathan Neuschäfer +Reviewed-by: Andy Shevchenko +Link: https://lore.kernel.org/r/20220205155332.1308899-3-j.neuschaefer@gmx.net +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 156 +++++++++++++++--------------- + 1 file changed, 78 insertions(+), 78 deletions(-) + +--- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ++++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +@@ -904,7 +904,7 @@ static struct npcm7xx_func npcm7xx_funcs + #define DRIVE_STRENGTH_HI_SHIFT 12 + #define DRIVE_STRENGTH_MASK 0x0000FF00 + +-#define DS(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \ ++#define DSTR(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \ + ((hi) << DRIVE_STRENGTH_HI_SHIFT)) + #define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & 0xF) + #define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & 0xF) +@@ -924,31 +924,31 @@ struct npcm7xx_pincfg { + static const struct npcm7xx_pincfg pincfg[] = { + /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FLAGS */ + NPCM7XX_PINCFG(0, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0), +- NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DS(8, 12)), +- NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DS(8, 12)), ++ NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), ++ NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(3, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(4, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(5, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(6, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(7, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW), +- NPCM7XX_PINCFG(8, lkgpo1, FLOCKR1, 4, none, NONE, 0, none, NONE, 0, DS(8, 12)), +- NPCM7XX_PINCFG(9, lkgpo2, FLOCKR1, 8, none, NONE, 0, none, NONE, 0, DS(8, 12)), +- NPCM7XX_PINCFG(10, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)), +- NPCM7XX_PINCFG(11, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)), ++ NPCM7XX_PINCFG(8, lkgpo1, FLOCKR1, 4, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), ++ NPCM7XX_PINCFG(9, lkgpo2, FLOCKR1, 8, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), ++ NPCM7XX_PINCFG(10, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), ++ NPCM7XX_PINCFG(11, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(12, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(13, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW), +- NPCM7XX_PINCFG(16, lkgpo0, FLOCKR1, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), +- NPCM7XX_PINCFG(17, pspi2, MFSEL3, 13, smb4den, I2CSEGSEL, 23, none, NONE, 0, DS(8, 12)), +- NPCM7XX_PINCFG(18, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DS(8, 12)), +- NPCM7XX_PINCFG(19, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DS(8, 12)), ++ NPCM7XX_PINCFG(16, lkgpo0, FLOCKR1, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), ++ NPCM7XX_PINCFG(17, pspi2, MFSEL3, 13, smb4den, I2CSEGSEL, 23, none, NONE, 0, DSTR(8, 12)), ++ NPCM7XX_PINCFG(18, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)), ++ NPCM7XX_PINCFG(19, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(20, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0), + NPCM7XX_PINCFG(21, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0), + NPCM7XX_PINCFG(22, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0), + NPCM7XX_PINCFG(23, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0), +- NPCM7XX_PINCFG(24, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)), +- NPCM7XX_PINCFG(25, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)), ++ NPCM7XX_PINCFG(24, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), ++ NPCM7XX_PINCFG(25, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0), +@@ -964,12 +964,12 @@ static const struct npcm7xx_pincfg pincf + NPCM7XX_PINCFG(39, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(40, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(41, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, 0), +- NPCM7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DS(2, 4) | GPO), ++ NPCM7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DSTR(2, 4) | GPO), + NPCM7XX_PINCFG(43, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0), + NPCM7XX_PINCFG(44, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0), + NPCM7XX_PINCFG(45, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, 0), +- NPCM7XX_PINCFG(46, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DS(2, 8)), +- NPCM7XX_PINCFG(47, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DS(2, 8)), ++ NPCM7XX_PINCFG(46, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)), ++ NPCM7XX_PINCFG(47, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)), + NPCM7XX_PINCFG(48, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, GPO), + NPCM7XX_PINCFG(49, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, 0), + NPCM7XX_PINCFG(50, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), +@@ -979,8 +979,8 @@ static const struct npcm7xx_pincfg pincf + NPCM7XX_PINCFG(54, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(55, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0, none, NONE, 0, 0), +- NPCM7XX_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DS(2, 4)), +- NPCM7XX_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DS(2, 4)), ++ NPCM7XX_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), ++ NPCM7XX_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), + NPCM7XX_PINCFG(59, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(60, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(61, uart1, MFSEL1, 10, none, NONE, 0, none, NONE, 0, GPO), +@@ -1003,19 +1003,19 @@ static const struct npcm7xx_pincfg pincf + NPCM7XX_PINCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, 0), +- NPCM7XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, DS(4, 8)), +- NPCM7XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, DS(4, 8)), +- NPCM7XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, DS(4, 8)), +- NPCM7XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, DS(4, 8)), +- NPCM7XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), ++ NPCM7XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), ++ NPCM7XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), ++ NPCM7XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), ++ NPCM7XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), ++ NPCM7XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0, none, NONE, 0, 0), +- NPCM7XX_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DS(2, 4)), +- NPCM7XX_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DS(2, 4)), ++ NPCM7XX_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), ++ NPCM7XX_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), + NPCM7XX_PINCFG(93, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0), + NPCM7XX_PINCFG(94, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0), + NPCM7XX_PINCFG(95, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0), +@@ -1061,34 +1061,34 @@ static const struct npcm7xx_pincfg pincf + NPCM7XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(134, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(135, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0), +- NPCM7XX_PINCFG(136, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(137, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(138, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(139, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(140, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), ++ NPCM7XX_PINCFG(136, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(137, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(138, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(139, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(140, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(141, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, 0), +- NPCM7XX_PINCFG(142, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), ++ NPCM7XX_PINCFG(142, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(143, sd1, MFSEL3, 12, sd1pwr, MFSEL4, 5, none, NONE, 0, 0), +- NPCM7XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, DS(4, 8)), +- NPCM7XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, DS(4, 8)), +- NPCM7XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, DS(4, 8)), +- NPCM7XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, DS(4, 8)), +- NPCM7XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), ++ NPCM7XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), ++ NPCM7XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), ++ NPCM7XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), ++ NPCM7XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), ++ NPCM7XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(153, mmcwp, FLOCKR1, 24, none, NONE, 0, none, NONE, 0, 0), /* Z1/A1 */ +- NPCM7XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), ++ NPCM7XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(155, mmccd, MFSEL3, 25, mmcrst, MFSEL4, 6, none, NONE, 0, 0), /* Z1/A1 */ +- NPCM7XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), +- +- NPCM7XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DS(8, 12)), +- NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DS(8, 12)), ++ NPCM7XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), ++ ++ NPCM7XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DSTR(8, 12)), ++ NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(163, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0), + NPCM7XX_PINCFG(164, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC), + NPCM7XX_PINCFG(165, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC), +@@ -1101,25 +1101,25 @@ static const struct npcm7xx_pincfg pincf + NPCM7XX_PINCFG(172, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(173, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(174, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0), +- NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)), +- NPCM7XX_PINCFG(176, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)), +- NPCM7XX_PINCFG(177, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)), +- NPCM7XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), ++ NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)), ++ NPCM7XX_PINCFG(176, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)), ++ NPCM7XX_PINCFG(177, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)), ++ NPCM7XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), +- NPCM7XX_PINCFG(183, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO), +- NPCM7XX_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO), +- NPCM7XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12)), +- NPCM7XX_PINCFG(187, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, DS(8, 12)), +- NPCM7XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DS(2, 4)), +- NPCM7XX_PINCFG(191, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), /* XX */ ++ NPCM7XX_PINCFG(183, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), ++ NPCM7XX_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), ++ NPCM7XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), ++ NPCM7XX_PINCFG(187, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), ++ NPCM7XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DSTR(2, 4)), ++ NPCM7XX_PINCFG(191, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */ + +- NPCM7XX_PINCFG(192, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), /* XX */ ++ NPCM7XX_PINCFG(192, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */ + NPCM7XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(194, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(195, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0), +@@ -1130,11 +1130,11 @@ static const struct npcm7xx_pincfg pincf + NPCM7XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(202, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0), +- NPCM7XX_PINCFG(203, faninx, MFSEL3, 3, none, NONE, 0, none, NONE, 0, DS(8, 12)), ++ NPCM7XX_PINCFG(203, faninx, MFSEL3, 3, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(204, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(205, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW), +- NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DS(4, 8)), +- NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DS(4, 8)), ++ NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)), ++ NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), + NPCM7XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), + NPCM7XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), +@@ -1146,20 +1146,20 @@ static const struct npcm7xx_pincfg pincf + NPCM7XX_PINCFG(216, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0), + NPCM7XX_PINCFG(217, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0), + NPCM7XX_PINCFG(218, wdog1, MFSEL3, 19, none, NONE, 0, none, NONE, 0, 0), +- NPCM7XX_PINCFG(219, wdog2, MFSEL3, 20, none, NONE, 0, none, NONE, 0, DS(4, 8)), ++ NPCM7XX_PINCFG(219, wdog2, MFSEL3, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(220, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(221, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(222, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0), + NPCM7XX_PINCFG(223, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0), + + NPCM7XX_PINCFG(224, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, SLEW), +- NPCM7XX_PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO), +- NPCM7XX_PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO), +- NPCM7XX_PINCFG(227, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(228, spixcs1, MFSEL4, 28, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(229, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(230, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), +- NPCM7XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, DS(8, 12)), ++ NPCM7XX_PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), ++ NPCM7XX_PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), ++ NPCM7XX_PINCFG(227, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(228, spixcs1, MFSEL4, 28, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(229, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(230, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), ++ NPCM7XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */ + NPCM7XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */ + NPCM7XX_PINCFG(255, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* DACOSEL */ diff --git a/queue-5.10/pinctrl-nuvoton-npcm7xx-use-zu-printk-format-for-array_size.patch b/queue-5.10/pinctrl-nuvoton-npcm7xx-use-zu-printk-format-for-array_size.patch new file mode 100644 index 00000000000..f944d4c01cc --- /dev/null +++ b/queue-5.10/pinctrl-nuvoton-npcm7xx-use-zu-printk-format-for-array_size.patch @@ -0,0 +1,38 @@ +From 9d0f18bca3b557ae5d2128661ac06d33b3f45c0a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= +Date: Sat, 5 Feb 2022 16:53:30 +0100 +Subject: pinctrl: nuvoton: npcm7xx: Use %zu printk format for ARRAY_SIZE() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Jonathan Neuschäfer + +commit 9d0f18bca3b557ae5d2128661ac06d33b3f45c0a upstream. + +When compile-testing on 64-bit architectures, GCC complains about the +mismatch of types between the %d format specifier and value returned by +ARRAY_LENGTH(). Use %zu, which is correct everywhere. + +Reported-by: kernel test robot +Fixes: 3b588e43ee5c7 ("pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver") +Signed-off-by: Jonathan Neuschäfer +Reviewed-by: Andy Shevchenko +Link: https://lore.kernel.org/r/20220205155332.1308899-2-j.neuschaefer@gmx.net +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c ++++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +@@ -1560,7 +1560,7 @@ static int npcm7xx_get_groups_count(stru + { + struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); + +- dev_dbg(npcm->dev, "group size: %d\n", ARRAY_SIZE(npcm7xx_groups)); ++ dev_dbg(npcm->dev, "group size: %zu\n", ARRAY_SIZE(npcm7xx_groups)); + return ARRAY_SIZE(npcm7xx_groups); + } + diff --git a/queue-5.10/series b/queue-5.10/series index 718ad0f6479..866b884d52f 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -558,3 +558,9 @@ mailbox-imx-fix-wakeup-failure-from-freeze-mode.patch crypto-arm-aes-neonbs-cbc-select-generic-cbc-and-aes.patch watch_queue-free-the-page-array-when-watch_queue-is-dismantled.patch pinctrl-pinconf-generic-print-arguments-for-bias-pull.patch +watchdog-rti-wdt-add-missing-pm_runtime_disable-in-probe-function.patch +pinctrl-nuvoton-npcm7xx-rename-ds-macro-to-dstr.patch +pinctrl-nuvoton-npcm7xx-use-zu-printk-format-for-array_size.patch +asoc-mediatek-mt6358-add-missing-export_symbols.patch +ubi-fix-race-condition-between-ctrl_cdev_ioctl-and-ubi_cdev_ioctl.patch +arm-iop32x-offset-irq-numbers-by-1.patch diff --git a/queue-5.10/ubi-fix-race-condition-between-ctrl_cdev_ioctl-and-ubi_cdev_ioctl.patch b/queue-5.10/ubi-fix-race-condition-between-ctrl_cdev_ioctl-and-ubi_cdev_ioctl.patch new file mode 100644 index 00000000000..5173d12d4b5 --- /dev/null +++ b/queue-5.10/ubi-fix-race-condition-between-ctrl_cdev_ioctl-and-ubi_cdev_ioctl.patch @@ -0,0 +1,192 @@ +From 3cbf0e392f173ba0ce425968c8374a6aa3e90f2e Mon Sep 17 00:00:00 2001 +From: Baokun Li +Date: Fri, 5 Nov 2021 17:30:22 +0800 +Subject: ubi: Fix race condition between ctrl_cdev_ioctl and ubi_cdev_ioctl + +From: Baokun Li + +commit 3cbf0e392f173ba0ce425968c8374a6aa3e90f2e upstream. + +Hulk Robot reported a KASAN report about use-after-free: + ================================================================== + BUG: KASAN: use-after-free in __list_del_entry_valid+0x13d/0x160 + Read of size 8 at addr ffff888035e37d98 by task ubiattach/1385 + [...] + Call Trace: + klist_dec_and_del+0xa7/0x4a0 + klist_put+0xc7/0x1a0 + device_del+0x4d4/0xed0 + cdev_device_del+0x1a/0x80 + ubi_attach_mtd_dev+0x2951/0x34b0 [ubi] + ctrl_cdev_ioctl+0x286/0x2f0 [ubi] + + Allocated by task 1414: + device_add+0x60a/0x18b0 + cdev_device_add+0x103/0x170 + ubi_create_volume+0x1118/0x1a10 [ubi] + ubi_cdev_ioctl+0xb7f/0x1ba0 [ubi] + + Freed by task 1385: + cdev_device_del+0x1a/0x80 + ubi_remove_volume+0x438/0x6c0 [ubi] + ubi_cdev_ioctl+0xbf4/0x1ba0 [ubi] + [...] + ================================================================== + +The lock held by ctrl_cdev_ioctl is ubi_devices_mutex, but the lock held +by ubi_cdev_ioctl is ubi->device_mutex. Therefore, the two locks can be +concurrent. + +ctrl_cdev_ioctl contains two operations: ubi_attach and ubi_detach. +ubi_detach is bug-free because it uses reference counting to prevent +concurrency. However, uif_init and uif_close in ubi_attach may race with +ubi_cdev_ioctl. + +uif_init will race with ubi_cdev_ioctl as in the following stack. + cpu1 cpu2 cpu3 +_______________________|________________________|______________________ +ctrl_cdev_ioctl + ubi_attach_mtd_dev + uif_init + ubi_cdev_ioctl + ubi_create_volume + cdev_device_add + ubi_add_volume + // sysfs exist + kill_volumes + ubi_cdev_ioctl + ubi_remove_volume + cdev_device_del + // first free + ubi_free_volume + cdev_del + // double free + cdev_device_del + +And uif_close will race with ubi_cdev_ioctl as in the following stack. + cpu1 cpu2 cpu3 +_______________________|________________________|______________________ +ctrl_cdev_ioctl + ubi_attach_mtd_dev + uif_init + ubi_cdev_ioctl + ubi_create_volume + cdev_device_add + ubi_debugfs_init_dev + //error goto out_uif; + uif_close + kill_volumes + ubi_cdev_ioctl + ubi_remove_volume + cdev_device_del + // first free + ubi_free_volume + // double free + +The cause of this problem is that commit 714fb87e8bc0 make device +"available" before it becomes accessible via sysfs. Therefore, we +roll back the modification. We will fix the race condition between +ubi device creation and udev by removing ubi_get_device in +vol_attribute_show and dev_attribute_show.This avoids accessing +uninitialized ubi_devices[ubi_num]. + +ubi_get_device is used to prevent devices from being deleted during +sysfs execution. However, now kernfs ensures that devices will not +be deleted before all reference counting are released. +The key process is shown in the following stack. + +device_del + device_remove_attrs + device_remove_groups + sysfs_remove_groups + sysfs_remove_group + remove_files + kernfs_remove_by_name + kernfs_remove_by_name_ns + __kernfs_remove + kernfs_drain + +Fixes: 714fb87e8bc0 ("ubi: Fix race condition between ubi device creation and udev") +Reported-by: Hulk Robot +Signed-off-by: Baokun Li +Signed-off-by: Richard Weinberger +Signed-off-by: Greg Kroah-Hartman +--- + drivers/mtd/ubi/build.c | 9 +-------- + drivers/mtd/ubi/vmt.c | 8 +------- + 2 files changed, 2 insertions(+), 15 deletions(-) + +--- a/drivers/mtd/ubi/build.c ++++ b/drivers/mtd/ubi/build.c +@@ -350,9 +350,6 @@ static ssize_t dev_attribute_show(struct + * we still can use 'ubi->ubi_num'. + */ + ubi = container_of(dev, struct ubi_device, dev); +- ubi = ubi_get_device(ubi->ubi_num); +- if (!ubi) +- return -ENODEV; + + if (attr == &dev_eraseblock_size) + ret = sprintf(buf, "%d\n", ubi->leb_size); +@@ -381,7 +378,6 @@ static ssize_t dev_attribute_show(struct + else + ret = -EINVAL; + +- ubi_put_device(ubi); + return ret; + } + +@@ -980,9 +976,6 @@ int ubi_attach_mtd_dev(struct mtd_info * + goto out_detach; + } + +- /* Make device "available" before it becomes accessible via sysfs */ +- ubi_devices[ubi_num] = ubi; +- + err = uif_init(ubi); + if (err) + goto out_detach; +@@ -1027,6 +1020,7 @@ int ubi_attach_mtd_dev(struct mtd_info * + wake_up_process(ubi->bgt_thread); + spin_unlock(&ubi->wl_lock); + ++ ubi_devices[ubi_num] = ubi; + ubi_notify_all(ubi, UBI_VOLUME_ADDED, NULL); + return ubi_num; + +@@ -1035,7 +1029,6 @@ out_debugfs: + out_uif: + uif_close(ubi); + out_detach: +- ubi_devices[ubi_num] = NULL; + ubi_wl_close(ubi); + ubi_free_all_volumes(ubi); + vfree(ubi->vtbl); +--- a/drivers/mtd/ubi/vmt.c ++++ b/drivers/mtd/ubi/vmt.c +@@ -56,16 +56,11 @@ static ssize_t vol_attribute_show(struct + { + int ret; + struct ubi_volume *vol = container_of(dev, struct ubi_volume, dev); +- struct ubi_device *ubi; +- +- ubi = ubi_get_device(vol->ubi->ubi_num); +- if (!ubi) +- return -ENODEV; ++ struct ubi_device *ubi = vol->ubi; + + spin_lock(&ubi->volumes_lock); + if (!ubi->volumes[vol->vol_id]) { + spin_unlock(&ubi->volumes_lock); +- ubi_put_device(ubi); + return -ENODEV; + } + /* Take a reference to prevent volume removal */ +@@ -103,7 +98,6 @@ static ssize_t vol_attribute_show(struct + vol->ref_count -= 1; + ubi_assert(vol->ref_count >= 0); + spin_unlock(&ubi->volumes_lock); +- ubi_put_device(ubi); + return ret; + } + diff --git a/queue-5.10/watchdog-rti-wdt-add-missing-pm_runtime_disable-in-probe-function.patch b/queue-5.10/watchdog-rti-wdt-add-missing-pm_runtime_disable-in-probe-function.patch new file mode 100644 index 00000000000..9d8ce65096c --- /dev/null +++ b/queue-5.10/watchdog-rti-wdt-add-missing-pm_runtime_disable-in-probe-function.patch @@ -0,0 +1,33 @@ +From d055ef3a2c6919cff504ae3b710c96318d545fd2 Mon Sep 17 00:00:00 2001 +From: Miaoqian Lin +Date: Wed, 5 Jan 2022 09:21:13 +0000 +Subject: watchdog: rti-wdt: Add missing pm_runtime_disable() in probe function + +From: Miaoqian Lin + +commit d055ef3a2c6919cff504ae3b710c96318d545fd2 upstream. + +If the probe fails, we should use pm_runtime_disable() to balance +pm_runtime_enable(). + +Fixes: 2d63908bdbfb ("watchdog: Add K3 RTI watchdog support") +Signed-off-by: Miaoqian Lin +Reviewed-by: Guenter Roeck +Link: https://lore.kernel.org/r/20220105092114.23932-1-linmq006@gmail.com +Signed-off-by: Guenter Roeck +Signed-off-by: Wim Van Sebroeck +Signed-off-by: Greg Kroah-Hartman +--- + drivers/watchdog/rti_wdt.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/watchdog/rti_wdt.c ++++ b/drivers/watchdog/rti_wdt.c +@@ -229,6 +229,7 @@ static int rti_wdt_probe(struct platform + ret = pm_runtime_get_sync(dev); + if (ret) { + pm_runtime_put_noidle(dev); ++ pm_runtime_disable(&pdev->dev); + return dev_err_probe(dev, ret, "runtime pm failed\n"); + } +