From: Palmer Dabbelt Date: Mon, 19 Jun 2023 19:01:43 +0000 (-0700) Subject: RISC-V: Document that V registers are clobbered on syscalls X-Git-Tag: v6.5-rc1~25^2~16 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=bcc8790057c1f02d20654f68d107973405c1f823;p=thirdparty%2Fkernel%2Flinux.git RISC-V: Document that V registers are clobbered on syscalls This is included in the ISA manual, but it's pretty common for bits of the ISA manual that are actually ABI to change. So let's document it explicitly. Reviewed-by: Björn Töpel Link: https://lore.kernel.org/r/20230619190142.26498-1-palmer@rivosinc.com Signed-off-by: Palmer Dabbelt --- diff --git a/Documentation/riscv/vector.rst b/Documentation/riscv/vector.rst index 48f189d79e413..165b7ed0ac4f1 100644 --- a/Documentation/riscv/vector.rst +++ b/Documentation/riscv/vector.rst @@ -130,3 +130,11 @@ processes in form of sysctl knob: Modifying the system default enablement status does not affect the enablement status of any existing process of thread that do not make an execve() call. + +3. Vector Register State Across System Calls +--------------------------------------------- + +As indicated by version 1.0 of the V extension [1], vector registers are +clobbered by system calls. + +1: https://github.com/riscv/riscv-v-spec/blob/master/calling-convention.adoc