From: Greg Kroah-Hartman Date: Mon, 10 Feb 2014 20:01:02 +0000 (-0800) Subject: 3.4-stable patches X-Git-Tag: v3.4.80~38 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=bd252091889f7a585dcc84967874486b8d14f8db;p=thirdparty%2Fkernel%2Fstable-queue.git 3.4-stable patches added patches: drm-radeon-dce4-clear-bios-scratch-dpms-bit-v2.patch drm-radeon-set-the-full-cache-bit-for-fences-on-r7xx.patch drm-radeon-skip-colorbuffer-checking-if-color_info.format-is-set-to-invalid.patch --- diff --git a/queue-3.4/drm-radeon-dce4-clear-bios-scratch-dpms-bit-v2.patch b/queue-3.4/drm-radeon-dce4-clear-bios-scratch-dpms-bit-v2.patch new file mode 100644 index 00000000000..a171470f812 --- /dev/null +++ b/queue-3.4/drm-radeon-dce4-clear-bios-scratch-dpms-bit-v2.patch @@ -0,0 +1,38 @@ +From 6802d4bad83f50081b2788698570218aaff8d10e Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Mon, 27 Jan 2014 18:29:35 -0500 +Subject: drm/radeon/DCE4+: clear bios scratch dpms bit (v2) + +From: Alex Deucher + +commit 6802d4bad83f50081b2788698570218aaff8d10e upstream. + +The BlankCrtc table in some DCE8 boards has some +logic shortcuts for the vbios when this bit is set. +Clear it for driver use. + +v2: fix typo + +Bug: +https://bugs.freedesktop.org/show_bug.cgi?id=73420 + +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/radeon_atombios.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/gpu/drm/radeon/radeon_atombios.c ++++ b/drivers/gpu/drm/radeon/radeon_atombios.c +@@ -2785,6 +2785,10 @@ void radeon_atom_initialize_bios_scratch + /* tell the bios not to handle mode switching */ + bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; + ++ /* clear the vbios dpms state */ ++ if (ASIC_IS_DCE4(rdev)) ++ bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE; ++ + if (rdev->family >= CHIP_R600) { + WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); + WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); diff --git a/queue-3.4/drm-radeon-set-the-full-cache-bit-for-fences-on-r7xx.patch b/queue-3.4/drm-radeon-set-the-full-cache-bit-for-fences-on-r7xx.patch new file mode 100644 index 00000000000..7b5b1a8c9dc --- /dev/null +++ b/queue-3.4/drm-radeon-set-the-full-cache-bit-for-fences-on-r7xx.patch @@ -0,0 +1,63 @@ +From d45b964a22cad962d3ede1eba8d24f5cee7b2a92 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Thu, 16 Jan 2014 18:11:47 -0500 +Subject: drm/radeon: set the full cache bit for fences on r7xx+ + +From: Alex Deucher + +commit d45b964a22cad962d3ede1eba8d24f5cee7b2a92 upstream. + +Needed to properly flush the read caches for fences. + +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/r600.c | 13 +++++++------ + drivers/gpu/drm/radeon/r600d.h | 1 + + 2 files changed, 8 insertions(+), 6 deletions(-) + +--- a/drivers/gpu/drm/radeon/r600.c ++++ b/drivers/gpu/drm/radeon/r600.c +@@ -2313,14 +2313,17 @@ void r600_fence_ring_emit(struct radeon_ + struct radeon_fence *fence) + { + struct radeon_ring *ring = &rdev->ring[fence->ring]; ++ u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA | ++ PACKET3_SH_ACTION_ENA; ++ ++ if (rdev->family >= CHIP_RV770) ++ cp_coher_cntl |= PACKET3_FULL_CACHE_ENA; + + if (rdev->wb.use_event) { + u64 addr = rdev->fence_drv[fence->ring].gpu_addr; + /* flush read cache over gart */ + radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); +- radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | +- PACKET3_VC_ACTION_ENA | +- PACKET3_SH_ACTION_ENA); ++ radeon_ring_write(ring, cp_coher_cntl); + radeon_ring_write(ring, 0xFFFFFFFF); + radeon_ring_write(ring, 0); + radeon_ring_write(ring, 10); /* poll interval */ +@@ -2334,9 +2337,7 @@ void r600_fence_ring_emit(struct radeon_ + } else { + /* flush read cache over gart */ + radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); +- radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | +- PACKET3_VC_ACTION_ENA | +- PACKET3_SH_ACTION_ENA); ++ radeon_ring_write(ring, cp_coher_cntl); + radeon_ring_write(ring, 0xFFFFFFFF); + radeon_ring_write(ring, 0); + radeon_ring_write(ring, 10); /* poll interval */ +--- a/drivers/gpu/drm/radeon/r600d.h ++++ b/drivers/gpu/drm/radeon/r600d.h +@@ -873,6 +873,7 @@ + #define PACKET3_INDIRECT_BUFFER 0x32 + #define PACKET3_SURFACE_SYNC 0x43 + # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) ++# define PACKET3_FULL_CACHE_ENA (1 << 20) /* r7xx+ only */ + # define PACKET3_TC_ACTION_ENA (1 << 23) + # define PACKET3_VC_ACTION_ENA (1 << 24) + # define PACKET3_CB_ACTION_ENA (1 << 25) diff --git a/queue-3.4/drm-radeon-skip-colorbuffer-checking-if-color_info.format-is-set-to-invalid.patch b/queue-3.4/drm-radeon-skip-colorbuffer-checking-if-color_info.format-is-set-to-invalid.patch new file mode 100644 index 00000000000..9847cd2b9f8 --- /dev/null +++ b/queue-3.4/drm-radeon-skip-colorbuffer-checking-if-color_info.format-is-set-to-invalid.patch @@ -0,0 +1,52 @@ +From 56492e0fac2dbaf7735ffd66b206a90624917789 Mon Sep 17 00:00:00 2001 +From: Marek Olšák +Date: Wed, 8 Jan 2014 18:16:26 +0100 +Subject: drm/radeon: skip colorbuffer checking if COLOR_INFO.FORMAT is set to INVALID +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Marek Olšák + +commit 56492e0fac2dbaf7735ffd66b206a90624917789 upstream. + +This fixes a bug which was causing rejections of valid GPU commands +from userspace. + +Signed-off-by: Marek Olšák +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/evergreen_cs.c | 5 ++++- + drivers/gpu/drm/radeon/r600_cs.c | 5 ++++- + 2 files changed, 8 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/radeon/evergreen_cs.c ++++ b/drivers/gpu/drm/radeon/evergreen_cs.c +@@ -942,7 +942,10 @@ static int evergreen_cs_track_check(stru + if (track->cb_dirty) { + tmp = track->cb_target_mask; + for (i = 0; i < 8; i++) { +- if ((tmp >> (i * 4)) & 0xF) { ++ u32 format = G_028C70_FORMAT(track->cb_color_info[i]); ++ ++ if (format != V_028C70_COLOR_INVALID && ++ (tmp >> (i * 4)) & 0xF) { + /* at least one component is enabled */ + if (track->cb_color_bo[i] == NULL) { + dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", +--- a/drivers/gpu/drm/radeon/r600_cs.c ++++ b/drivers/gpu/drm/radeon/r600_cs.c +@@ -747,7 +747,10 @@ static int r600_cs_track_check(struct ra + if (track->cb_dirty) { + tmp = track->cb_target_mask; + for (i = 0; i < 8; i++) { +- if ((tmp >> (i * 4)) & 0xF) { ++ u32 format = G_0280A0_FORMAT(track->cb_color_info[i]); ++ ++ if (format != V_0280A0_COLOR_INVALID && ++ (tmp >> (i * 4)) & 0xF) { + /* at least one component is enabled */ + if (track->cb_color_bo[i] == NULL) { + dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", diff --git a/queue-3.4/series b/queue-3.4/series index 61289df5a46..512f993e2d4 100644 --- a/queue-3.4/series +++ b/queue-3.4/series @@ -16,3 +16,6 @@ dm-wait-until-embedded-kobject-is-released-before-destroying-a-device.patch dm-space-map-common-make-sure-new-space-is-used-during-extend.patch drm-radeon-warn-users-when-hw_i2c-is-enabled-v2.patch radeon-pm-guard-access-to-rdev-pm.power_state-array.patch +drm-radeon-skip-colorbuffer-checking-if-color_info.format-is-set-to-invalid.patch +drm-radeon-set-the-full-cache-bit-for-fences-on-r7xx.patch +drm-radeon-dce4-clear-bios-scratch-dpms-bit-v2.patch