From: Jeff Law <jlaw@ventanamicro.com>
Date: Tue, 24 Jun 2025 00:27:49 +0000 (-0600)
Subject: [RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=bf7162b321128ba93521a824e5a7a00d1cc3d1f8;p=thirdparty%2Fgcc.git

[RISC-V][PR target/118241] Fix data prefetch predicate/constraint for RISC-V

Fix typo in comment spotted by Peter B.

	PR target/118241
gcc/
	* config/riscv/predicates.md: Fix comment typo in recent change.
---

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 8072d67fbd9..061904b6e00 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -27,7 +27,7 @@
   (ior (match_operand 0 "const_arith_operand")
        (match_operand 0 "register_operand")))
 
-;; REG or REG+D where D fits in a simm12 and has the low 4 bits
+;; REG or REG+D where D fits in a simm12 and has the low 5 bits
 ;; off.  The REG+D form can be reloaded into a temporary if needed
 ;; after FP elimination if that exposes an invalid offset.
 (define_predicate "prefetch_operand"