From: Greg Kroah-Hartman Date: Sun, 22 Jan 2023 14:36:34 +0000 (+0100) Subject: 6.1-stable patches X-Git-Tag: v4.14.304~17 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=c01c3d7cf35b4864f3eaafe7b8c61cc81fd81e02;p=thirdparty%2Fkernel%2Fstable-queue.git 6.1-stable patches added patches: drm-amdgpu-add-gfx-support-for-gc-11.0.4.patch drm-amdgpu-add-gmc-v11-support-for-gc-11.0.4.patch drm-amdgpu-add-smu-13-support-for-smu-13.0.11.patch drm-amdgpu-add-tmz-support-for-gc-11.0.1.patch drm-amdgpu-add-tmz-support-for-gc-ip-v11.0.4.patch drm-amdgpu-correct-mec-number-for-gfx11-apus.patch drm-amdgpu-discovery-add-psp-ip-v13.0.11-support.patch drm-amdgpu-discovery-enable-gfx-v11-for-gc-11.0.4.patch drm-amdgpu-discovery-enable-gmc-v11-for-gc-11.0.4.patch drm-amdgpu-discovery-enable-mes-support-for-gc-v11.0.4.patch drm-amdgpu-discovery-enable-nbio-support-for-nbio-v7.7.1.patch drm-amdgpu-discovery-enable-soc21-common-for-gc-11.0.4.patch drm-amdgpu-discovery-set-the-apu-flag-for-gc-11.0.4.patch drm-amdgpu-enable-gfx-clock-gating-control-for-gc-ip-v11.0.4.patch drm-amdgpu-enable-gfx-ip-v11.0.4-cg-support.patch drm-amdgpu-enable-gfx-power-gating-for-gc-ip-v11.0.4.patch drm-amdgpu-enable-psp-ip-v13.0.11-support.patch drm-amdgpu-pm-add-gfxoff-control-ip-version-check-for-smu-ip-v13.0.11.patch drm-amdgpu-pm-enable-swsmu-for-smu-ip-v13.0.11.patch drm-amdgpu-pm-use-the-specific-mailbox-registers-only-for-smu-ip-v13.0.4.patch drm-amdgpu-set-gc-11.0.4-family.patch drm-amdgpu-soc21-add-mode2-asic-reset-for-smu-ip-v13.0.11.patch --- diff --git a/queue-6.1/drm-amdgpu-add-gfx-support-for-gc-11.0.4.patch b/queue-6.1/drm-amdgpu-add-gfx-support-for-gc-11.0.4.patch new file mode 100644 index 00000000000..d6abcf12ce5 --- /dev/null +++ b/queue-6.1/drm-amdgpu-add-gfx-support-for-gc-11.0.4.patch @@ -0,0 +1,67 @@ +From 1763cb65e870e783e26d2dc9def4edbeadcb1050 Mon Sep 17 00:00:00 2001 +From: Yifan Zhang +Date: Wed, 12 Oct 2022 12:49:06 +0800 +Subject: drm/amdgpu: add gfx support for GC 11.0.4 + +From: Yifan Zhang + +commit 1763cb65e870e783e26d2dc9def4edbeadcb1050 upstream. + +this patch to add GC 11.0.4 gfx support to gfx11 implementation. + +Signed-off-by: Yifan Zhang +Reviewed-by: Aaron Liu +Signed-off-by: Alex Deucher +Cc: "Limonciello, Mario" +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +@@ -77,6 +77,10 @@ MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bi + MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin"); + MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin"); + MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin"); ++MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin"); ++MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin"); ++MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin"); ++MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin"); + + static const struct soc15_reg_golden golden_settings_gc_11_0_1[] = + { +@@ -262,6 +266,7 @@ static void gfx_v11_0_init_golden_regist + { + switch (adev->ip_versions[GC_HWIP][0]) { + case IP_VERSION(11, 0, 1): ++ case IP_VERSION(11, 0, 4): + soc15_program_register_sequence(adev, + golden_settings_gc_11_0_1, + (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1)); +@@ -856,6 +861,7 @@ static int gfx_v11_0_gpu_early_init(stru + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; + break; + case IP_VERSION(11, 0, 1): ++ case IP_VERSION(11, 0, 4): + adev->gfx.config.max_hw_contexts = 8; + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; +@@ -1285,6 +1291,7 @@ static int gfx_v11_0_sw_init(void *handl + case IP_VERSION(11, 0, 1): + case IP_VERSION(11, 0, 2): + case IP_VERSION(11, 0, 3): ++ case IP_VERSION(11, 0, 4): + adev->gfx.me.num_me = 1; + adev->gfx.me.num_pipe_per_me = 1; + adev->gfx.me.num_queue_per_pipe = 1; +@@ -2486,7 +2493,8 @@ static int gfx_v11_0_wait_for_rlc_autolo + for (i = 0; i < adev->usec_timeout; i++) { + cp_status = RREG32_SOC15(GC, 0, regCP_STAT); + +- if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 1)) ++ if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 1) || ++ adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 4)) + bootload_status = RREG32_SOC15(GC, 0, + regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1); + else diff --git a/queue-6.1/drm-amdgpu-add-gmc-v11-support-for-gc-11.0.4.patch b/queue-6.1/drm-amdgpu-add-gmc-v11-support-for-gc-11.0.4.patch new file mode 100644 index 00000000000..45e70cab314 --- /dev/null +++ b/queue-6.1/drm-amdgpu-add-gmc-v11-support-for-gc-11.0.4.patch @@ -0,0 +1,30 @@ +From d0ca8248999e4c5b02ac64f40536ff46dc14dda7 Mon Sep 17 00:00:00 2001 +From: Yifan Zhang +Date: Wed, 12 Oct 2022 12:56:01 +0800 +Subject: drm/amdgpu: add gmc v11 support for GC 11.0.4 + +From: Yifan Zhang + +commit d0ca8248999e4c5b02ac64f40536ff46dc14dda7 upstream. + +Add gmc v11 support for GC 11.0.4. + +Signed-off-by: Yifan Zhang +Reviewed-by: Aaron Liu +Signed-off-by: Alex Deucher +Cc: "Limonciello, Mario" +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +@@ -749,6 +749,7 @@ static int gmc_v11_0_sw_init(void *handl + case IP_VERSION(11, 0, 1): + case IP_VERSION(11, 0, 2): + case IP_VERSION(11, 0, 3): ++ case IP_VERSION(11, 0, 4): + adev->num_vmhubs = 2; + /* + * To fulfill 4-level page support, diff --git a/queue-6.1/drm-amdgpu-add-smu-13-support-for-smu-13.0.11.patch b/queue-6.1/drm-amdgpu-add-smu-13-support-for-smu-13.0.11.patch new file mode 100644 index 00000000000..6803abd43e0 --- /dev/null +++ b/queue-6.1/drm-amdgpu-add-smu-13-support-for-smu-13.0.11.patch @@ -0,0 +1,49 @@ +From 51e7a2168769c2f46edd93a18d4cba4a6d4adb13 Mon Sep 17 00:00:00 2001 +From: Yifan Zhang +Date: Wed, 12 Oct 2022 13:16:25 +0800 +Subject: drm/amdgpu: add smu 13 support for smu 13.0.11 + +From: Yifan Zhang + +commit 51e7a2168769c2f46edd93a18d4cba4a6d4adb13 upstream. + +this patch to add smu 13 support for smu 13.0.11. + +Signed-off-by: Yifan Zhang +Reviewed-by: Aaron Liu +Signed-off-by: Alex Deucher +Cc: "Limonciello, Mario" +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 2 ++ + 2 files changed, 3 insertions(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +@@ -1689,6 +1689,7 @@ static int amdgpu_discovery_set_smu_ip_b + case IP_VERSION(13, 0, 7): + case IP_VERSION(13, 0, 8): + case IP_VERSION(13, 0, 10): ++ case IP_VERSION(13, 0, 11): + amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); + break; + default: +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +@@ -250,6 +250,7 @@ int smu_v13_0_check_fw_status(struct smu + + switch (adev->ip_versions[MP1_HWIP][0]) { + case IP_VERSION(13, 0, 4): ++ case IP_VERSION(13, 0, 11): + mp1_fw_flags = RREG32_PCIE(MP1_Public | + (smnMP1_V13_0_4_FIRMWARE_FLAGS & 0xffffffff)); + break; +@@ -303,6 +304,7 @@ int smu_v13_0_check_fw_version(struct sm + smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_YELLOW_CARP; + break; + case IP_VERSION(13, 0, 4): ++ case IP_VERSION(13, 0, 11): + smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_SMU_V13_0_4; + break; + case IP_VERSION(13, 0, 5): diff --git a/queue-6.1/drm-amdgpu-add-tmz-support-for-gc-11.0.1.patch b/queue-6.1/drm-amdgpu-add-tmz-support-for-gc-11.0.1.patch new file mode 100644 index 00000000000..5631e545b8c --- /dev/null +++ b/queue-6.1/drm-amdgpu-add-tmz-support-for-gc-11.0.1.patch @@ -0,0 +1,30 @@ +From 97074216917b4188f0af3e52cc5b3f2b277bbbca Mon Sep 17 00:00:00 2001 +From: Yifan Zhang +Date: Sun, 9 Oct 2022 14:35:20 +0800 +Subject: drm/amdgpu: add tmz support for GC 11.0.1 + +From: Yifan Zhang + +commit 97074216917b4188f0af3e52cc5b3f2b277bbbca upstream. + +this patch to add tmz support for GC 11.0.1. + +Signed-off-by: Yifan Zhang +Reviewed-by: Tim Huang +Signed-off-by: Alex Deucher +Cc: "Limonciello, Mario" +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +@@ -548,6 +548,7 @@ void amdgpu_gmc_tmz_set(struct amdgpu_de + case IP_VERSION(10, 3, 1): + /* YELLOW_CARP*/ + case IP_VERSION(10, 3, 3): ++ case IP_VERSION(11, 0, 1): + /* Don't enable it by default yet. + */ + if (amdgpu_tmz < 1) { diff --git a/queue-6.1/drm-amdgpu-add-tmz-support-for-gc-ip-v11.0.4.patch b/queue-6.1/drm-amdgpu-add-tmz-support-for-gc-ip-v11.0.4.patch new file mode 100644 index 00000000000..f095167400f --- /dev/null +++ b/queue-6.1/drm-amdgpu-add-tmz-support-for-gc-ip-v11.0.4.patch @@ -0,0 +1,30 @@ +From 2aecbe492a3c0bf4c21f78c099a6f6c205fab0c7 Mon Sep 17 00:00:00 2001 +From: Tim Huang +Date: Mon, 5 Dec 2022 14:33:25 +0800 +Subject: drm/amdgpu: add tmz support for GC IP v11.0.4 + +From: Tim Huang + +commit 2aecbe492a3c0bf4c21f78c099a6f6c205fab0c7 upstream. + +Add tmz support for GC 11.0.4. + +Signed-off-by: Tim Huang +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Cc: "Limonciello, Mario" +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +@@ -549,6 +549,7 @@ void amdgpu_gmc_tmz_set(struct amdgpu_de + /* YELLOW_CARP*/ + case IP_VERSION(10, 3, 3): + case IP_VERSION(11, 0, 1): ++ case IP_VERSION(11, 0, 4): + /* Don't enable it by default yet. + */ + if (amdgpu_tmz < 1) { diff --git a/queue-6.1/drm-amdgpu-correct-mec-number-for-gfx11-apus.patch b/queue-6.1/drm-amdgpu-correct-mec-number-for-gfx11-apus.patch new file mode 100644 index 00000000000..835df8e8df6 --- /dev/null +++ b/queue-6.1/drm-amdgpu-correct-mec-number-for-gfx11-apus.patch @@ -0,0 +1,50 @@ +From 0ddadc3a2208aedb1b27dbb76d0b4e722b5b527a Mon Sep 17 00:00:00 2001 +From: Lang Yu +Date: Wed, 11 Jan 2023 09:52:11 +0800 +Subject: drm/amdgpu: correct MEC number for gfx11 APUs + +From: Lang Yu + +commit 0ddadc3a2208aedb1b27dbb76d0b4e722b5b527a upstream. + +There is only one MEC on these APUs. + +Signed-off-by: Lang Yu +Reviewed-by: Aaron Liu +Reviewed-by: Yifan Zhang +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.1.x +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 11 +++++++++-- + 1 file changed, 9 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +@@ -1288,10 +1288,8 @@ static int gfx_v11_0_sw_init(void *handl + + switch (adev->ip_versions[GC_HWIP][0]) { + case IP_VERSION(11, 0, 0): +- case IP_VERSION(11, 0, 1): + case IP_VERSION(11, 0, 2): + case IP_VERSION(11, 0, 3): +- case IP_VERSION(11, 0, 4): + adev->gfx.me.num_me = 1; + adev->gfx.me.num_pipe_per_me = 1; + adev->gfx.me.num_queue_per_pipe = 1; +@@ -1299,6 +1297,15 @@ static int gfx_v11_0_sw_init(void *handl + adev->gfx.mec.num_pipe_per_mec = 4; + adev->gfx.mec.num_queue_per_pipe = 4; + break; ++ case IP_VERSION(11, 0, 1): ++ case IP_VERSION(11, 0, 4): ++ adev->gfx.me.num_me = 1; ++ adev->gfx.me.num_pipe_per_me = 1; ++ adev->gfx.me.num_queue_per_pipe = 1; ++ adev->gfx.mec.num_mec = 1; ++ adev->gfx.mec.num_pipe_per_mec = 4; ++ adev->gfx.mec.num_queue_per_pipe = 4; ++ break; + default: + adev->gfx.me.num_me = 1; + adev->gfx.me.num_pipe_per_me = 1; diff --git a/queue-6.1/drm-amdgpu-discovery-add-psp-ip-v13.0.11-support.patch b/queue-6.1/drm-amdgpu-discovery-add-psp-ip-v13.0.11-support.patch new file mode 100644 index 00000000000..0f199d59e22 --- /dev/null +++ b/queue-6.1/drm-amdgpu-discovery-add-psp-ip-v13.0.11-support.patch @@ -0,0 +1,31 @@ +From 7c1389f1b1228b96e621815e63eaa2e89b9f7511 Mon Sep 17 00:00:00 2001 +From: Tim Huang +Date: Mon, 21 Nov 2022 16:19:44 +0800 +Subject: drm/amdgpu/discovery: add PSP IP v13.0.11 support + +From: Tim Huang + +commit 7c1389f1b1228b96e621815e63eaa2e89b9f7511 upstream. + +Add PSP IP v13.0.11 ip discovery support. + +Signed-off-by: Tim Huang +Signed-off-by: Yifan Zhang +Reviewed-by: Aaron Liu +Signed-off-by: Alex Deucher +Cc: "Limonciello, Mario" +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +@@ -1638,6 +1638,7 @@ static int amdgpu_discovery_set_psp_ip_b + case IP_VERSION(13, 0, 7): + case IP_VERSION(13, 0, 8): + case IP_VERSION(13, 0, 10): ++ case IP_VERSION(13, 0, 11): + amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); + break; + case IP_VERSION(13, 0, 4): diff --git a/queue-6.1/drm-amdgpu-discovery-enable-gfx-v11-for-gc-11.0.4.patch b/queue-6.1/drm-amdgpu-discovery-enable-gfx-v11-for-gc-11.0.4.patch new file mode 100644 index 00000000000..34336832f50 --- /dev/null +++ b/queue-6.1/drm-amdgpu-discovery-enable-gfx-v11-for-gc-11.0.4.patch @@ -0,0 +1,30 @@ +From b952d6b3d3ff3c1570fab77f2137d5e5280a0e57 Mon Sep 17 00:00:00 2001 +From: Yifan Zhang +Date: Wed, 12 Oct 2022 11:11:09 +0800 +Subject: drm/amdgpu/discovery: enable gfx v11 for GC 11.0.4 + +From: Yifan Zhang + +commit b952d6b3d3ff3c1570fab77f2137d5e5280a0e57 upstream. + +Enable gfx v11 for GC 11.0.4. + +Signed-off-by: Yifan Zhang +Reviewed-by: Aaron Liu +Signed-off-by: Alex Deucher +Cc: "Limonciello, Mario" +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +@@ -1787,6 +1787,7 @@ static int amdgpu_discovery_set_gc_ip_bl + case IP_VERSION(11, 0, 1): + case IP_VERSION(11, 0, 2): + case IP_VERSION(11, 0, 3): ++ case IP_VERSION(11, 0, 4): + amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); + break; + default: diff --git a/queue-6.1/drm-amdgpu-discovery-enable-gmc-v11-for-gc-11.0.4.patch b/queue-6.1/drm-amdgpu-discovery-enable-gmc-v11-for-gc-11.0.4.patch new file mode 100644 index 00000000000..83c4dcfe4db --- /dev/null +++ b/queue-6.1/drm-amdgpu-discovery-enable-gmc-v11-for-gc-11.0.4.patch @@ -0,0 +1,30 @@ +From d5fd8c89ed206b2df3933bc4ea129401b2b60869 Mon Sep 17 00:00:00 2001 +From: Yifan Zhang +Date: Wed, 12 Oct 2022 11:09:50 +0800 +Subject: drm/amdgpu/discovery: enable gmc v11 for GC 11.0.4 + +From: Yifan Zhang + +commit d5fd8c89ed206b2df3933bc4ea129401b2b60869 upstream. + +Enable gmc (graphic memory controller) v11 for GC 11.0.4. + +Signed-off-by: Yifan Zhang +Reviewed-by: Aaron Liu +Signed-off-by: Alex Deucher +Cc: "Limonciello, Mario" +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +@@ -1552,6 +1552,7 @@ static int amdgpu_discovery_set_gmc_ip_b + case IP_VERSION(11, 0, 1): + case IP_VERSION(11, 0, 2): + case IP_VERSION(11, 0, 3): ++ case IP_VERSION(11, 0, 4): + amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); + break; + default: diff --git a/queue-6.1/drm-amdgpu-discovery-enable-mes-support-for-gc-v11.0.4.patch b/queue-6.1/drm-amdgpu-discovery-enable-mes-support-for-gc-v11.0.4.patch new file mode 100644 index 00000000000..19be7872158 --- /dev/null +++ b/queue-6.1/drm-amdgpu-discovery-enable-mes-support-for-gc-v11.0.4.patch @@ -0,0 +1,30 @@ +From 6a6af77570add4e58721386be429dbd02cd4b9dd Mon Sep 17 00:00:00 2001 +From: Yifan Zhang +Date: Wed, 12 Oct 2022 11:11:57 +0800 +Subject: drm/amdgpu/discovery: enable mes support for GC v11.0.4 + +From: Yifan Zhang + +commit 6a6af77570add4e58721386be429dbd02cd4b9dd upstream. + +this patch is to enable mes for GC 11.0.4. + +Signed-off-by: Yifan Zhang +Reviewed-by: Aaron Liu +Signed-off-by: Alex Deucher +Cc: "Limonciello, Mario" +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +@@ -1951,6 +1951,7 @@ static int amdgpu_discovery_set_mes_ip_b + case IP_VERSION(11, 0, 1): + case IP_VERSION(11, 0, 2): + case IP_VERSION(11, 0, 3): ++ case IP_VERSION(11, 0, 4): + amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); + adev->enable_mes = true; + adev->enable_mes_kiq = true; diff --git a/queue-6.1/drm-amdgpu-discovery-enable-nbio-support-for-nbio-v7.7.1.patch b/queue-6.1/drm-amdgpu-discovery-enable-nbio-support-for-nbio-v7.7.1.patch new file mode 100644 index 00000000000..fc21b00dd8f --- /dev/null +++ b/queue-6.1/drm-amdgpu-discovery-enable-nbio-support-for-nbio-v7.7.1.patch @@ -0,0 +1,30 @@ +From 7308ceb44663f40bf9e7373c3b1aa4f7f433d625 Mon Sep 17 00:00:00 2001 +From: Yifan Zhang +Date: Tue, 25 Oct 2022 16:59:44 +0800 +Subject: drm/amdgpu/discovery: enable nbio support for NBIO v7.7.1 + +From: Yifan Zhang + +commit 7308ceb44663f40bf9e7373c3b1aa4f7f433d625 upstream. + +this patch is to enable nbio support for NBIO v7.7.1. + +Signed-off-by: Yifan Zhang +Reviewed-by: Aaron Liu +Signed-off-by: Alex Deucher +Cc: "Limonciello, Mario" +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +@@ -2258,6 +2258,7 @@ int amdgpu_discovery_set_ip_blocks(struc + adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; + break; + case IP_VERSION(7, 7, 0): ++ case IP_VERSION(7, 7, 1): + adev->nbio.funcs = &nbio_v7_7_funcs; + adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; + break; diff --git a/queue-6.1/drm-amdgpu-discovery-enable-soc21-common-for-gc-11.0.4.patch b/queue-6.1/drm-amdgpu-discovery-enable-soc21-common-for-gc-11.0.4.patch new file mode 100644 index 00000000000..3954f63394e --- /dev/null +++ b/queue-6.1/drm-amdgpu-discovery-enable-soc21-common-for-gc-11.0.4.patch @@ -0,0 +1,30 @@ +From 69dc98bbd44160930b6b3ca9ca558f89435d2702 Mon Sep 17 00:00:00 2001 +From: Yifan Zhang +Date: Wed, 12 Oct 2022 11:08:49 +0800 +Subject: drm/amdgpu/discovery: enable soc21 common for GC 11.0.4 + +From: Yifan Zhang + +commit 69dc98bbd44160930b6b3ca9ca558f89435d2702 upstream. + +Enable soc21 common for GC 11.0.4. + +Signed-off-by: Yifan Zhang +Reviewed-by: Aaron Liu +Signed-off-by: Alex Deucher +Cc: "Limonciello, Mario" +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +@@ -1507,6 +1507,7 @@ static int amdgpu_discovery_set_common_i + case IP_VERSION(11, 0, 1): + case IP_VERSION(11, 0, 2): + case IP_VERSION(11, 0, 3): ++ case IP_VERSION(11, 0, 4): + amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); + break; + default: diff --git a/queue-6.1/drm-amdgpu-discovery-set-the-apu-flag-for-gc-11.0.4.patch b/queue-6.1/drm-amdgpu-discovery-set-the-apu-flag-for-gc-11.0.4.patch new file mode 100644 index 00000000000..be41e621ccd --- /dev/null +++ b/queue-6.1/drm-amdgpu-discovery-set-the-apu-flag-for-gc-11.0.4.patch @@ -0,0 +1,30 @@ +From dd2d9c7fd7716838d477e257f43facd68c53d3a9 Mon Sep 17 00:00:00 2001 +From: Yifan Zhang +Date: Wed, 12 Oct 2022 11:16:29 +0800 +Subject: drm/amdgpu/discovery: set the APU flag for GC 11.0.4 + +From: Yifan Zhang + +commit dd2d9c7fd7716838d477e257f43facd68c53d3a9 upstream. + +Set the APU flag appropriately for GC 11.0.4. + +Signed-off-by: Yifan Zhang +Reviewed-by: Aaron Liu +Signed-off-by: Alex Deucher +Cc: "Limonciello, Mario" +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +@@ -2199,6 +2199,7 @@ int amdgpu_discovery_set_ip_blocks(struc + case IP_VERSION(10, 3, 6): + case IP_VERSION(10, 3, 7): + case IP_VERSION(11, 0, 1): ++ case IP_VERSION(11, 0, 4): + adev->flags |= AMD_IS_APU; + break; + default: diff --git a/queue-6.1/drm-amdgpu-enable-gfx-clock-gating-control-for-gc-ip-v11.0.4.patch b/queue-6.1/drm-amdgpu-enable-gfx-clock-gating-control-for-gc-ip-v11.0.4.patch new file mode 100644 index 00000000000..ef8c80d7b33 --- /dev/null +++ b/queue-6.1/drm-amdgpu-enable-gfx-clock-gating-control-for-gc-ip-v11.0.4.patch @@ -0,0 +1,30 @@ +From f9caa237372b106b5e70ba1a4bfd4222eb79ec71 Mon Sep 17 00:00:00 2001 +From: Tim Huang +Date: Mon, 5 Dec 2022 14:18:23 +0800 +Subject: drm/amdgpu: enable GFX Clock Gating control for GC IP v11.0.4 + +From: Tim Huang + +commit f9caa237372b106b5e70ba1a4bfd4222eb79ec71 upstream. + +Enable GFX IP v11.0.4 CG gate/ungate control. + +Signed-off-by: Tim Huang +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Cc: "Limonciello, Mario" +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +@@ -5088,6 +5088,7 @@ static int gfx_v11_0_set_clockgating_sta + case IP_VERSION(11, 0, 1): + case IP_VERSION(11, 0, 2): + case IP_VERSION(11, 0, 3): ++ case IP_VERSION(11, 0, 4): + gfx_v11_0_update_gfx_clock_gating(adev, + state == AMD_CG_STATE_GATE); + break; diff --git a/queue-6.1/drm-amdgpu-enable-gfx-ip-v11.0.4-cg-support.patch b/queue-6.1/drm-amdgpu-enable-gfx-ip-v11.0.4-cg-support.patch new file mode 100644 index 00000000000..79b5825ab64 --- /dev/null +++ b/queue-6.1/drm-amdgpu-enable-gfx-ip-v11.0.4-cg-support.patch @@ -0,0 +1,47 @@ +From f2b91e5a7cc0368709964994ca253781b51a486a Mon Sep 17 00:00:00 2001 +From: Tim Huang +Date: Mon, 5 Dec 2022 11:24:37 +0800 +Subject: drm/amdgpu: enable GFX IP v11.0.4 CG support + +From: Tim Huang + +commit f2b91e5a7cc0368709964994ca253781b51a486a upstream. + +Add CG support for GFX/MC/HDP/ATHUB/IH/BIF. + +Signed-off-by: Tim Huang +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Cc: "Limonciello, Mario" +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/soc21.c | 18 +++++++++++++++++- + 1 file changed, 17 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/soc21.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc21.c +@@ -655,7 +655,23 @@ static int soc21_common_early_init(void + adev->external_rev_id = adev->rev_id + 0x20; + break; + case IP_VERSION(11, 0, 4): +- adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | ++ adev->cg_flags = ++ AMD_CG_SUPPORT_GFX_CGCG | ++ AMD_CG_SUPPORT_GFX_CGLS | ++ AMD_CG_SUPPORT_GFX_MGCG | ++ AMD_CG_SUPPORT_GFX_FGCG | ++ AMD_CG_SUPPORT_REPEATER_FGCG | ++ AMD_CG_SUPPORT_GFX_PERF_CLK | ++ AMD_CG_SUPPORT_MC_MGCG | ++ AMD_CG_SUPPORT_MC_LS | ++ AMD_CG_SUPPORT_HDP_MGCG | ++ AMD_CG_SUPPORT_HDP_LS | ++ AMD_CG_SUPPORT_ATHUB_MGCG | ++ AMD_CG_SUPPORT_ATHUB_LS | ++ AMD_CG_SUPPORT_IH_CG | ++ AMD_CG_SUPPORT_BIF_MGCG | ++ AMD_CG_SUPPORT_BIF_LS | ++ AMD_CG_SUPPORT_VCN_MGCG | + AMD_CG_SUPPORT_JPEG_MGCG; + adev->pg_flags = AMD_PG_SUPPORT_VCN | + AMD_PG_SUPPORT_VCN_DPG | diff --git a/queue-6.1/drm-amdgpu-enable-gfx-power-gating-for-gc-ip-v11.0.4.patch b/queue-6.1/drm-amdgpu-enable-gfx-power-gating-for-gc-ip-v11.0.4.patch new file mode 100644 index 00000000000..9020eff63e8 --- /dev/null +++ b/queue-6.1/drm-amdgpu-enable-gfx-power-gating-for-gc-ip-v11.0.4.patch @@ -0,0 +1,38 @@ +From a89e2965da6e644729a8ee9c318b7fa9a2990353 Mon Sep 17 00:00:00 2001 +From: Tim Huang +Date: Mon, 5 Dec 2022 13:55:36 +0800 +Subject: drm/amdgpu: enable GFX Power Gating for GC IP v11.0.4 + +From: Tim Huang + +commit a89e2965da6e644729a8ee9c318b7fa9a2990353 upstream. + +Enable GFX Power Gating control for GC IP v11.0.4. + +Signed-off-by: Tim Huang +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Cc: "Limonciello, Mario" +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +@@ -5030,6 +5030,7 @@ static void gfx_v11_cntl_power_gating(st + if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { + switch (adev->ip_versions[GC_HWIP][0]) { + case IP_VERSION(11, 0, 1): ++ case IP_VERSION(11, 0, 4): + WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); + break; + default: +@@ -5063,6 +5064,7 @@ static int gfx_v11_0_set_powergating_sta + amdgpu_gfx_off_ctrl(adev, enable); + break; + case IP_VERSION(11, 0, 1): ++ case IP_VERSION(11, 0, 4): + gfx_v11_cntl_pg(adev, enable); + amdgpu_gfx_off_ctrl(adev, enable); + break; diff --git a/queue-6.1/drm-amdgpu-enable-psp-ip-v13.0.11-support.patch b/queue-6.1/drm-amdgpu-enable-psp-ip-v13.0.11-support.patch new file mode 100644 index 00000000000..8d67b88c77f --- /dev/null +++ b/queue-6.1/drm-amdgpu-enable-psp-ip-v13.0.11-support.patch @@ -0,0 +1,51 @@ +From 2c83e3fd928b9cb1e35340e58d4b1bd2eea23ed6 Mon Sep 17 00:00:00 2001 +From: Tim Huang +Date: Mon, 21 Nov 2022 10:24:14 +0800 +Subject: drm/amdgpu: enable PSP IP v13.0.11 support + +From: Tim Huang + +commit 2c83e3fd928b9cb1e35340e58d4b1bd2eea23ed6 upstream. + +Enable PSP FW loading for PSP IP v13.0.11 + +Signed-off-by: Tim Huang +Signed-off-by: Yifan Zhang +Reviewed-by: Aaron Liu +Signed-off-by: Alex Deucher +Cc: "Limonciello, Mario" +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 + + drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 3 +++ + 2 files changed, 4 insertions(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +@@ -139,6 +139,7 @@ static int psp_early_init(void *handle) + case IP_VERSION(13, 0, 5): + case IP_VERSION(13, 0, 8): + case IP_VERSION(13, 0, 10): ++ case IP_VERSION(13, 0, 11): + psp_v13_0_set_psp_funcs(psp); + psp->autoload_supported = true; + break; +--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c +@@ -46,6 +46,8 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.b + MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin"); + MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin"); + MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin"); ++MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin"); ++MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin"); + + /* For large FW files the time to complete can be very long */ + #define USBC_PD_POLLING_LIMIT_S 240 +@@ -102,6 +104,7 @@ static int psp_v13_0_init_microcode(stru + case IP_VERSION(13, 0, 3): + case IP_VERSION(13, 0, 5): + case IP_VERSION(13, 0, 8): ++ case IP_VERSION(13, 0, 11): + err = psp_init_toc_microcode(psp, chip_name); + if (err) + return err; diff --git a/queue-6.1/drm-amdgpu-pm-add-gfxoff-control-ip-version-check-for-smu-ip-v13.0.11.patch b/queue-6.1/drm-amdgpu-pm-add-gfxoff-control-ip-version-check-for-smu-ip-v13.0.11.patch new file mode 100644 index 00000000000..906f18235c4 --- /dev/null +++ b/queue-6.1/drm-amdgpu-pm-add-gfxoff-control-ip-version-check-for-smu-ip-v13.0.11.patch @@ -0,0 +1,30 @@ +From 9f83e61201bb21957e4993736532edad7a11c7fa Mon Sep 17 00:00:00 2001 +From: Yifan Zhang +Date: Wed, 12 Oct 2022 13:17:40 +0800 +Subject: drm/amdgpu/pm: add GFXOFF control IP version check for SMU IP v13.0.11 + +From: Yifan Zhang + +commit 9f83e61201bb21957e4993736532edad7a11c7fa upstream. + +Enable the SMU IP v13.0.11 GFXOFF control + +Signed-off-by: Yifan Zhang +Reviewed-by: Aaron Liu +Signed-off-by: Alex Deucher +Cc: "Limonciello, Mario" +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +@@ -845,6 +845,7 @@ int smu_v13_0_gfx_off_control(struct smu + case IP_VERSION(13, 0, 7): + case IP_VERSION(13, 0, 8): + case IP_VERSION(13, 0, 10): ++ case IP_VERSION(13, 0, 11): + if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) + return 0; + if (enable) diff --git a/queue-6.1/drm-amdgpu-pm-enable-swsmu-for-smu-ip-v13.0.11.patch b/queue-6.1/drm-amdgpu-pm-enable-swsmu-for-smu-ip-v13.0.11.patch new file mode 100644 index 00000000000..fba253ac631 --- /dev/null +++ b/queue-6.1/drm-amdgpu-pm-enable-swsmu-for-smu-ip-v13.0.11.patch @@ -0,0 +1,30 @@ +From 16412a94364d1dcebded9217ecb693c9659eaabc Mon Sep 17 00:00:00 2001 +From: Yifan Zhang +Date: Wed, 12 Oct 2022 13:08:30 +0800 +Subject: drm/amdgpu/pm: enable swsmu for SMU IP v13.0.11 + +From: Yifan Zhang + +commit 16412a94364d1dcebded9217ecb693c9659eaabc upstream. + +Add the entry to set the ppt functions for SMU IP v13.0.11. + +Signed-off-by: Yifan Zhang +Reviewed-by: Aaron Liu +Signed-off-by: Alex Deucher +Cc: "Limonciello, Mario" +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +@@ -585,6 +585,7 @@ static int smu_set_funcs(struct amdgpu_d + yellow_carp_set_ppt_funcs(smu); + break; + case IP_VERSION(13, 0, 4): ++ case IP_VERSION(13, 0, 11): + smu_v13_0_4_set_ppt_funcs(smu); + break; + case IP_VERSION(13, 0, 5): diff --git a/queue-6.1/drm-amdgpu-pm-use-the-specific-mailbox-registers-only-for-smu-ip-v13.0.4.patch b/queue-6.1/drm-amdgpu-pm-use-the-specific-mailbox-registers-only-for-smu-ip-v13.0.4.patch new file mode 100644 index 00000000000..0ac38349f98 --- /dev/null +++ b/queue-6.1/drm-amdgpu-pm-use-the-specific-mailbox-registers-only-for-smu-ip-v13.0.4.patch @@ -0,0 +1,54 @@ +From 069a5af97ce3a1448a3566ce8b63b60e51e19958 Mon Sep 17 00:00:00 2001 +From: Tim Huang +Date: Mon, 24 Oct 2022 11:05:59 +0800 +Subject: drm/amdgpu/pm: use the specific mailbox registers only for SMU IP v13.0.4 + +From: Tim Huang + +commit 069a5af97ce3a1448a3566ce8b63b60e51e19958 upstream. + +The SMU IP v13.0.4 ppt interface is shared by IP v13.0.11, they use +the different mailbox register offset. So use the specific mailbox +registers offset for v13.0.4. + +Signed-off-by: Tim Huang +Signed-off-by: Yifan Zhang +Reviewed-by: Aaron Liu +Signed-off-by: Alex Deucher +Cc: "Limonciello, Mario" +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 17 ++++++++++++++--- + 1 file changed, 14 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c +@@ -1026,6 +1026,15 @@ static const struct pptable_funcs smu_v1 + .set_gfx_power_up_by_imu = smu_v13_0_set_gfx_power_up_by_imu, + }; + ++static void smu_v13_0_4_set_smu_mailbox_registers(struct smu_context *smu) ++{ ++ struct amdgpu_device *adev = smu->adev; ++ ++ smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); ++ smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); ++ smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); ++} ++ + void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu) + { + struct amdgpu_device *adev = smu->adev; +@@ -1035,7 +1044,9 @@ void smu_v13_0_4_set_ppt_funcs(struct sm + smu->feature_map = smu_v13_0_4_feature_mask_map; + smu->table_map = smu_v13_0_4_table_map; + smu->is_apu = true; +- smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); +- smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); +- smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); ++ ++ if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) ++ smu_v13_0_4_set_smu_mailbox_registers(smu); ++ else ++ smu_v13_0_set_smu_mailbox_registers(smu); + } diff --git a/queue-6.1/drm-amdgpu-set-gc-11.0.4-family.patch b/queue-6.1/drm-amdgpu-set-gc-11.0.4-family.patch new file mode 100644 index 00000000000..8e07fed6b2a --- /dev/null +++ b/queue-6.1/drm-amdgpu-set-gc-11.0.4-family.patch @@ -0,0 +1,30 @@ +From 94ab70685844227b5c9cb9027a5c4acd3b0e4564 Mon Sep 17 00:00:00 2001 +From: Yifan Zhang +Date: Wed, 12 Oct 2022 11:15:24 +0800 +Subject: drm/amdgpu: set GC 11.0.4 family + +From: Yifan Zhang + +commit 94ab70685844227b5c9cb9027a5c4acd3b0e4564 upstream. + +this patch is to set GC 11.0.4 family. + +Signed-off-by: Yifan Zhang +Reviewed-by: Aaron Liu +Signed-off-by: Alex Deucher +Cc: "Limonciello, Mario" +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +@@ -2181,6 +2181,7 @@ int amdgpu_discovery_set_ip_blocks(struc + adev->family = AMDGPU_FAMILY_GC_11_0_0; + break; + case IP_VERSION(11, 0, 1): ++ case IP_VERSION(11, 0, 4): + adev->family = AMDGPU_FAMILY_GC_11_0_1; + break; + default: diff --git a/queue-6.1/drm-amdgpu-soc21-add-mode2-asic-reset-for-smu-ip-v13.0.11.patch b/queue-6.1/drm-amdgpu-soc21-add-mode2-asic-reset-for-smu-ip-v13.0.11.patch new file mode 100644 index 00000000000..4cb5cf6b0fe --- /dev/null +++ b/queue-6.1/drm-amdgpu-soc21-add-mode2-asic-reset-for-smu-ip-v13.0.11.patch @@ -0,0 +1,31 @@ +From 18ad18853cf2d8b94cef0112ba94f7a7535a9e89 Mon Sep 17 00:00:00 2001 +From: Tim Huang +Date: Mon, 24 Oct 2022 10:32:05 +0800 +Subject: drm/amdgpu/soc21: add mode2 asic reset for SMU IP v13.0.11 + +From: Tim Huang + +commit 18ad18853cf2d8b94cef0112ba94f7a7535a9e89 upstream. + +Set the default reset method to mode2 for SMU IP v13.0.11 + +Signed-off-by: Tim Huang +Signed-off-by: Yifan Zhang +Reviewed-by: Aaron Liu +Signed-off-by: Alex Deucher +Cc: "Limonciello, Mario" +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/soc21.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/amdgpu/soc21.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc21.c +@@ -325,6 +325,7 @@ soc21_asic_reset_method(struct amdgpu_de + case IP_VERSION(13, 0, 10): + return AMD_RESET_METHOD_MODE1; + case IP_VERSION(13, 0, 4): ++ case IP_VERSION(13, 0, 11): + return AMD_RESET_METHOD_MODE2; + default: + if (amdgpu_dpm_is_baco_supported(adev)) diff --git a/queue-6.1/series b/queue-6.1/series index dc7814ce36c..7c18969ea19 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -158,3 +158,25 @@ docs-fix-path-paste-o-for-sys-kernel-warn_count.patch exit-use-read_once-for-all-oops-warn-limit-reads.patch x86-fpu-use-_alignof-to-avoid-undefined-behavior-in-type_align.patch arch-fix-broken-buildid-for-arm64-and-riscv.patch +drm-amdgpu-discovery-enable-soc21-common-for-gc-11.0.4.patch +drm-amdgpu-discovery-enable-gmc-v11-for-gc-11.0.4.patch +drm-amdgpu-discovery-enable-gfx-v11-for-gc-11.0.4.patch +drm-amdgpu-discovery-enable-mes-support-for-gc-v11.0.4.patch +drm-amdgpu-set-gc-11.0.4-family.patch +drm-amdgpu-discovery-set-the-apu-flag-for-gc-11.0.4.patch +drm-amdgpu-add-gfx-support-for-gc-11.0.4.patch +drm-amdgpu-add-gmc-v11-support-for-gc-11.0.4.patch +drm-amdgpu-discovery-add-psp-ip-v13.0.11-support.patch +drm-amdgpu-pm-enable-swsmu-for-smu-ip-v13.0.11.patch +drm-amdgpu-add-smu-13-support-for-smu-13.0.11.patch +drm-amdgpu-pm-add-gfxoff-control-ip-version-check-for-smu-ip-v13.0.11.patch +drm-amdgpu-soc21-add-mode2-asic-reset-for-smu-ip-v13.0.11.patch +drm-amdgpu-pm-use-the-specific-mailbox-registers-only-for-smu-ip-v13.0.4.patch +drm-amdgpu-discovery-enable-nbio-support-for-nbio-v7.7.1.patch +drm-amdgpu-enable-psp-ip-v13.0.11-support.patch +drm-amdgpu-enable-gfx-ip-v11.0.4-cg-support.patch +drm-amdgpu-enable-gfx-power-gating-for-gc-ip-v11.0.4.patch +drm-amdgpu-enable-gfx-clock-gating-control-for-gc-ip-v11.0.4.patch +drm-amdgpu-add-tmz-support-for-gc-11.0.1.patch +drm-amdgpu-add-tmz-support-for-gc-ip-v11.0.4.patch +drm-amdgpu-correct-mec-number-for-gfx11-apus.patch