From: Lorenzo Pieralisi <lpieralisi@kernel.org>
Date: Tue, 10 Jun 2025 12:09:35 +0000 (+0200)
Subject: docs: arm64: Fix ICC_SRE_EL2 register typo in booting.rst
X-Git-Tag: v6.16-rc3~20^2~3
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=c0c7fa4e7a512006710c8e4d6b6f7b40c9f786cd;p=thirdparty%2Fkernel%2Flinux.git

docs: arm64: Fix ICC_SRE_EL2 register typo in booting.rst

Fix trivial ICC_SRE_EL2 register spelling typo in booting.rst.

Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Will Deacon <will@kernel.org>
CC: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20250610120935.852034-1-lpieralisi@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
---

diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst
index dee7b6de864fc..ee9b790c0d72f 100644
--- a/Documentation/arch/arm64/booting.rst
+++ b/Documentation/arch/arm64/booting.rst
@@ -234,7 +234,7 @@ Before jumping into the kernel, the following conditions must be met:
 
   - If the kernel is entered at EL1:
 
-      - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
+      - ICC_SRE_EL2.Enable (bit 3) must be initialised to 0b1
       - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
 
   - The DT or ACPI tables must describe a GICv3 interrupt controller.