From: Nicolin Chen Date: Thu, 8 Oct 2020 00:37:42 +0000 (-0700) Subject: memory: tegra: Correct la.reg address of seswr X-Git-Tag: v5.11-rc1~90^2~21^2~35 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=c14bea053775e0c79a6fdd2d1b5a1d9de4fbd7c7;p=thirdparty%2Fkernel%2Flinux.git memory: tegra: Correct la.reg address of seswr According to Tegra X1 TRM, ALLOWANCE_SESWR is located in field [23:16] of register at address 0x3e0 with a reset value of 0x80 at register 0x3e0, while bit-1 of register 0xb98 is for enable bit of seswr. Signed-off-by: Nicolin Chen Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201008003746.25659-2-nicoleotsuka@gmail.com Signed-off-by: Krzysztof Kozlowski --- diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c index 7fb8b5438bf45..088814279616a 100644 --- a/drivers/memory/tegra/tegra210.c +++ b/drivers/memory/tegra/tegra210.c @@ -897,7 +897,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .bit = 1, }, .la = { - .reg = 0xb98, + .reg = 0x3e0, .shift = 16, .mask = 0xff, .def = 0x80,