From: Tomi Valkeinen Date: Wed, 25 Mar 2020 12:15:08 +0000 (+0100) Subject: media: ti-vpe: cal: improve wait for CIO resetdone X-Git-Tag: v5.8-rc1~162^2~374 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=c17013918a217cea51ecc4925953d640b0dc8858;p=thirdparty%2Fkernel%2Flinux.git media: ti-vpe: cal: improve wait for CIO resetdone Sometimes there is a timeout when waiting for the 'ComplexIO Reset Done'. Testing shows that sometimes we need to wait more than what the current code does. It is not clear how long this wait can be, but it is based on how quickly the sensor provides a valid clock, and how quickly CAL syncs to it. Change the code to make it more obvious how long we'll wait, and set a wider range for usleep_range. Increase the timeout to 750ms. Signed-off-by: Tomi Valkeinen Reviewed-by: Benoit Parrot Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 318b70ec452e4..38f1ae63f26a7 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -825,15 +825,16 @@ static void csi2_phy_init(struct cal_ctx *ctx) static void csi2_wait_complexio_reset(struct cal_ctx *ctx) { - int i; + unsigned long timeout; - for (i = 0; i < 250; i++) { + timeout = jiffies + msecs_to_jiffies(750); + while (time_before(jiffies, timeout)) { if (reg_read_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) == CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED) break; - usleep_range(1000, 1100); + usleep_range(500, 5000); } if (reg_read_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),