From: Jiaxun Yang Date: Wed, 12 Jun 2024 08:54:28 +0000 (+0100) Subject: MIPS: csrc-r4k: Refine rating computation X-Git-Tag: v6.11-rc1~95^2~26 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=c171186c177970d3ec22dd814f2693f1f7fc1e7d;p=thirdparty%2Fkernel%2Flinux.git MIPS: csrc-r4k: Refine rating computation Increase frequency addend dividend to 10000000 (10MHz) to reasonably accommodate multi GHz level mips_hpt_frequency. Cap rating of csrc-r4k into 299 to ensure it doesn't go into "Desired" range, given all the drama we have with CP0 count registers (SMP sync, behaviour on wait etc). Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c index edc4afc080faa..f02ae333f4f95 100644 --- a/arch/mips/kernel/csrc-r4k.c +++ b/arch/mips/kernel/csrc-r4k.c @@ -111,7 +111,8 @@ int __init init_r4k_clocksource(void) return -ENXIO; /* Calculate a somewhat reasonable rating value */ - clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; + clocksource_mips.rating = 200; + clocksource_mips.rating += clamp(mips_hpt_frequency / 10000000, 0, 99); /* * R2 onwards makes the count accessible to user mode so it can be used