From: Peter Maydell Date: Tue, 19 Aug 2025 14:56:58 +0000 (+0100) Subject: target/arm: Correct condition of aa64_atomics feature function X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=c2fae597099ef6ff81ca63d69ee28eddb982d894;p=thirdparty%2Fqemu.git target/arm: Correct condition of aa64_atomics feature function The ARMv8.1-Atomics feature (renamed FEAT_LSE in more modern versions of the Arm ARM) has always ben indicated by ID_AA64ISAR0.ATOMIC being 0b0010 or greater; 0b0001 is a reserved unused value. We were incorrectly checking for != 0; this had no harmful effects because all the CPUs set their value for this field to either 0 (for not having the feature) or 2 (if they do have it), but it's better to match what the architecture specifies here. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20250819145659.2165160-1-peter.maydell@linaro.org --- diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 41511d08350..d48754bcf27 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -408,7 +408,7 @@ static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id) static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id) { - return FIELD_EX64_IDREG(id, ID_AA64ISAR0, ATOMIC) != 0; + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, ATOMIC) >= 2; } static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)