From: Greg Kroah-Hartman Date: Thu, 8 Jun 2023 17:56:02 +0000 (+0200) Subject: drop loongarch-relay-bce-exceptions-to-userland-as-sigseg.patch from everywhere X-Git-Tag: v4.14.317~1 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=c4a33d1749fea5e29ab7e67ba78a46f011c07b9f;p=thirdparty%2Fkernel%2Fstable-queue.git drop loongarch-relay-bce-exceptions-to-userland-as-sigseg.patch from everywhere --- diff --git a/queue-6.1/loongarch-relay-bce-exceptions-to-userland-as-sigseg.patch b/queue-6.1/loongarch-relay-bce-exceptions-to-userland-as-sigseg.patch deleted file mode 100644 index e73a3a6e6b7..00000000000 --- a/queue-6.1/loongarch-relay-bce-exceptions-to-userland-as-sigseg.patch +++ /dev/null @@ -1,241 +0,0 @@ -From e3dfa110446fabe5e54ffce840033bc2b08eb12e Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 1 May 2023 17:19:27 +0800 -Subject: LoongArch: Relay BCE exceptions to userland as SIGSEGV with - si_code=SEGV_BNDERR - -From: WANG Xuerui - -[ Upstream commit c23e7f01cf621290770069d968ca4c8356a50d00 ] - -SEGV_BNDERR was introduced initially for supporting the Intel MPX, but -fell into disuse after the MPX support was removed. The LoongArch -bounds-checking instructions behave very differently than MPX, but -overall the interface is still kind of suitable for conveying the -information to userland when bounds-checking assertions trigger, so we -wouldn't have to invent more UAPI. Specifically, when the BCE triggers, -a SEGV_BNDERR is sent to userland, with si_addr set to the out-of-bounds -address or value (in asrt{gt,le}'s case), and one of si_lower or -si_upper set to the configured bound depending on the faulting -instruction. The other bound is set to either 0 or ULONG_MAX to resemble -a range with both lower and upper bounds. - -Note that it is possible to have si_addr == si_lower in case of a -failing asrtgt or {ld,st}gt, because those instructions test for strict -greater-than relationship. This should not pose a problem for userland, -though, because the faulting PC is available for the application to -associate back to the exact instruction for figuring out the -expectation. - -Example exception context generated by a faulting `asrtgt.d t0, t1` -(assert t0 > t1 or BCE) with t0=100 and t1=200: - -> pc 00005555558206a4 ra 00007ffff2d854fc tp 00007ffff2f2f180 sp 00007ffffbf9fb80 -> a0 0000000000000002 a1 00007ffffbf9fce8 a2 00007ffffbf9fd00 a3 00007ffff2ed4558 -> a4 0000000000000000 a5 00007ffff2f044c8 a6 00007ffffbf9fce0 a7 fffffffffffff000 -> t0 0000000000000064 t1 00000000000000c8 t2 00007ffffbfa2d5e t3 00007ffff2f12aa0 -> t4 00007ffff2ed6158 t5 00007ffff2ed6158 t6 000000000000002e t7 0000000003d8f538 -> t8 0000000000000005 u0 0000000000000000 s9 0000000000000000 s0 00007ffffbf9fce8 -> s1 0000000000000002 s2 0000000000000000 s3 00007ffff2f2c038 s4 0000555555820610 -> s5 00007ffff2ed5000 s6 0000555555827e38 s7 00007ffffbf9fd00 s8 0000555555827e38 -> ra: 00007ffff2d854fc -> ERA: 00005555558206a4 -> CRMD: 000000b0 (PLV0 -IE -DA +PG DACF=CC DACM=CC -WE) -> PRMD: 00000007 (PPLV3 +PIE -PWE) -> EUEN: 00000000 (-FPE -SXE -ASXE -BTE) -> ECFG: 0007181c (LIE=2-4,11-12 VS=7) -> ESTAT: 000a0000 [BCE] (IS= ECode=10 EsubCode=0) -> PRID: 0014c010 (Loongson-64bit, Loongson-3A5000) - -Signed-off-by: WANG Xuerui -Signed-off-by: Huacai Chen -Signed-off-by: Sasha Levin ---- - arch/loongarch/include/asm/inst.h | 26 +++++++++ - arch/loongarch/kernel/genex.S | 1 + - arch/loongarch/kernel/traps.c | 92 +++++++++++++++++++++++++++++++ - 3 files changed, 119 insertions(+) - -diff --git a/arch/loongarch/include/asm/inst.h b/arch/loongarch/include/asm/inst.h -index fce1843ceebb3..d476a88b9616c 100644 ---- a/arch/loongarch/include/asm/inst.h -+++ b/arch/loongarch/include/asm/inst.h -@@ -105,6 +105,8 @@ enum reg2bstrd_op { - }; - - enum reg3_op { -+ asrtle_op = 0x02, -+ asrtgt_op = 0x03, - addw_op = 0x20, - addd_op = 0x21, - subw_op = 0x22, -@@ -156,6 +158,30 @@ enum reg3_op { - amord_op = 0x70c7, - amxorw_op = 0x70c8, - amxord_op = 0x70c9, -+ fldgts_op = 0x70e8, -+ fldgtd_op = 0x70e9, -+ fldles_op = 0x70ea, -+ fldled_op = 0x70eb, -+ fstgts_op = 0x70ec, -+ fstgtd_op = 0x70ed, -+ fstles_op = 0x70ee, -+ fstled_op = 0x70ef, -+ ldgtb_op = 0x70f0, -+ ldgth_op = 0x70f1, -+ ldgtw_op = 0x70f2, -+ ldgtd_op = 0x70f3, -+ ldleb_op = 0x70f4, -+ ldleh_op = 0x70f5, -+ ldlew_op = 0x70f6, -+ ldled_op = 0x70f7, -+ stgtb_op = 0x70f8, -+ stgth_op = 0x70f9, -+ stgtw_op = 0x70fa, -+ stgtd_op = 0x70fb, -+ stleb_op = 0x70fc, -+ stleh_op = 0x70fd, -+ stlew_op = 0x70fe, -+ stled_op = 0x70ff, - }; - - enum reg3sa2_op { -diff --git a/arch/loongarch/kernel/genex.S b/arch/loongarch/kernel/genex.S -index 75e5be807a0d5..42ff28eadf04d 100644 ---- a/arch/loongarch/kernel/genex.S -+++ b/arch/loongarch/kernel/genex.S -@@ -79,6 +79,7 @@ SYM_FUNC_END(except_vec_cex) - - BUILD_HANDLER ade ade badv - BUILD_HANDLER ale ale badv -+ BUILD_HANDLER bce bce none - BUILD_HANDLER bp bp none - BUILD_HANDLER fpe fpe fcsr - BUILD_HANDLER fpu fpu none -diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c -index 1a4dce84ebc60..5d5ae11d9f67e 100644 ---- a/arch/loongarch/kernel/traps.c -+++ b/arch/loongarch/kernel/traps.c -@@ -35,6 +35,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -50,6 +51,7 @@ - - extern asmlinkage void handle_ade(void); - extern asmlinkage void handle_ale(void); -+extern asmlinkage void handle_bce(void); - extern asmlinkage void handle_sys(void); - extern asmlinkage void handle_bp(void); - extern asmlinkage void handle_ri(void); -@@ -401,6 +403,95 @@ static void bug_handler(struct pt_regs *regs) - } - } - -+asmlinkage void noinstr do_bce(struct pt_regs *regs) -+{ -+ bool user = user_mode(regs); -+ unsigned long era = exception_era(regs); -+ u64 badv = 0, lower = 0, upper = ULONG_MAX; -+ union loongarch_instruction insn; -+ irqentry_state_t state = irqentry_enter(regs); -+ -+ if (regs->csr_prmd & CSR_PRMD_PIE) -+ local_irq_enable(); -+ -+ current->thread.trap_nr = read_csr_excode(); -+ -+ die_if_kernel("Bounds check error in kernel code", regs); -+ -+ /* -+ * Pull out the address that failed bounds checking, and the lower / -+ * upper bound, by minimally looking at the faulting instruction word -+ * and reading from the correct register. -+ */ -+ if (__get_inst(&insn.word, (u32 *)era, user)) -+ goto bad_era; -+ -+ switch (insn.reg3_format.opcode) { -+ case asrtle_op: -+ if (insn.reg3_format.rd != 0) -+ break; /* not asrtle */ -+ badv = regs->regs[insn.reg3_format.rj]; -+ upper = regs->regs[insn.reg3_format.rk]; -+ break; -+ -+ case asrtgt_op: -+ if (insn.reg3_format.rd != 0) -+ break; /* not asrtgt */ -+ badv = regs->regs[insn.reg3_format.rj]; -+ lower = regs->regs[insn.reg3_format.rk]; -+ break; -+ -+ case ldleb_op: -+ case ldleh_op: -+ case ldlew_op: -+ case ldled_op: -+ case stleb_op: -+ case stleh_op: -+ case stlew_op: -+ case stled_op: -+ case fldles_op: -+ case fldled_op: -+ case fstles_op: -+ case fstled_op: -+ badv = regs->regs[insn.reg3_format.rj]; -+ upper = regs->regs[insn.reg3_format.rk]; -+ break; -+ -+ case ldgtb_op: -+ case ldgth_op: -+ case ldgtw_op: -+ case ldgtd_op: -+ case stgtb_op: -+ case stgth_op: -+ case stgtw_op: -+ case stgtd_op: -+ case fldgts_op: -+ case fldgtd_op: -+ case fstgts_op: -+ case fstgtd_op: -+ badv = regs->regs[insn.reg3_format.rj]; -+ lower = regs->regs[insn.reg3_format.rk]; -+ break; -+ } -+ -+ force_sig_bnderr((void __user *)badv, (void __user *)lower, (void __user *)upper); -+ -+out: -+ if (regs->csr_prmd & CSR_PRMD_PIE) -+ local_irq_disable(); -+ -+ irqentry_exit(regs, state); -+ return; -+ -+bad_era: -+ /* -+ * Cannot pull out the instruction word, hence cannot provide more -+ * info than a regular SIGSEGV in this case. -+ */ -+ force_sig(SIGSEGV); -+ goto out; -+} -+ - asmlinkage void noinstr do_bp(struct pt_regs *regs) - { - bool user = user_mode(regs); -@@ -721,6 +812,7 @@ void __init trap_init(void) - - set_handler(EXCCODE_ADE * VECSIZE, handle_ade, VECSIZE); - set_handler(EXCCODE_ALE * VECSIZE, handle_ale, VECSIZE); -+ set_handler(EXCCODE_BCE * VECSIZE, handle_bce, VECSIZE); - set_handler(EXCCODE_SYS * VECSIZE, handle_sys, VECSIZE); - set_handler(EXCCODE_BP * VECSIZE, handle_bp, VECSIZE); - set_handler(EXCCODE_INE * VECSIZE, handle_ri, VECSIZE); --- -2.39.2 - diff --git a/queue-6.1/series b/queue-6.1/series index e1e960db4c1..89499b7e052 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -60,7 +60,6 @@ mptcp-add-annotations-around-sk-sk_shutdown-accesses.patch drm-amdgpu-release-gpu-full-access-after-amdgpu_devi.patch watchdog-menz069_wdt-fix-watchdog-initialisation.patch alsa-hda-glenfly-add-hd-audio-pci-ids-and-hdmi-codec.patch -loongarch-relay-bce-exceptions-to-userland-as-sigseg.patch asoc-intel-soc-acpi-cht-add-quirk-for-nextbook-ares-.patch drm-amdgpu-use-the-default-reset-when-loading-or-rel.patch mailbox-mailbox-test-fix-potential-double-free-in-mb.patch diff --git a/queue-6.3/loongarch-relay-bce-exceptions-to-userland-as-sigseg.patch b/queue-6.3/loongarch-relay-bce-exceptions-to-userland-as-sigseg.patch deleted file mode 100644 index 4fe2ee6e4bd..00000000000 --- a/queue-6.3/loongarch-relay-bce-exceptions-to-userland-as-sigseg.patch +++ /dev/null @@ -1,241 +0,0 @@ -From 66fc814a147e718b7f74fc0ed6e5ecf7638b80c5 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Mon, 1 May 2023 17:19:27 +0800 -Subject: LoongArch: Relay BCE exceptions to userland as SIGSEGV with - si_code=SEGV_BNDERR - -From: WANG Xuerui - -[ Upstream commit c23e7f01cf621290770069d968ca4c8356a50d00 ] - -SEGV_BNDERR was introduced initially for supporting the Intel MPX, but -fell into disuse after the MPX support was removed. The LoongArch -bounds-checking instructions behave very differently than MPX, but -overall the interface is still kind of suitable for conveying the -information to userland when bounds-checking assertions trigger, so we -wouldn't have to invent more UAPI. Specifically, when the BCE triggers, -a SEGV_BNDERR is sent to userland, with si_addr set to the out-of-bounds -address or value (in asrt{gt,le}'s case), and one of si_lower or -si_upper set to the configured bound depending on the faulting -instruction. The other bound is set to either 0 or ULONG_MAX to resemble -a range with both lower and upper bounds. - -Note that it is possible to have si_addr == si_lower in case of a -failing asrtgt or {ld,st}gt, because those instructions test for strict -greater-than relationship. This should not pose a problem for userland, -though, because the faulting PC is available for the application to -associate back to the exact instruction for figuring out the -expectation. - -Example exception context generated by a faulting `asrtgt.d t0, t1` -(assert t0 > t1 or BCE) with t0=100 and t1=200: - -> pc 00005555558206a4 ra 00007ffff2d854fc tp 00007ffff2f2f180 sp 00007ffffbf9fb80 -> a0 0000000000000002 a1 00007ffffbf9fce8 a2 00007ffffbf9fd00 a3 00007ffff2ed4558 -> a4 0000000000000000 a5 00007ffff2f044c8 a6 00007ffffbf9fce0 a7 fffffffffffff000 -> t0 0000000000000064 t1 00000000000000c8 t2 00007ffffbfa2d5e t3 00007ffff2f12aa0 -> t4 00007ffff2ed6158 t5 00007ffff2ed6158 t6 000000000000002e t7 0000000003d8f538 -> t8 0000000000000005 u0 0000000000000000 s9 0000000000000000 s0 00007ffffbf9fce8 -> s1 0000000000000002 s2 0000000000000000 s3 00007ffff2f2c038 s4 0000555555820610 -> s5 00007ffff2ed5000 s6 0000555555827e38 s7 00007ffffbf9fd00 s8 0000555555827e38 -> ra: 00007ffff2d854fc -> ERA: 00005555558206a4 -> CRMD: 000000b0 (PLV0 -IE -DA +PG DACF=CC DACM=CC -WE) -> PRMD: 00000007 (PPLV3 +PIE -PWE) -> EUEN: 00000000 (-FPE -SXE -ASXE -BTE) -> ECFG: 0007181c (LIE=2-4,11-12 VS=7) -> ESTAT: 000a0000 [BCE] (IS= ECode=10 EsubCode=0) -> PRID: 0014c010 (Loongson-64bit, Loongson-3A5000) - -Signed-off-by: WANG Xuerui -Signed-off-by: Huacai Chen -Signed-off-by: Sasha Levin ---- - arch/loongarch/include/asm/inst.h | 26 +++++++++ - arch/loongarch/kernel/genex.S | 1 + - arch/loongarch/kernel/traps.c | 92 +++++++++++++++++++++++++++++++ - 3 files changed, 119 insertions(+) - -diff --git a/arch/loongarch/include/asm/inst.h b/arch/loongarch/include/asm/inst.h -index a04fe755d7193..b09887ffcd15d 100644 ---- a/arch/loongarch/include/asm/inst.h -+++ b/arch/loongarch/include/asm/inst.h -@@ -121,6 +121,8 @@ enum reg2bstrd_op { - }; - - enum reg3_op { -+ asrtle_op = 0x02, -+ asrtgt_op = 0x03, - addw_op = 0x20, - addd_op = 0x21, - subw_op = 0x22, -@@ -176,6 +178,30 @@ enum reg3_op { - amord_op = 0x70c7, - amxorw_op = 0x70c8, - amxord_op = 0x70c9, -+ fldgts_op = 0x70e8, -+ fldgtd_op = 0x70e9, -+ fldles_op = 0x70ea, -+ fldled_op = 0x70eb, -+ fstgts_op = 0x70ec, -+ fstgtd_op = 0x70ed, -+ fstles_op = 0x70ee, -+ fstled_op = 0x70ef, -+ ldgtb_op = 0x70f0, -+ ldgth_op = 0x70f1, -+ ldgtw_op = 0x70f2, -+ ldgtd_op = 0x70f3, -+ ldleb_op = 0x70f4, -+ ldleh_op = 0x70f5, -+ ldlew_op = 0x70f6, -+ ldled_op = 0x70f7, -+ stgtb_op = 0x70f8, -+ stgth_op = 0x70f9, -+ stgtw_op = 0x70fa, -+ stgtd_op = 0x70fb, -+ stleb_op = 0x70fc, -+ stleh_op = 0x70fd, -+ stlew_op = 0x70fe, -+ stled_op = 0x70ff, - }; - - enum reg3sa2_op { -diff --git a/arch/loongarch/kernel/genex.S b/arch/loongarch/kernel/genex.S -index 44ff1ff642601..78f0663846575 100644 ---- a/arch/loongarch/kernel/genex.S -+++ b/arch/loongarch/kernel/genex.S -@@ -82,6 +82,7 @@ SYM_FUNC_END(except_vec_cex) - - BUILD_HANDLER ade ade badv - BUILD_HANDLER ale ale badv -+ BUILD_HANDLER bce bce none - BUILD_HANDLER bp bp none - BUILD_HANDLER fpe fpe fcsr - BUILD_HANDLER fpu fpu none -diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c -index de8ebe20b666c..03ebfd2a4392f 100644 ---- a/arch/loongarch/kernel/traps.c -+++ b/arch/loongarch/kernel/traps.c -@@ -35,6 +35,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -50,6 +51,7 @@ - - extern asmlinkage void handle_ade(void); - extern asmlinkage void handle_ale(void); -+extern asmlinkage void handle_bce(void); - extern asmlinkage void handle_sys(void); - extern asmlinkage void handle_bp(void); - extern asmlinkage void handle_ri(void); -@@ -430,6 +432,95 @@ static void bug_handler(struct pt_regs *regs) - } - } - -+asmlinkage void noinstr do_bce(struct pt_regs *regs) -+{ -+ bool user = user_mode(regs); -+ unsigned long era = exception_era(regs); -+ u64 badv = 0, lower = 0, upper = ULONG_MAX; -+ union loongarch_instruction insn; -+ irqentry_state_t state = irqentry_enter(regs); -+ -+ if (regs->csr_prmd & CSR_PRMD_PIE) -+ local_irq_enable(); -+ -+ current->thread.trap_nr = read_csr_excode(); -+ -+ die_if_kernel("Bounds check error in kernel code", regs); -+ -+ /* -+ * Pull out the address that failed bounds checking, and the lower / -+ * upper bound, by minimally looking at the faulting instruction word -+ * and reading from the correct register. -+ */ -+ if (__get_inst(&insn.word, (u32 *)era, user)) -+ goto bad_era; -+ -+ switch (insn.reg3_format.opcode) { -+ case asrtle_op: -+ if (insn.reg3_format.rd != 0) -+ break; /* not asrtle */ -+ badv = regs->regs[insn.reg3_format.rj]; -+ upper = regs->regs[insn.reg3_format.rk]; -+ break; -+ -+ case asrtgt_op: -+ if (insn.reg3_format.rd != 0) -+ break; /* not asrtgt */ -+ badv = regs->regs[insn.reg3_format.rj]; -+ lower = regs->regs[insn.reg3_format.rk]; -+ break; -+ -+ case ldleb_op: -+ case ldleh_op: -+ case ldlew_op: -+ case ldled_op: -+ case stleb_op: -+ case stleh_op: -+ case stlew_op: -+ case stled_op: -+ case fldles_op: -+ case fldled_op: -+ case fstles_op: -+ case fstled_op: -+ badv = regs->regs[insn.reg3_format.rj]; -+ upper = regs->regs[insn.reg3_format.rk]; -+ break; -+ -+ case ldgtb_op: -+ case ldgth_op: -+ case ldgtw_op: -+ case ldgtd_op: -+ case stgtb_op: -+ case stgth_op: -+ case stgtw_op: -+ case stgtd_op: -+ case fldgts_op: -+ case fldgtd_op: -+ case fstgts_op: -+ case fstgtd_op: -+ badv = regs->regs[insn.reg3_format.rj]; -+ lower = regs->regs[insn.reg3_format.rk]; -+ break; -+ } -+ -+ force_sig_bnderr((void __user *)badv, (void __user *)lower, (void __user *)upper); -+ -+out: -+ if (regs->csr_prmd & CSR_PRMD_PIE) -+ local_irq_disable(); -+ -+ irqentry_exit(regs, state); -+ return; -+ -+bad_era: -+ /* -+ * Cannot pull out the instruction word, hence cannot provide more -+ * info than a regular SIGSEGV in this case. -+ */ -+ force_sig(SIGSEGV); -+ goto out; -+} -+ - asmlinkage void noinstr do_bp(struct pt_regs *regs) - { - bool user = user_mode(regs); -@@ -797,6 +888,7 @@ void __init trap_init(void) - - set_handler(EXCCODE_ADE * VECSIZE, handle_ade, VECSIZE); - set_handler(EXCCODE_ALE * VECSIZE, handle_ale, VECSIZE); -+ set_handler(EXCCODE_BCE * VECSIZE, handle_bce, VECSIZE); - set_handler(EXCCODE_SYS * VECSIZE, handle_sys, VECSIZE); - set_handler(EXCCODE_BP * VECSIZE, handle_bp, VECSIZE); - set_handler(EXCCODE_INE * VECSIZE, handle_ri, VECSIZE); --- -2.39.2 - diff --git a/queue-6.3/misc-fastrpc-reassign-memory-ownership-only-for-remote-heap.patch b/queue-6.3/misc-fastrpc-reassign-memory-ownership-only-for-remote-heap.patch index 9d3792ec13b..a985a3f737a 100644 --- a/queue-6.3/misc-fastrpc-reassign-memory-ownership-only-for-remote-heap.patch +++ b/queue-6.3/misc-fastrpc-reassign-memory-ownership-only-for-remote-heap.patch @@ -28,14 +28,12 @@ Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20230523152550.438363-3-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman --- - drivers/misc/fastrpc.c | 2 +- + drivers/misc/fastrpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c -index 32a5415624bf..a654dc416480 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c -@@ -1904,7 +1904,7 @@ static int fastrpc_req_mmap(struct fastrpc_user *fl, char __user *argp) +@@ -1892,7 +1892,7 @@ static int fastrpc_req_mmap(struct fastr req.vaddrout = rsp_msg.vaddr; /* Add memory to static PD pool, protection thru hypervisor */ @@ -44,6 +42,3 @@ index 32a5415624bf..a654dc416480 100644 struct qcom_scm_vmperm perm; perm.vmid = QCOM_SCM_VMID_HLOS; --- -2.41.0 - diff --git a/queue-6.3/series b/queue-6.3/series index b169ef6ae76..ab6639ecd5c 100644 --- a/queue-6.3/series +++ b/queue-6.3/series @@ -86,7 +86,6 @@ drm-amdgpu-release-gpu-full-access-after-amdgpu_devi.patch watchdog-menz069_wdt-fix-watchdog-initialisation.patch alsa-hda-glenfly-add-hd-audio-pci-ids-and-hdmi-codec.patch drm-amd-display-fix-memleak-in-aconnector-timing_req.patch -loongarch-relay-bce-exceptions-to-userland-as-sigseg.patch loongarch-add-arch_has_fortify_source-selection.patch asoc-intel-soc-acpi-cht-add-quirk-for-nextbook-ares-.patch drm-amdgpu-use-the-default-reset-when-loading-or-rel.patch