From: Michal Simek Date: Tue, 25 Jun 2019 13:52:15 +0000 (+0200) Subject: arm64: versal: Add description for a2197-p x-prc-05 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=c532ac554c379b024f07c0806a232b76f3b33db1;p=thirdparty%2Fu-boot.git arm64: versal: Add description for a2197-p x-prc-05 Description is done without schematics only based on spec. It needs to be validated when HW is ready. Signed-off-by: Michal Simek --- diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ea12d88b6ad..29664f6ae98 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -174,6 +174,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-a2197-p-revA-x-prc-02-revA.dtbo \ zynqmp-a2197-p-revA-x-prc-03-revA.dtbo \ zynqmp-a2197-p-revA-x-prc-04-revA.dtbo \ + zynqmp-a2197-p-revA-x-prc-05-revA.dtbo \ zynqmp-mini.dtb \ zynqmp-mini-emmc0.dtb \ zynqmp-mini-emmc1.dtb \ @@ -222,6 +223,7 @@ dtb-$(CONFIG_ARCH_VERSAL) += \ versal-vc-p-a2197-00-revA-x-prc-03-revA.dtb \ versal-vc-p-a2197-00-revA-x-prc-04-revA.dtb \ versal-vc-p-a2197-00-revA-x-prc-04-revA-ospi.dtb \ + versal-vc-p-a2197-00-revA-x-prc-05-revA.dtb \ versal-vc-d-d1760-01-revA.dtb dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \ zynqmp-r5.dtb diff --git a/arch/arm/dts/versal-vc-p-a2197-00-revA-x-prc-05-revA.dts b/arch/arm/dts/versal-vc-p-a2197-00-revA-x-prc-05-revA.dts new file mode 100644 index 00000000000..a5d40b61164 --- /dev/null +++ b/arch/arm/dts/versal-vc-p-a2197-00-revA-x-prc-05-revA.dts @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal X-PRC-05 revA (SE5) + * + * (C) Copyright 2019, Xilinx, Inc. + * + * Michal Simek + */ + +#include "versal-vc-p-a2197-00-revA.dts" + +/ { + chosen { + bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; + stdout-path = "serial0:115200"; + }; + + aliases { + serial0 = &serial0; + ethernet0 = &gem0; + ethernet1 = &gem1; + i2c0 = &i2c0; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + gpio0 = &gpio; + spi0 = &qspi; + usb0 = &usb0; + }; +}; + +&gem0 { + status = "okay"; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + phy1: phy@1 { /* 88e1510 */ + reg = <1>; /* FIXME */ + }; + phy2: phy@2 { /* VSC8531 */ + reg = <2>; /* FIXME */ + }; +}; + +&gem1 { + status = "okay"; + phy-handle = <&phy2>; + phy-mode = "rgmii-id"; +}; + +&gpio { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + eeprom_versal: eeprom@51 { + compatible = "st,24c128", "atmel,24c128"; + reg = <0x51>; + }; +}; + +&qspi { + status = "okay"; + num-cs = <0x1>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + + flash@0 { /* MX25U12835 128Mbit */ + compatible = "m25p80", "spi-flash"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <104000000>; + }; +}; + +&sdhci0 { /* emmc0 */ + status = "okay"; + non-removable; + disable-wp; + bus-width = <8>; + xlnx,mio_bank = <0>; /* FIXME */ +}; + +&sdhci1 { /* connector */ + status = "okay"; + xlnx,mio_bank = <1>; /* FIXME */ + no-1-8-v; +}; + +&serial0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + xlnx,usb-polarity = <0>; + xlnx,usb-reset-mode = <0>; +}; + +&dwc3_0 { /* USB 2.0 host */ + status = "okay"; + dr_mode = "host"; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,usb3_lpm_capable; + phy-names = "usb3-phy"; +}; diff --git a/arch/arm/dts/zynqmp-a2197-p-revA-x-prc-05-revA.dts b/arch/arm/dts/zynqmp-a2197-p-revA-x-prc-05-revA.dts new file mode 100644 index 00000000000..c79ea197060 --- /dev/null +++ b/arch/arm/dts/zynqmp-a2197-p-revA-x-prc-05-revA.dts @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5) + * + * (C) Copyright 2019, Xilinx, Inc. + * + * Michal Simek + */ + +/dts-v1/; +/plugin/; + +/{ + compatible = "xlnx,zynqmp-x-prc-05-revA", "xlnx,zynqmp-x-prc-05"; + + fragment@0 { + target = <&dc_i2c>; + + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + x_prc_eeprom: eeprom@52 { /* u120 */ + compatible = "atmel,24c02"; + reg = <0x52>; + }; + + x_prc_tca9534: gpio@22 { /* u121 tca9534 */ + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; /* IRQ not connected */ + #gpio-cells = <2>; + gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", + "", "", "", ""; + gtr_sel0 { + gpio-hog; + gpios = <0 0>; + input; /* FIXME add meaning */ + line-name = "sw4_1"; + }; + gtr_sel1 { + gpio-hog; + gpios = <1 0>; + input; /* FIXME add meaning */ + line-name = "sw4_2"; + }; + gtr_sel2 { + gpio-hog; + gpios = <2 0>; + input; /* FIXME add meaning */ + line-name = "sw4_3"; + }; + gtr_sel3 { + gpio-hog; + gpios = <3 0>; + input; /* FIXME add meaning */ + line-name = "sw4_4"; + }; + }; + + si570_gem_tsu: clock-generator@5d { /* u164 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; /* FIXME */ + clock-frequency = <300000000>; + clock-output-names = "si570_gem_tsu_clk"; + }; + }; + }; + + fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + eeprom_versal: eeprom@51 { /* u153 */ + compatible = "atmel,24c02"; + reg = <0x51>; + }; + }; + }; +}; diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index e106ffb1438..a10b484a879 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -46,7 +46,7 @@ CONFIG_EFI_PARTITION=y # CONFIG_PARTITION_UUIDS is not set CONFIG_OF_BOARD=y CONFIG_DEFAULT_DEVICE_TREE="versal-vc-p-a2197-00-revA-x-prc-01-revA" -CONFIG_OF_LIST="versal-vc-p-a2197-00-revA-x-prc-01-revA versal-vc-p-a2197-00-revA-x-prc-01-revA-ospi versal-vc-p-a2197-00-revA-x-prc-02-revA versal-vc-p-a2197-00-revA-x-prc-03-revA versal-vc-p-a2197-00-revA-x-prc-04-revA versal-vc-p-a2197-00-revA-x-prc-04-revA-ospi versal-vc-d-d1760-01-revA" +CONFIG_OF_LIST="versal-vc-p-a2197-00-revA-x-prc-01-revA versal-vc-p-a2197-00-revA-x-prc-01-revA-ospi versal-vc-p-a2197-00-revA-x-prc-02-revA versal-vc-p-a2197-00-revA-x-prc-03-revA versal-vc-p-a2197-00-revA-x-prc-04-revA versal-vc-p-a2197-00-revA-x-prc-04-revA-ospi versal-vc-p-a2197-00-revA-x-prc-05-revA versal-vc-d-d1760-01-revA" CONFIG_MULTI_DTB_FIT=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y