From: Unnathi Chalicheemala Date: Fri, 31 May 2024 16:45:26 +0000 (-0700) Subject: arm64: dts: qcom: sm8450: Add Broadcast_AND register in LLCC block X-Git-Tag: v6.11-rc1~188^2~8^2~157 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=c566143137aaacfed1af09d8710edab1971c312d;p=thirdparty%2Flinux.git arm64: dts: qcom: sm8450: Add Broadcast_AND register in LLCC block Chipsets before SM8450 have only one broadcast register (Broadcast_OR) which is used to broadcast writes and check for status bit 0 only in all channels. >From SM8450 onwards, a new Broadcast_AND region was added which checks for status bit 1. This hasn't been updated and Broadcast_OR region was wrongly being used to check for status bit 1 all along. Hence mapping Broadcast_AND region's address space to LLCC in SM8450. Signed-off-by: Unnathi Chalicheemala Link: https://lore.kernel.org/r/bfc817da4188abdf5b543bedafb9cb0eb82806c2.1717014052.git.quic_uchalich@quicinc.com Signed-off-by: Bjorn Andersson --- diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index fe9cb08042859..216f4f7036433 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -4461,9 +4461,10 @@ compatible = "qcom,sm8450-llcc"; reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, - <0 0x19a00000 0 0x80000>; + <0 0x19a00000 0 0x80000>, <0 0x19c00000 0 0x80000>; reg-names = "llcc0_base", "llcc1_base", "llcc2_base", - "llcc3_base", "llcc_broadcast_base"; + "llcc3_base", "llcc_broadcast_base", + "llcc_broadcast_and_base"; interrupts = ; };