From: Stephen Boyd Date: Wed, 6 Nov 2024 21:40:12 +0000 (-0800) Subject: Merge tag 'clk-meson-v6.13-1' of https://github.com/BayLibre/clk-meson into clk-amlogic X-Git-Tag: v6.13-rc1~110^2~1^5~1 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=c601478bf02e124744308bca3618e07ad8a8208d;p=thirdparty%2Fkernel%2Flinux.git Merge tag 'clk-meson-v6.13-1' of https://github.com/BayLibre/clk-meson into clk-amlogic Pull Amlogic clk driver updates from Jerome Brunet: - Fix hifi_pll rate calculation on Amlogic s4 and c3 - Move audio reset implementation from the Amlogic axg-audio clock controller driver to the reset directory, using the auxiliary device bus - Remove the unnecessary spinlock in the Amlogic mpll driver - Fix Amlogic meson8 clock controller DT bindings * tag 'clk-meson-v6.13-1' of https://github.com/BayLibre/clk-meson: clk: amlogic: axg-audio: use the auxiliary reset driver reset: amlogic: Fix small whitespace issue reset: amlogic: add auxiliary reset driver support reset: amlogic: split the device core and platform probe reset: amlogic: move drivers to a dedicated directory reset: amlogic: add reset status support reset: amlogic: use reset number instead of register count reset: amlogic: add driver parameters reset: amlogic: make parameters unsigned reset: amlogic: use generic data matching function reset: amlogic: convert driver to regmap dt-bindings: clock: convert amlogic,meson8b-clkc.txt to dtschema clk: meson: meson8b: remove spinlock clk: meson: mpll: Delete a useless spinlock from the MPLL clk: meson: s4: pll: fix frac maximum value for hifi_pll clk: meson: c3: pll: fix frac maximum value for hifi_pll clk: meson: Support PLL with fixed fractional denominators clk: meson: s4: pll: hifi_pll support fractional multiplier --- c601478bf02e124744308bca3618e07ad8a8208d