From: Dharma Balasubiramani Date: Mon, 15 Sep 2025 09:13:57 +0000 (+0530) Subject: ARM: dts: microchip: sam9x7: Add qspi controller X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=c656932c3ece3eebe6240bb20e5c1d8aa0d7ecb0;p=thirdparty%2Fkernel%2Fstable.git ARM: dts: microchip: sam9x7: Add qspi controller Add support for QSPI controller. Signed-off-by: Dharma Balasubiramani Link: https://lore.kernel.org/r/20250915-sam9x7-qspi-dtsi-v1-1-1cc9adba7573@microchip.com Signed-off-by: Nicolas Ferre --- diff --git a/arch/arm/boot/dts/microchip/sam9x7.dtsi b/arch/arm/boot/dts/microchip/sam9x7.dtsi index 66c07e642c3e1..46dacbbd201dd 100644 --- a/arch/arm/boot/dts/microchip/sam9x7.dtsi +++ b/arch/arm/boot/dts/microchip/sam9x7.dtsi @@ -271,6 +271,27 @@ status = "disabled"; }; + qspi: spi@f0014000 { + compatible = "microchip,sam9x7-ospi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xf0014000 0x100>, <0x60000000 0x20000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(26))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(27))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>; + clock-names = "pclk", "gclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 35>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_PLLADIV2>; + status = "disabled"; + }; + i2s: i2s@f001c000 { compatible = "microchip,sam9x7-i2smcc", "microchip,sam9x60-i2smcc"; reg = <0xf001c000 0x100>;