From: Chen Wang <unicorn_wang@outlook.com>
Date: Mon, 20 Oct 2025 03:39:22 +0000 (+0800)
Subject: riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=c6c215099e89b1eb71ed6592163ae5b530f4538e;p=thirdparty%2Fkernel%2Fstable.git

riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X

Enable PCIe controllers for Sophgo SG2042_EVB_V1.X board,
which uses SG2042 SoC.

Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/1ad96631cc9d9d7403a2bed5585d856fa101a2ef.1760929111.git.unicorn_wang@outlook.com
Tested-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
---

diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
index 3320bc1dd2c6..a186d036cf36 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
@@ -164,6 +164,18 @@
 	};
 };
 
+&pcie_rc0 {
+	status = "okay";
+};
+
+&pcie_rc1 {
+	status = "okay";
+};
+
+&pcie_rc2 {
+	status = "okay";
+};
+
 &pinctrl {
 	emmc_cfg: sdhci-emmc-cfg {
 		sdhci-emmc-wp-pins {