From: Greg Kroah-Hartman Date: Sat, 15 Apr 2023 18:42:14 +0000 (+0200) Subject: 5.10-stable patches X-Git-Tag: v4.14.313~52 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=c7a50de2de512abcbe412921cb54810c8859c7a2;p=thirdparty%2Fkernel%2Fstable-queue.git 5.10-stable patches added patches: drm-i915-dsi-fix-dss-ctl-register-offsets-for-tgl.patch --- diff --git a/queue-5.10/drm-i915-dsi-fix-dss-ctl-register-offsets-for-tgl.patch b/queue-5.10/drm-i915-dsi-fix-dss-ctl-register-offsets-for-tgl.patch new file mode 100644 index 00000000000..9fe1ce07325 --- /dev/null +++ b/queue-5.10/drm-i915-dsi-fix-dss-ctl-register-offsets-for-tgl.patch @@ -0,0 +1,76 @@ +From 6b8446859c971a5783a2cdc90adf32e64de3bd23 Mon Sep 17 00:00:00 2001 +From: Jani Nikula +Date: Wed, 1 Mar 2023 17:14:09 +0200 +Subject: drm/i915/dsi: fix DSS CTL register offsets for TGL+ +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Jani Nikula + +commit 6b8446859c971a5783a2cdc90adf32e64de3bd23 upstream. + +On TGL+ the DSS control registers are at different offsets, and there's +one per pipe. Fix the offsets to fix dual link DSI for TGL+. + +There would be helpers for this in the DSC code, but just do the quick +fix now for DSI. Long term, we should probably move all the DSS handling +into intel_vdsc.c, so exporting the helpers seems counter-productive. + +Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8232 +Cc: Ville Syrjala +Cc: stable@vger.kernel.org +Signed-off-by: Jani Nikula +Reviewed-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20230301151409.1581574-1-jani.nikula@intel.com +(cherry picked from commit 1a62dd9895dca78bee28bba3a36f08836fdd143d) +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/icl_dsi.c | 20 ++++++++++++++++---- + 1 file changed, 16 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/i915/display/icl_dsi.c ++++ b/drivers/gpu/drm/i915/display/icl_dsi.c +@@ -276,9 +276,21 @@ static void configure_dual_link_mode(str + { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); ++ i915_reg_t dss_ctl1_reg, dss_ctl2_reg; + u32 dss_ctl1; + +- dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1); ++ /* FIXME: Move all DSS handling to intel_vdsc.c */ ++ if (DISPLAY_VER(dev_priv) >= 12) { ++ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); ++ ++ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe); ++ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe); ++ } else { ++ dss_ctl1_reg = DSS_CTL1; ++ dss_ctl2_reg = DSS_CTL2; ++ } ++ ++ dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg); + dss_ctl1 |= SPLITTER_ENABLE; + dss_ctl1 &= ~OVERLAP_PIXELS_MASK; + dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); +@@ -299,16 +311,16 @@ static void configure_dual_link_mode(str + + dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; + dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); +- dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2); ++ dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg); + dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK; + dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); +- intel_de_write(dev_priv, DSS_CTL2, dss_ctl2); ++ intel_de_write(dev_priv, dss_ctl2_reg, dss_ctl2); + } else { + /* Interleave */ + dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; + } + +- intel_de_write(dev_priv, DSS_CTL1, dss_ctl1); ++ intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1); + } + + /* aka DSI 8X clock */ diff --git a/queue-5.10/series b/queue-5.10/series index 6c2d74feba5..83a5d79860c 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -65,3 +65,4 @@ mtdblock-tolerate-corrected-bit-flips.patch mtd-rawnand-meson-fix-bitmask-for-length-in-command-word.patch mtd-rawnand-stm32_fmc2-remove-unsupported-edo-mode.patch mtd-rawnand-stm32_fmc2-use-timings.mode-instead-of-checking-trc_min.patch +drm-i915-dsi-fix-dss-ctl-register-offsets-for-tgl.patch