From: Greg Kroah-Hartman Date: Mon, 10 Feb 2025 13:32:34 +0000 (+0100) Subject: 6.6-stable patches X-Git-Tag: v6.6.77~20 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=c7a52eecdfaec4cd68b6c2f2f0e49d409285213a;p=thirdparty%2Fkernel%2Fstable-queue.git 6.6-stable patches added patches: clk-mediatek-mt2701-aud-fix-conversion-to-mtk_clk_simple_probe.patch clk-mediatek-mt2701-bdp-add-missing-dummy-clk.patch clk-mediatek-mt2701-img-add-missing-dummy-clk.patch clk-mediatek-mt2701-mm-add-missing-dummy-clk.patch clk-mediatek-mt2701-vdec-fix-conversion-to-mtk_clk_simple_probe.patch clk-qcom-clk-alpha-pll-fix-alpha-mode-configuration.patch clk-qcom-clk-rpmh-prevent-integer-overflow-in-recalc_rate.patch clk-qcom-dispcc-sm6350-add-missing-parent_map-for-a-clock.patch clk-qcom-gcc-mdm9607-fix-cmd_rcgr-offset-for-blsp1_uart6-rcg.patch clk-qcom-gcc-sm6350-add-missing-parent_map-for-two-clocks.patch clk-qcom-gcc-sm8550-do-not-turn-off-pcie-gdscs-during-gdsc_disable.patch clk-sunxi-ng-a100-enable-mmc-clock-reparenting.patch media-i2c-ds90ub960-fix-ub9702-refclk-register-access.patch --- diff --git a/queue-6.6/clk-mediatek-mt2701-aud-fix-conversion-to-mtk_clk_simple_probe.patch b/queue-6.6/clk-mediatek-mt2701-aud-fix-conversion-to-mtk_clk_simple_probe.patch new file mode 100644 index 0000000000..fbfc5f4ef9 --- /dev/null +++ b/queue-6.6/clk-mediatek-mt2701-aud-fix-conversion-to-mtk_clk_simple_probe.patch @@ -0,0 +1,69 @@ +From 5fba40be5fbad563914e3ce9d5129a6baaea1ff5 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sun, 15 Dec 2024 22:14:11 +0000 +Subject: clk: mediatek: mt2701-aud: fix conversion to mtk_clk_simple_probe + +From: Daniel Golle + +commit 5fba40be5fbad563914e3ce9d5129a6baaea1ff5 upstream. + +Some of the audio subsystem clocks defined in clk-mt2701.h aren't +actually used by the driver. This broke conversion to +mtk_clk_simple_probe which expects that the highest possible clk id is +defined by the ARRAY_SIZE. + +Add additional dummy clocks to fill the gaps and remain compatible with +the existing DT bindings. + +Fixes: 0f69a423c458 ("clk: mediatek: Switch to mtk_clk_simple_probe() where possible") +Cc: stable@vger.kernel.org +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/a07584d803af57b9ce4b5df5e122c09bf5a56ac9.1734300668.git.daniel@makrotopia.org +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Stephen Boyd +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/mediatek/clk-mt2701-aud.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/drivers/clk/mediatek/clk-mt2701-aud.c ++++ b/drivers/clk/mediatek/clk-mt2701-aud.c +@@ -55,10 +55,16 @@ static const struct mtk_gate audio_clks[ + GATE_DUMMY(CLK_DUMMY, "aud_dummy"), + /* AUDIO0 */ + GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2), ++ GATE_DUMMY(CLK_AUD_LRCK_DETECT, "audio_lrck_detect_dummy"), ++ GATE_DUMMY(CLK_AUD_I2S, "audio_i2c_dummy"), ++ GATE_DUMMY(CLK_AUD_APLL_TUNER, "audio_apll_tuner_dummy"), + GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20), + GATE_AUDIO0(CLK_AUD_SPDF, "audio_spdf", "audpll_sel", 21), + GATE_AUDIO0(CLK_AUD_SPDF2, "audio_spdf2", "audpll_sel", 22), + GATE_AUDIO0(CLK_AUD_APLL, "audio_apll", "audpll_sel", 23), ++ GATE_DUMMY(CLK_AUD_TML, "audio_tml_dummy"), ++ GATE_DUMMY(CLK_AUD_AHB_IDLE_EXT, "audio_ahb_idle_ext_dummy"), ++ GATE_DUMMY(CLK_AUD_AHB_IDLE_INT, "audio_ahb_idle_int_dummy"), + /* AUDIO1 */ + GATE_AUDIO1(CLK_AUD_I2SIN1, "audio_i2sin1", "aud_mux1_sel", 0), + GATE_AUDIO1(CLK_AUD_I2SIN2, "audio_i2sin2", "aud_mux1_sel", 1), +@@ -76,10 +82,12 @@ static const struct mtk_gate audio_clks[ + GATE_AUDIO1(CLK_AUD_ASRCI2, "audio_asrci2", "asm_h_sel", 13), + GATE_AUDIO1(CLK_AUD_ASRCO1, "audio_asrco1", "asm_h_sel", 14), + GATE_AUDIO1(CLK_AUD_ASRCO2, "audio_asrco2", "asm_h_sel", 15), ++ GATE_DUMMY(CLK_AUD_HDMIRX, "audio_hdmirx_dummy"), + GATE_AUDIO1(CLK_AUD_INTDIR, "audio_intdir", "intdir_sel", 20), + GATE_AUDIO1(CLK_AUD_A1SYS, "audio_a1sys", "aud_mux1_sel", 21), + GATE_AUDIO1(CLK_AUD_A2SYS, "audio_a2sys", "aud_mux2_sel", 22), + GATE_AUDIO1(CLK_AUD_AFE_CONN, "audio_afe_conn", "aud_mux1_sel", 23), ++ GATE_DUMMY(CLK_AUD_AFE_PCMIF, "audio_afe_pcmif_dummy"), + GATE_AUDIO1(CLK_AUD_AFE_MRGIF, "audio_afe_mrgif", "aud_mux1_sel", 25), + /* AUDIO2 */ + GATE_AUDIO2(CLK_AUD_MMIF_UL1, "audio_ul1", "aud_mux1_sel", 0), +@@ -100,6 +108,8 @@ static const struct mtk_gate audio_clks[ + GATE_AUDIO2(CLK_AUD_MMIF_AWB2, "audio_awb2", "aud_mux1_sel", 15), + GATE_AUDIO2(CLK_AUD_MMIF_DAI, "audio_dai", "aud_mux1_sel", 16), + /* AUDIO3 */ ++ GATE_DUMMY(CLK_AUD_DMIC1, "audio_dmic1_dummy"), ++ GATE_DUMMY(CLK_AUD_DMIC2, "audio_dmic2_dummy"), + GATE_AUDIO3(CLK_AUD_ASRCI3, "audio_asrci3", "asm_h_sel", 2), + GATE_AUDIO3(CLK_AUD_ASRCI4, "audio_asrci4", "asm_h_sel", 3), + GATE_AUDIO3(CLK_AUD_ASRCI5, "audio_asrci5", "asm_h_sel", 4), diff --git a/queue-6.6/clk-mediatek-mt2701-bdp-add-missing-dummy-clk.patch b/queue-6.6/clk-mediatek-mt2701-bdp-add-missing-dummy-clk.patch new file mode 100644 index 0000000000..ad074382ad --- /dev/null +++ b/queue-6.6/clk-mediatek-mt2701-bdp-add-missing-dummy-clk.patch @@ -0,0 +1,33 @@ +From fd291adc5e9a4ee6cd91e57f148f3b427f80647b Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sun, 15 Dec 2024 22:14:24 +0000 +Subject: clk: mediatek: mt2701-bdp: add missing dummy clk + +From: Daniel Golle + +commit fd291adc5e9a4ee6cd91e57f148f3b427f80647b upstream. + +Add dummy clk for index 0 which was missed during the conversion to +mtk_clk_simple_probe(). + +Fixes: 973d1607d936 ("clk: mediatek: mt2701: use mtk_clk_simple_probe to simplify driver") +Cc: stable@vger.kernel.org +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/b8526c882a50f2b158df0eccb4a165956fd8fa13.1734300668.git.daniel@makrotopia.org +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Stephen Boyd +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/mediatek/clk-mt2701-bdp.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/clk/mediatek/clk-mt2701-bdp.c ++++ b/drivers/clk/mediatek/clk-mt2701-bdp.c +@@ -31,6 +31,7 @@ static const struct mtk_gate_regs bdp1_c + GATE_MTK(_id, _name, _parent, &bdp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + + static const struct mtk_gate bdp_clks[] = { ++ GATE_DUMMY(CLK_DUMMY, "bdp_dummy"), + GATE_BDP0(CLK_BDP_BRG_BA, "brg_baclk", "mm_sel", 0), + GATE_BDP0(CLK_BDP_BRG_DRAM, "brg_dram", "mm_sel", 1), + GATE_BDP0(CLK_BDP_LARB_DRAM, "larb_dram", "mm_sel", 2), diff --git a/queue-6.6/clk-mediatek-mt2701-img-add-missing-dummy-clk.patch b/queue-6.6/clk-mediatek-mt2701-img-add-missing-dummy-clk.patch new file mode 100644 index 0000000000..8931639e2f --- /dev/null +++ b/queue-6.6/clk-mediatek-mt2701-img-add-missing-dummy-clk.patch @@ -0,0 +1,33 @@ +From 366640868ccb4a7991aebe8442b01340fab218e2 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sun, 15 Dec 2024 22:14:48 +0000 +Subject: clk: mediatek: mt2701-img: add missing dummy clk + +From: Daniel Golle + +commit 366640868ccb4a7991aebe8442b01340fab218e2 upstream. + +Add dummy clk for index 0 which was missed during the conversion to +mtk_clk_simple_probe(). + +Fixes: 973d1607d936 ("clk: mediatek: mt2701: use mtk_clk_simple_probe to simplify driver") +Cc: stable@vger.kernel.org +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/d677486a5c563fe5c47aa995841adc2aaa183b8a.1734300668.git.daniel@makrotopia.org +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Stephen Boyd +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/mediatek/clk-mt2701-img.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/clk/mediatek/clk-mt2701-img.c ++++ b/drivers/clk/mediatek/clk-mt2701-img.c +@@ -22,6 +22,7 @@ static const struct mtk_gate_regs img_cg + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + + static const struct mtk_gate img_clks[] = { ++ GATE_DUMMY(CLK_DUMMY, "img_dummy"), + GATE_IMG(CLK_IMG_SMI_COMM, "img_smi_comm", "mm_sel", 0), + GATE_IMG(CLK_IMG_RESZ, "img_resz", "mm_sel", 1), + GATE_IMG(CLK_IMG_JPGDEC_SMI, "img_jpgdec_smi", "mm_sel", 5), diff --git a/queue-6.6/clk-mediatek-mt2701-mm-add-missing-dummy-clk.patch b/queue-6.6/clk-mediatek-mt2701-mm-add-missing-dummy-clk.patch new file mode 100644 index 0000000000..048414ff86 --- /dev/null +++ b/queue-6.6/clk-mediatek-mt2701-mm-add-missing-dummy-clk.patch @@ -0,0 +1,34 @@ +From 67aea188f23a5dde51c31a720ccf66aed0ce4187 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sun, 15 Dec 2024 22:14:34 +0000 +Subject: clk: mediatek: mt2701-mm: add missing dummy clk + +From: Daniel Golle + +commit 67aea188f23a5dde51c31a720ccf66aed0ce4187 upstream. + +Add dummy clk which was missed during the conversion to +mtk_clk_pdev_probe() and is required for the existing DT bindings to +keep working. + +Fixes: 65c10c50c9c7 ("clk: mediatek: Migrate to mtk_clk_pdev_probe() for multimedia clocks") +Cc: stable@vger.kernel.org +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/9de23440fcba1ffef9e77d58c9f505105e57a250.1734300668.git.daniel@makrotopia.org +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Stephen Boyd +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/mediatek/clk-mt2701-mm.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/clk/mediatek/clk-mt2701-mm.c ++++ b/drivers/clk/mediatek/clk-mt2701-mm.c +@@ -31,6 +31,7 @@ static const struct mtk_gate_regs disp1_ + GATE_MTK(_id, _name, _parent, &disp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + + static const struct mtk_gate mm_clks[] = { ++ GATE_DUMMY(CLK_DUMMY, "mm_dummy"), + GATE_DISP0(CLK_MM_SMI_COMMON, "mm_smi_comm", "mm_sel", 0), + GATE_DISP0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1), + GATE_DISP0(CLK_MM_CMDQ, "mm_cmdq", "mm_sel", 2), diff --git a/queue-6.6/clk-mediatek-mt2701-vdec-fix-conversion-to-mtk_clk_simple_probe.patch b/queue-6.6/clk-mediatek-mt2701-vdec-fix-conversion-to-mtk_clk_simple_probe.patch new file mode 100644 index 0000000000..6e2cf08086 --- /dev/null +++ b/queue-6.6/clk-mediatek-mt2701-vdec-fix-conversion-to-mtk_clk_simple_probe.patch @@ -0,0 +1,37 @@ +From 7c8746126a4e256fcf1af9174ee7d92cc3f3bc31 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sun, 15 Dec 2024 22:13:49 +0000 +Subject: clk: mediatek: mt2701-vdec: fix conversion to mtk_clk_simple_probe + +From: Daniel Golle + +commit 7c8746126a4e256fcf1af9174ee7d92cc3f3bc31 upstream. + +Commit 973d1607d936 ("clk: mediatek: mt2701: use mtk_clk_simple_probe to +simplify driver") broke DT bindings as the highest index was reduced by +1 because the id count starts from 1 and not from 0. + +Fix this, like for other drivers which had the same issue, by adding a +dummy clk at index 0. + +Fixes: 973d1607d936 ("clk: mediatek: mt2701: use mtk_clk_simple_probe to simplify driver") +Cc: stable@vger.kernel.org +Signed-off-by: Daniel Golle +Link: https://lore.kernel.org/r/b126a5577f3667ef19b1b5feea5e70174084fb03.1734300668.git.daniel@makrotopia.org +Reviewed-by: AngeloGioacchino Del Regno +Signed-off-by: Stephen Boyd +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/mediatek/clk-mt2701-vdec.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/clk/mediatek/clk-mt2701-vdec.c ++++ b/drivers/clk/mediatek/clk-mt2701-vdec.c +@@ -31,6 +31,7 @@ static const struct mtk_gate_regs vdec1_ + GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + + static const struct mtk_gate vdec_clks[] = { ++ GATE_DUMMY(CLK_DUMMY, "vdec_dummy"), + GATE_VDEC0(CLK_VDEC_CKGEN, "vdec_cken", "vdec_sel", 0), + GATE_VDEC1(CLK_VDEC_LARB, "vdec_larb_cken", "mm_sel", 0), + }; diff --git a/queue-6.6/clk-qcom-clk-alpha-pll-fix-alpha-mode-configuration.patch b/queue-6.6/clk-qcom-clk-alpha-pll-fix-alpha-mode-configuration.patch new file mode 100644 index 0000000000..7b3c958deb --- /dev/null +++ b/queue-6.6/clk-qcom-clk-alpha-pll-fix-alpha-mode-configuration.patch @@ -0,0 +1,81 @@ +From 33f1722eb86e45320a3dd7b3d42f6593a1d595c2 Mon Sep 17 00:00:00 2001 +From: Gabor Juhos +Date: Mon, 21 Oct 2024 19:32:48 +0200 +Subject: clk: qcom: clk-alpha-pll: fix alpha mode configuration + +From: Gabor Juhos + +commit 33f1722eb86e45320a3dd7b3d42f6593a1d595c2 upstream. + +Commit c45ae598fc16 ("clk: qcom: support for alpha mode configuration") +added support for configuring alpha mode, but it seems that the feature +was never working in practice. + +The value of the alpha_{en,mode}_mask members of the configuration gets +added to the value parameter passed to the regmap_update_bits() function, +however the same values are not getting applied to the bitmask. As the +result, the respective bits in the USER_CTL register are never modifed +which leads to improper configuration of several PLLs. + +The following table shows the PLL configurations where the 'alpha_en_mask' +member is set and which are passed as a parameter for the +clk_alpha_pll_configure() function. In the table the 'expected rate' column +shows the rate the PLL should run at with the given configuration, and +the 'real rate' column shows the rate the PLL runs at actually. The real +rates has been verified on hardwareOn IPQ* platforms, on other platforms, +those are computed values only. + + file pll expected rate real rate + dispcc-qcm2290.c disp_cc_pll0 768.0 MHz 768.0 MHz + dispcc-sm6115.c disp_cc_pll0 768.0 MHz 768.0 MHz + gcc-ipq5018.c ubi32_pll 1000.0 MHz != 984.0 MHz + gcc-ipq6018.c nss_crypto_pll 1200.0 MHz 1200.0 MHz + gcc-ipq6018.c ubi32_pll 1497.6 MHz != 1488.0 MHz + gcc-ipq8074.c nss_crypto_pll 1200.0 MHz != 1190.4 MHz + gcc-qcm2290.c gpll11 532.0 MHz != 518.4 MHz + gcc-qcm2290.c gpll8 533.2 MHz != 518.4 MHz + gcc-qcs404.c gpll3 921.6 MHz 921.6 MHz + gcc-sm6115.c gpll11 600.0 MHz != 595.2 MHz + gcc-sm6115.c gpll8 800.0 MHz != 787.2 MHz + gpucc-sdm660.c gpu_cc_pll0 800.0 MHz != 787.2 MHz + gpucc-sdm660.c gpu_cc_pll1 740.0 MHz != 729.6 MHz + gpucc-sm6115.c gpu_cc_pll0 1200.0 MHz != 1190.4 MHz + gpucc-sm6115.c gpu_cc_pll1 640.0 MHz != 633.6 MHz + gpucc-sm6125.c gpu_pll0 1020.0 MHz != 1017.6 MHz + gpucc-sm6125.c gpu_pll1 930.0 MHz != 921.6 MHz + mmcc-sdm660.c mmpll8 930.0 MHz != 921.6 MHz + mmcc-sdm660.c mmpll5 825.0 MHz != 806.4 MHz + +As it can be seen from the above, there are several PLLs which are +configured incorrectly. + +Change the code to apply both 'alpha_en_mask' and 'alpha_mode_mask' +values to the bitmask in order to configure the alpha mode correctly. + +Applying the 'alpha_en_mask' fixes the initial rate of the PLLs showed +in the table above. Since the 'alpha_mode_mask' is not used by any driver +currently, that part of the change causes no functional changes. + +Cc: stable@vger.kernel.org +Fixes: c45ae598fc16 ("clk: qcom: support for alpha mode configuration") +Signed-off-by: Gabor Juhos +Reviewed-by: Dmitry Baryshkov +Tested-by: Gabor Juhos +Link: https://lore.kernel.org/r/20241021-fix-alpha-mode-config-v1-1-f32c254e02bc@gmail.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/qcom/clk-alpha-pll.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/clk/qcom/clk-alpha-pll.c ++++ b/drivers/clk/qcom/clk-alpha-pll.c +@@ -407,6 +407,8 @@ void clk_alpha_pll_configure(struct clk_ + mask |= config->pre_div_mask; + mask |= config->post_div_mask; + mask |= config->vco_mask; ++ mask |= config->alpha_en_mask; ++ mask |= config->alpha_mode_mask; + + regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); + diff --git a/queue-6.6/clk-qcom-clk-rpmh-prevent-integer-overflow-in-recalc_rate.patch b/queue-6.6/clk-qcom-clk-rpmh-prevent-integer-overflow-in-recalc_rate.patch new file mode 100644 index 0000000000..7809b7ff60 --- /dev/null +++ b/queue-6.6/clk-qcom-clk-rpmh-prevent-integer-overflow-in-recalc_rate.patch @@ -0,0 +1,37 @@ +From 89aa5925d201b90a48416784831916ca203658f9 Mon Sep 17 00:00:00 2001 +From: Anastasia Belova +Date: Tue, 3 Dec 2024 11:42:31 +0300 +Subject: clk: qcom: clk-rpmh: prevent integer overflow in recalc_rate + +From: Anastasia Belova + +commit 89aa5925d201b90a48416784831916ca203658f9 upstream. + +aggr_state and unit fields are u32. The result of their +multiplication may not fit in this type. + +Add explicit casting to prevent overflow. + +Found by Linux Verification Center (linuxtesting.org) with SVACE. + +Fixes: 04053f4d23a4 ("clk: qcom: clk-rpmh: Add IPA clock support") +Cc: stable@vger.kernel.org # 5.4+ +Signed-off-by: Anastasia Belova +Link: https://lore.kernel.org/r/20241203084231.6001-1-abelova@astralinux.ru +Signed-off-by: Bjorn Andersson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/qcom/clk-rpmh.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/qcom/clk-rpmh.c ++++ b/drivers/clk/qcom/clk-rpmh.c +@@ -329,7 +329,7 @@ static unsigned long clk_rpmh_bcm_recalc + { + struct clk_rpmh *c = to_clk_rpmh(hw); + +- return c->aggr_state * c->unit; ++ return (unsigned long)c->aggr_state * c->unit; + } + + static const struct clk_ops clk_rpmh_bcm_ops = { diff --git a/queue-6.6/clk-qcom-dispcc-sm6350-add-missing-parent_map-for-a-clock.patch b/queue-6.6/clk-qcom-dispcc-sm6350-add-missing-parent_map-for-a-clock.patch new file mode 100644 index 0000000000..ec303aa903 --- /dev/null +++ b/queue-6.6/clk-qcom-dispcc-sm6350-add-missing-parent_map-for-a-clock.patch @@ -0,0 +1,58 @@ +From d4cdb196f182d2fbe336c968228be00d8c3fed05 Mon Sep 17 00:00:00 2001 +From: Luca Weiss +Date: Fri, 20 Dec 2024 10:03:31 +0100 +Subject: clk: qcom: dispcc-sm6350: Add missing parent_map for a clock + +From: Luca Weiss + +commit d4cdb196f182d2fbe336c968228be00d8c3fed05 upstream. + +If a clk_rcg2 has a parent, it should also have parent_map defined, +otherwise we'll get a NULL pointer dereference when calling clk_set_rate +like the following: + + [ 3.388105] Call trace: + [ 3.390664] qcom_find_src_index+0x3c/0x70 (P) + [ 3.395301] qcom_find_src_index+0x1c/0x70 (L) + [ 3.399934] _freq_tbl_determine_rate+0x48/0x100 + [ 3.404753] clk_rcg2_determine_rate+0x1c/0x28 + [ 3.409387] clk_core_determine_round_nolock+0x58/0xe4 + [ 3.421414] clk_core_round_rate_nolock+0x48/0xfc + [ 3.432974] clk_core_round_rate_nolock+0xd0/0xfc + [ 3.444483] clk_core_set_rate_nolock+0x8c/0x300 + [ 3.455886] clk_set_rate+0x38/0x14c + +Add the parent_map property for the clock where it's missing and also +un-inline the parent_data as well to keep the matching parent_map and +parent_data together. + +Fixes: 837519775f1d ("clk: qcom: Add display clock controller driver for SM6350") +Cc: stable@vger.kernel.org +Signed-off-by: Luca Weiss +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20241220-sm6350-parent_map-v1-2-64f3d04cb2eb@fairphone.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/qcom/dispcc-sm6350.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +--- a/drivers/clk/qcom/dispcc-sm6350.c ++++ b/drivers/clk/qcom/dispcc-sm6350.c +@@ -187,13 +187,12 @@ static struct clk_rcg2 disp_cc_mdss_dp_a + .cmd_rcgr = 0x1144, + .mnd_width = 0, + .hid_width = 5, ++ .parent_map = disp_cc_parent_map_6, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_aux_clk_src", +- .parent_data = &(const struct clk_parent_data){ +- .fw_name = "bi_tcxo", +- }, +- .num_parents = 1, ++ .parent_data = disp_cc_parent_data_6, ++ .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), + .ops = &clk_rcg2_ops, + }, + }; diff --git a/queue-6.6/clk-qcom-gcc-mdm9607-fix-cmd_rcgr-offset-for-blsp1_uart6-rcg.patch b/queue-6.6/clk-qcom-gcc-mdm9607-fix-cmd_rcgr-offset-for-blsp1_uart6-rcg.patch new file mode 100644 index 0000000000..a0be688d87 --- /dev/null +++ b/queue-6.6/clk-qcom-gcc-mdm9607-fix-cmd_rcgr-offset-for-blsp1_uart6-rcg.patch @@ -0,0 +1,33 @@ +From 88d9dca36aac9659446be1e569d8fbe3462b5741 Mon Sep 17 00:00:00 2001 +From: Satya Priya Kakitapalli +Date: Fri, 20 Dec 2024 15:20:48 +0530 +Subject: clk: qcom: gcc-mdm9607: Fix cmd_rcgr offset for blsp1_uart6 rcg + +From: Satya Priya Kakitapalli + +commit 88d9dca36aac9659446be1e569d8fbe3462b5741 upstream. + +Fix cmd_rcgr offset for blsp1_uart6_apps_clk_src on mdm9607 platform. + +Fixes: 48b7253264ea ("clk: qcom: Add MDM9607 GCC driver") +Cc: stable@vger.kernel.org +Signed-off-by: Satya Priya Kakitapalli +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20241220095048.248425-1-quic_skakitap@quicinc.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/qcom/gcc-mdm9607.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/qcom/gcc-mdm9607.c ++++ b/drivers/clk/qcom/gcc-mdm9607.c +@@ -535,7 +535,7 @@ static struct clk_rcg2 blsp1_uart5_apps_ + }; + + static struct clk_rcg2 blsp1_uart6_apps_clk_src = { +- .cmd_rcgr = 0x6044, ++ .cmd_rcgr = 0x7044, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, diff --git a/queue-6.6/clk-qcom-gcc-sm6350-add-missing-parent_map-for-two-clocks.patch b/queue-6.6/clk-qcom-gcc-sm6350-add-missing-parent_map-for-two-clocks.patch new file mode 100644 index 0000000000..5a4209f8b1 --- /dev/null +++ b/queue-6.6/clk-qcom-gcc-sm6350-add-missing-parent_map-for-two-clocks.patch @@ -0,0 +1,90 @@ +From 96fe1a7ee477d701cfc98ab9d3c730c35d966861 Mon Sep 17 00:00:00 2001 +From: Luca Weiss +Date: Fri, 20 Dec 2024 10:03:30 +0100 +Subject: clk: qcom: gcc-sm6350: Add missing parent_map for two clocks + +From: Luca Weiss + +commit 96fe1a7ee477d701cfc98ab9d3c730c35d966861 upstream. + +If a clk_rcg2 has a parent, it should also have parent_map defined, +otherwise we'll get a NULL pointer dereference when calling clk_set_rate +like the following: + + [ 3.388105] Call trace: + [ 3.390664] qcom_find_src_index+0x3c/0x70 (P) + [ 3.395301] qcom_find_src_index+0x1c/0x70 (L) + [ 3.399934] _freq_tbl_determine_rate+0x48/0x100 + [ 3.404753] clk_rcg2_determine_rate+0x1c/0x28 + [ 3.409387] clk_core_determine_round_nolock+0x58/0xe4 + [ 3.421414] clk_core_round_rate_nolock+0x48/0xfc + [ 3.432974] clk_core_round_rate_nolock+0xd0/0xfc + [ 3.444483] clk_core_set_rate_nolock+0x8c/0x300 + [ 3.455886] clk_set_rate+0x38/0x14c + +Add the parent_map property for two clocks where it's missing and also +un-inline the parent_data as well to keep the matching parent_map and +parent_data together. + +Fixes: 131abae905df ("clk: qcom: Add SM6350 GCC driver") +Cc: stable@vger.kernel.org +Signed-off-by: Luca Weiss +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20241220-sm6350-parent_map-v1-1-64f3d04cb2eb@fairphone.com +Signed-off-by: Bjorn Andersson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/qcom/gcc-sm6350.c | 22 ++++++++++++++-------- + 1 file changed, 14 insertions(+), 8 deletions(-) + +--- a/drivers/clk/qcom/gcc-sm6350.c ++++ b/drivers/clk/qcom/gcc-sm6350.c +@@ -182,6 +182,14 @@ static const struct clk_parent_data gcc_ + { .hw = &gpll0_out_odd.clkr.hw }, + }; + ++static const struct parent_map gcc_parent_map_3[] = { ++ { P_BI_TCXO, 0 }, ++}; ++ ++static const struct clk_parent_data gcc_parent_data_3[] = { ++ { .fw_name = "bi_tcxo" }, ++}; ++ + static const struct parent_map gcc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, +@@ -701,13 +709,12 @@ static struct clk_rcg2 gcc_ufs_phy_phy_a + .cmd_rcgr = 0x3a0b0, + .mnd_width = 0, + .hid_width = 5, ++ .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_phy_aux_clk_src", +- .parent_data = &(const struct clk_parent_data){ +- .fw_name = "bi_tcxo", +- }, +- .num_parents = 1, ++ .parent_data = gcc_parent_data_3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_3), + .ops = &clk_rcg2_ops, + }, + }; +@@ -764,13 +771,12 @@ static struct clk_rcg2 gcc_usb30_prim_mo + .cmd_rcgr = 0x1a034, + .mnd_width = 0, + .hid_width = 5, ++ .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_mock_utmi_clk_src", +- .parent_data = &(const struct clk_parent_data){ +- .fw_name = "bi_tcxo", +- }, +- .num_parents = 1, ++ .parent_data = gcc_parent_data_3, ++ .num_parents = ARRAY_SIZE(gcc_parent_data_3), + .ops = &clk_rcg2_ops, + }, + }; diff --git a/queue-6.6/clk-qcom-gcc-sm8550-do-not-turn-off-pcie-gdscs-during-gdsc_disable.patch b/queue-6.6/clk-qcom-gcc-sm8550-do-not-turn-off-pcie-gdscs-during-gdsc_disable.patch new file mode 100644 index 0000000000..9a20341fc2 --- /dev/null +++ b/queue-6.6/clk-qcom-gcc-sm8550-do-not-turn-off-pcie-gdscs-during-gdsc_disable.patch @@ -0,0 +1,69 @@ +From 967e011013eda287dbec9e8bd3a19ebe730b8a08 Mon Sep 17 00:00:00 2001 +From: Manivannan Sadhasivam +Date: Thu, 19 Dec 2024 22:30:10 +0530 +Subject: clk: qcom: gcc-sm8550: Do not turn off PCIe GDSCs during gdsc_disable() + +From: Manivannan Sadhasivam + +commit 967e011013eda287dbec9e8bd3a19ebe730b8a08 upstream. + +With PWRSTS_OFF_ON, PCIe GDSCs are turned off during gdsc_disable(). This +can happen during scenarios such as system suspend and breaks the resume +of PCIe controllers from suspend. + +So use PWRSTS_RET_ON to indicate the GDSC driver to not turn off the GDSCs +during gdsc_disable() and allow the hardware to transition the GDSCs to +retention when the parent domain enters low power state during system +suspend. + +Cc: stable@vger.kernel.org # 6.2 +Fixes: 955f2ea3b9e9 ("clk: qcom: Add GCC driver for SM8550") +Reported-by: Neil Armstrong +Signed-off-by: Manivannan Sadhasivam +Reviewed-by: Neil Armstrong +Tested-by: Neil Armstrong # on QRD8550 +Link: https://lore.kernel.org/r/20241219170011.70140-1-manivannan.sadhasivam@linaro.org +Signed-off-by: Bjorn Andersson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/qcom/gcc-sm8550.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/clk/qcom/gcc-sm8550.c ++++ b/drivers/clk/qcom/gcc-sm8550.c +@@ -3003,7 +3003,7 @@ static struct gdsc pcie_0_gdsc = { + .pd = { + .name = "pcie_0_gdsc", + }, +- .pwrsts = PWRSTS_OFF_ON, ++ .pwrsts = PWRSTS_RET_ON, + .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + }; + +@@ -3014,7 +3014,7 @@ static struct gdsc pcie_0_phy_gdsc = { + .pd = { + .name = "pcie_0_phy_gdsc", + }, +- .pwrsts = PWRSTS_OFF_ON, ++ .pwrsts = PWRSTS_RET_ON, + .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + }; + +@@ -3025,7 +3025,7 @@ static struct gdsc pcie_1_gdsc = { + .pd = { + .name = "pcie_1_gdsc", + }, +- .pwrsts = PWRSTS_OFF_ON, ++ .pwrsts = PWRSTS_RET_ON, + .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + }; + +@@ -3036,7 +3036,7 @@ static struct gdsc pcie_1_phy_gdsc = { + .pd = { + .name = "pcie_1_phy_gdsc", + }, +- .pwrsts = PWRSTS_OFF_ON, ++ .pwrsts = PWRSTS_RET_ON, + .flags = VOTABLE | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, + }; + diff --git a/queue-6.6/clk-sunxi-ng-a100-enable-mmc-clock-reparenting.patch b/queue-6.6/clk-sunxi-ng-a100-enable-mmc-clock-reparenting.patch new file mode 100644 index 0000000000..cad89b820c --- /dev/null +++ b/queue-6.6/clk-sunxi-ng-a100-enable-mmc-clock-reparenting.patch @@ -0,0 +1,59 @@ +From 16414720045de30945b8d14b7907e0cbf81a4b49 Mon Sep 17 00:00:00 2001 +From: Cody Eksal +Date: Fri, 8 Nov 2024 20:37:37 -0400 +Subject: clk: sunxi-ng: a100: enable MMC clock reparenting + +From: Cody Eksal + +commit 16414720045de30945b8d14b7907e0cbf81a4b49 upstream. + +While testing the MMC nodes proposed in [1], it was noted that mmc0/1 +would fail to initialize, with "mmc: fatal err update clk timeout" in +the kernel logs. A closer look at the clock definitions showed that the MMC +MPs had the "CLK_SET_RATE_NO_REPARENT" flag set. No reason was given for +adding this flag in the first place, and its original purpose is unknown, +but it doesn't seem to make sense and results in severe limitations to MMC +speeds. Thus, remove this flag from the 3 MMC MPs. + +[1] https://msgid.link/20241024170540.2721307-10-masterr3c0rd@epochal.quest + +Fixes: fb038ce4db55 ("clk: sunxi-ng: add support for the Allwinner A100 CCU") +Cc: stable@vger.kernel.org +Signed-off-by: Cody Eksal +Reviewed-by: Andre Przywara +Link: https://patch.msgid.link/20241109003739.3440904-1-masterr3c0rd@epochal.quest +Signed-off-by: Chen-Yu Tsai +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/sunxi-ng/ccu-sun50i-a100.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/clk/sunxi-ng/ccu-sun50i-a100.c ++++ b/drivers/clk/sunxi-ng/ccu-sun50i-a100.c +@@ -436,7 +436,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDI + 24, 2, /* mux */ + BIT(31), /* gate */ + 2, /* post-div */ +- CLK_SET_RATE_NO_REPARENT); ++ 0); + + static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834, + 0, 4, /* M */ +@@ -444,7 +444,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDI + 24, 2, /* mux */ + BIT(31), /* gate */ + 2, /* post-div */ +- CLK_SET_RATE_NO_REPARENT); ++ 0); + + static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838, + 0, 4, /* M */ +@@ -452,7 +452,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDI + 24, 2, /* mux */ + BIT(31), /* gate */ + 2, /* post-div */ +- CLK_SET_RATE_NO_REPARENT); ++ 0); + + static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0); + static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0); diff --git a/queue-6.6/media-i2c-ds90ub960-fix-ub9702-refclk-register-access.patch b/queue-6.6/media-i2c-ds90ub960-fix-ub9702-refclk-register-access.patch new file mode 100644 index 0000000000..1532f9453a --- /dev/null +++ b/queue-6.6/media-i2c-ds90ub960-fix-ub9702-refclk-register-access.patch @@ -0,0 +1,49 @@ +From ba3bdb93947c90f098061de1fb2458e2ca040093 Mon Sep 17 00:00:00 2001 +From: Tomi Valkeinen +Date: Fri, 6 Dec 2024 10:26:38 +0200 +Subject: media: i2c: ds90ub960: Fix UB9702 refclk register access + +From: Tomi Valkeinen + +commit ba3bdb93947c90f098061de1fb2458e2ca040093 upstream. + +UB9702 has the refclk freq register at a different offset than UB960, +but the code uses the UB960's offset for both chips. Fix this. + +The refclk freq is only used for a debug print, so there's no functional +change here. + +Cc: stable@vger.kernel.org +Fixes: afe267f2d368 ("media: i2c: add DS90UB960 driver") +Reviewed-by: Jai Luthra +Signed-off-by: Tomi Valkeinen +Signed-off-by: Sakari Ailus +Signed-off-by: Mauro Carvalho Chehab +Signed-off-by: Greg Kroah-Hartman +--- + drivers/media/i2c/ds90ub960.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +--- a/drivers/media/i2c/ds90ub960.c ++++ b/drivers/media/i2c/ds90ub960.c +@@ -352,6 +352,8 @@ + + #define UB960_SR_I2C_RX_ID(n) (0xf8 + (n)) /* < UB960_FPD_RX_NPORTS */ + ++#define UB9702_SR_REFCLK_FREQ 0x3d ++ + /* Indirect register blocks */ + #define UB960_IND_TARGET_PAT_GEN 0x00 + #define UB960_IND_TARGET_RX_ANA(n) (0x01 + (n)) +@@ -3838,7 +3840,10 @@ static int ub960_enable_core_hw(struct u + if (ret) + goto err_pd_gpio; + +- ret = ub960_read(priv, UB960_XR_REFCLK_FREQ, &refclk_freq); ++ if (priv->hw_data->is_ub9702) ++ ret = ub960_read(priv, UB9702_SR_REFCLK_FREQ, &refclk_freq); ++ else ++ ret = ub960_read(priv, UB960_XR_REFCLK_FREQ, &refclk_freq); + if (ret) + goto err_pd_gpio; + diff --git a/queue-6.6/series b/queue-6.6/series index ca4cce965f..44f3da091c 100644 --- a/queue-6.6/series +++ b/queue-6.6/series @@ -103,3 +103,16 @@ drm-komeda-add-check-for-komeda_get_layer_fourcc_list.patch drm-i915-drop-64bpp-yuv-formats-from-icl-sdr-planes.patch bluetooth-l2cap-handle-null-sock-pointer-in-l2cap_sock_alloc.patch bluetooth-l2cap-accept-zero-as-a-special-value-for-mtu-auto-selection.patch +clk-sunxi-ng-a100-enable-mmc-clock-reparenting.patch +media-i2c-ds90ub960-fix-ub9702-refclk-register-access.patch +clk-qcom-clk-alpha-pll-fix-alpha-mode-configuration.patch +clk-qcom-gcc-sm8550-do-not-turn-off-pcie-gdscs-during-gdsc_disable.patch +clk-qcom-gcc-sm6350-add-missing-parent_map-for-two-clocks.patch +clk-qcom-dispcc-sm6350-add-missing-parent_map-for-a-clock.patch +clk-qcom-gcc-mdm9607-fix-cmd_rcgr-offset-for-blsp1_uart6-rcg.patch +clk-qcom-clk-rpmh-prevent-integer-overflow-in-recalc_rate.patch +clk-mediatek-mt2701-vdec-fix-conversion-to-mtk_clk_simple_probe.patch +clk-mediatek-mt2701-aud-fix-conversion-to-mtk_clk_simple_probe.patch +clk-mediatek-mt2701-bdp-add-missing-dummy-clk.patch +clk-mediatek-mt2701-img-add-missing-dummy-clk.patch +clk-mediatek-mt2701-mm-add-missing-dummy-clk.patch