From: Robin Dapp <rdapp.gcc@gmail.com>
Date: Tue, 14 Jan 2025 00:19:42 +0000 (-0700)
Subject: RISC-V: Expand shift count in Xmode in interleave pattern.
X-Git-Tag: basepoints/gcc-16~2669
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=c864ffe615424de08abfe271fee7dc815c93bd21;p=thirdparty%2Fgcc.git

RISC-V: Expand shift count in Xmode in interleave pattern.

Hi,

currently ssa-dse-1.C ICEs because expand_simple_binop returns NULL
when building the scalar that is used to IOR two interleaving
sequences.

That's because we try to emit a shift in HImode.  This patch shifts in
Xmode and then lowpart-subregs the result to HImode.

Regtested on rv64gcv_zvl512b.

Regards
 Robin

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (expand_const_vector): Shift in Xmode.
---

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 9926a7b63bb..3735a5ba659 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1505,10 +1505,11 @@ expand_const_vector (rtx target, rtx src)
 		{
 		  /* { 1, 1, 2, 1, ... }.  */
 		  rtx scalar = expand_simple_binop (
-		    new_smode, ASHIFT,
-		    gen_int_mode (rtx_to_poly_int64 (base2), new_smode),
-		    gen_int_mode (builder.inner_bits_size (), new_smode),
+		    Xmode, ASHIFT,
+		    gen_int_mode (rtx_to_poly_int64 (base2), Xmode),
+		    gen_int_mode (builder.inner_bits_size (), Xmode),
 		    NULL_RTX, false, OPTAB_DIRECT);
+		  scalar = simplify_gen_subreg (new_smode, scalar, Xmode, 0);
 		  rtx tmp2 = gen_reg_rtx (new_mode);
 		  rtx ior_ops[] = {tmp2, tmp1, scalar};
 		  emit_vlmax_insn (code_for_pred_scalar (IOR, new_mode),