From: Greg Kroah-Hartman Date: Sat, 18 Jan 2020 15:13:56 +0000 (+0100) Subject: 5.4-stable patches X-Git-Tag: v4.4.211~63 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=c867d691371d960efa5e18c38fb14294bd23746a;p=thirdparty%2Fkernel%2Fstable-queue.git 5.4-stable patches added patches: alsa-dice-fix-fallback-from-protocol-extension-into-limited-functionality.patch alsa-firewire-tascam-fix-corruption-due-to-spin-lock-without-restoration-in-softirq-context.patch alsa-seq-fix-racy-access-for-queue-timer-in-proc-read.patch alsa-usb-audio-fix-sync-ep-altsetting-sanity-check.patch arm-davinci-select-config_reset_controller.patch arm-dts-am571x-idk-fix-gpios-property-to-have-the-correct-gpio-number.patch arm-dts-imx6q-dhcom-fix-rtc-compatible.patch arm-dts-imx6q-dhcom-fix-sgtl5000-vddio-regulator-connection.patch arm-dts-imx7ulp-fix-reg-of-cpu-node.patch arm-dts-meson8-fix-the-size-of-the-pmu-registers.patch arm-omap2-fix-ti_sysc_find_one_clockdomain-to-check-for-to_clk_hw_omap.patch arm64-dts-agilex-stratix10-fix-pmu-interrupt-numbers.patch arm64-dts-allwinner-a64-olinuxino-fix-emmc-supply-regulator.patch arm64-dts-allwinner-a64-olinuxino-fix-sdio-supply-regulator.patch arm64-dts-imx8mm-change-sdma1-ahb-clock-for-imx8mm.patch arm64-dts-imx8mq-librem5-devkit-use-correct-interrupt-for-the-magnetometer.patch arm64-dts-ls1028a-fix-endian-setting-for-dcfg.patch asoc-intel-bytcht_es8316-fix-irbis-nb41-netbook-quirk.patch asoc-msm8916-wcd-analog-fix-mic-bias-internal1.patch asoc-msm8916-wcd-analog-fix-selected-events-for-mic-bias-external1.patch asoc-msm8916-wcd-digital-reset-rx-interpolation-path-after-use.patch asoc-stm32-dfsdm-fix-16-bits-record.patch asoc-stm32-sai-fix-possible-circular-locking.patch block-fix-an-integer-overflow-in-logical-block-size.patch bus-ti-sysc-fix-iterating-over-clocks.patch clk-don-t-try-to-enable-critical-clocks-if-prepare-failed.patch clk-qcom-gcc-sdm845-add-missing-flag-to-votable-gdscs.patch clk-sunxi-ng-r40-allow-setting-parent-rate-for-external-clock-outputs.patch cpuidle-teo-fix-intervals-array-indexing-bug.patch dt-bindings-reset-meson8b-fix-duplicate-reset-ids.patch fix-built-in-early-load-intel-microcode-alignment.patch fuse-fix-fuse_send_readpages-in-the-syncronous-read-case.patch io_uring-only-allow-submit-from-owning-task.patch revert-gpio-thunderx-switch-to-gpiolib_irqchip.patch soc-amlogic-meson-ee-pwrc-propagate-errors-from-pm_genpd_init.patch soc-amlogic-meson-ee-pwrc-propagate-pd-provider-registration-errors.patch --- diff --git a/queue-5.4/alsa-dice-fix-fallback-from-protocol-extension-into-limited-functionality.patch b/queue-5.4/alsa-dice-fix-fallback-from-protocol-extension-into-limited-functionality.patch new file mode 100644 index 00000000000..af893527a74 --- /dev/null +++ b/queue-5.4/alsa-dice-fix-fallback-from-protocol-extension-into-limited-functionality.patch @@ -0,0 +1,40 @@ +From 3e2dc6bdb56893bc28257e482e1dbe5d39f313df Mon Sep 17 00:00:00 2001 +From: Takashi Sakamoto +Date: Mon, 13 Jan 2020 17:46:28 +0900 +Subject: ALSA: dice: fix fallback from protocol extension into limited functionality + +From: Takashi Sakamoto + +commit 3e2dc6bdb56893bc28257e482e1dbe5d39f313df upstream. + +At failure of attempt to detect protocol extension, ALSA dice driver +should be fallback to limited functionality. However it's not. + +This commit fixes it. + +Cc: # v4.18+ +Fixes: 58579c056c1c9 ("ALSA: dice: use extended protocol to detect available stream formats") +Signed-off-by: Takashi Sakamoto +Link: https://lore.kernel.org/r/20200113084630.14305-2-o-takashi@sakamocchi.jp +Signed-off-by: Takashi Iwai +Signed-off-by: Greg Kroah-Hartman + +--- + sound/firewire/dice/dice-extension.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/sound/firewire/dice/dice-extension.c ++++ b/sound/firewire/dice/dice-extension.c +@@ -159,8 +159,11 @@ int snd_dice_detect_extension_formats(st + int j; + + for (j = i + 1; j < 9; ++j) { +- if (pointers[i * 2] == pointers[j * 2]) ++ if (pointers[i * 2] == pointers[j * 2]) { ++ // Fallback to limited functionality. ++ err = -ENXIO; + goto end; ++ } + } + } + diff --git a/queue-5.4/alsa-firewire-tascam-fix-corruption-due-to-spin-lock-without-restoration-in-softirq-context.patch b/queue-5.4/alsa-firewire-tascam-fix-corruption-due-to-spin-lock-without-restoration-in-softirq-context.patch new file mode 100644 index 00000000000..b7ceb46d46f --- /dev/null +++ b/queue-5.4/alsa-firewire-tascam-fix-corruption-due-to-spin-lock-without-restoration-in-softirq-context.patch @@ -0,0 +1,44 @@ +From 747d1f076de5a60770011f6e512de43298ec64cb Mon Sep 17 00:00:00 2001 +From: Takashi Sakamoto +Date: Mon, 13 Jan 2020 17:57:19 +0900 +Subject: ALSA: firewire-tascam: fix corruption due to spin lock without restoration in SoftIRQ context + +From: Takashi Sakamoto + +commit 747d1f076de5a60770011f6e512de43298ec64cb upstream. + +ALSA firewire-tascam driver can bring corruption due to spin lock without +restoration of IRQ flag in SoftIRQ context. This commit fixes the bug. + +Cc: Scott Bahling +Cc: # v4.21 +Fixes: d7167422433c ("ALSA: firewire-tascam: queue events for change of control surface") +Signed-off-by: Takashi Sakamoto +Link: https://lore.kernel.org/r/20200113085719.26788-1-o-takashi@sakamocchi.jp +Signed-off-by: Takashi Iwai +Signed-off-by: Greg Kroah-Hartman + +--- + sound/firewire/tascam/amdtp-tascam.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/sound/firewire/tascam/amdtp-tascam.c ++++ b/sound/firewire/tascam/amdtp-tascam.c +@@ -157,14 +157,15 @@ static void read_status_messages(struct + if ((before ^ after) & mask) { + struct snd_firewire_tascam_change *entry = + &tscm->queue[tscm->push_pos]; ++ unsigned long flag; + +- spin_lock_irq(&tscm->lock); ++ spin_lock_irqsave(&tscm->lock, flag); + entry->index = index; + entry->before = before; + entry->after = after; + if (++tscm->push_pos >= SND_TSCM_QUEUE_COUNT) + tscm->push_pos = 0; +- spin_unlock_irq(&tscm->lock); ++ spin_unlock_irqrestore(&tscm->lock, flag); + + wake_up(&tscm->hwdep_wait); + } diff --git a/queue-5.4/alsa-seq-fix-racy-access-for-queue-timer-in-proc-read.patch b/queue-5.4/alsa-seq-fix-racy-access-for-queue-timer-in-proc-read.patch new file mode 100644 index 00000000000..69f81da6a19 --- /dev/null +++ b/queue-5.4/alsa-seq-fix-racy-access-for-queue-timer-in-proc-read.patch @@ -0,0 +1,54 @@ +From 60adcfde92fa40fcb2dbf7cc52f9b096e0cd109a Mon Sep 17 00:00:00 2001 +From: Takashi Iwai +Date: Wed, 15 Jan 2020 21:37:33 +0100 +Subject: ALSA: seq: Fix racy access for queue timer in proc read + +From: Takashi Iwai + +commit 60adcfde92fa40fcb2dbf7cc52f9b096e0cd109a upstream. + +snd_seq_info_timer_read() reads the information of the timer assigned +for each queue, but it's done in a racy way which may lead to UAF as +spotted by syzkaller. + +This patch applies the missing q->timer_mutex lock while accessing the +timer object as well as a slight code change to adapt the standard +coding style. + +Reported-by: syzbot+2b2ef983f973e5c40943@syzkaller.appspotmail.com +Cc: +Link: https://lore.kernel.org/r/20200115203733.26530-1-tiwai@suse.de +Signed-off-by: Takashi Iwai +Signed-off-by: Greg Kroah-Hartman + +--- + sound/core/seq/seq_timer.c | 14 +++++++++----- + 1 file changed, 9 insertions(+), 5 deletions(-) + +--- a/sound/core/seq/seq_timer.c ++++ b/sound/core/seq/seq_timer.c +@@ -465,15 +465,19 @@ void snd_seq_info_timer_read(struct snd_ + q = queueptr(idx); + if (q == NULL) + continue; +- if ((tmr = q->timer) == NULL || +- (ti = tmr->timeri) == NULL) { +- queuefree(q); +- continue; +- } ++ mutex_lock(&q->timer_mutex); ++ tmr = q->timer; ++ if (!tmr) ++ goto unlock; ++ ti = tmr->timeri; ++ if (!ti) ++ goto unlock; + snd_iprintf(buffer, "Timer for queue %i : %s\n", q->queue, ti->timer->name); + resolution = snd_timer_resolution(ti) * tmr->ticks; + snd_iprintf(buffer, " Period time : %lu.%09lu\n", resolution / 1000000000, resolution % 1000000000); + snd_iprintf(buffer, " Skew : %u / %u\n", tmr->skew, tmr->skew_base); ++unlock: ++ mutex_unlock(&q->timer_mutex); + queuefree(q); + } + } diff --git a/queue-5.4/alsa-usb-audio-fix-sync-ep-altsetting-sanity-check.patch b/queue-5.4/alsa-usb-audio-fix-sync-ep-altsetting-sanity-check.patch new file mode 100644 index 00000000000..d5d9a0c9ecb --- /dev/null +++ b/queue-5.4/alsa-usb-audio-fix-sync-ep-altsetting-sanity-check.patch @@ -0,0 +1,42 @@ +From 5d1b71226dc4d44b4b65766fa9d74492f9d4587b Mon Sep 17 00:00:00 2001 +From: Johan Hovold +Date: Tue, 14 Jan 2020 09:39:53 +0100 +Subject: ALSA: usb-audio: fix sync-ep altsetting sanity check + +From: Johan Hovold + +commit 5d1b71226dc4d44b4b65766fa9d74492f9d4587b upstream. + +The altsetting sanity check in set_sync_ep_implicit_fb_quirk() was +checking for there to be at least one altsetting but then went on to +access the second one, which may not exist. + +This could lead to random slab data being used to initialise the sync +endpoint in snd_usb_add_endpoint(). + +Fixes: c75a8a7ae565 ("ALSA: snd-usb: add support for implicit feedback") +Fixes: ca10a7ebdff1 ("ALSA: usb-audio: FT C400 sync playback EP to capture EP") +Fixes: 5e35dc0338d8 ("ALSA: usb-audio: add implicit fb quirk for Behringer UFX1204") +Fixes: 17f08b0d9aaf ("ALSA: usb-audio: add implicit fb quirk for Axe-Fx II") +Fixes: 103e9625647a ("ALSA: usb-audio: simplify set_sync_ep_implicit_fb_quirk") +Cc: stable # 3.5 +Signed-off-by: Johan Hovold +Link: https://lore.kernel.org/r/20200114083953.1106-1-johan@kernel.org +Signed-off-by: Takashi Iwai +Signed-off-by: Greg Kroah-Hartman + +--- + sound/usb/pcm.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/sound/usb/pcm.c ++++ b/sound/usb/pcm.c +@@ -370,7 +370,7 @@ static int set_sync_ep_implicit_fb_quirk + add_sync_ep_from_ifnum: + iface = usb_ifnum_to_if(dev, ifnum); + +- if (!iface || iface->num_altsetting == 0) ++ if (!iface || iface->num_altsetting < 2) + return -EINVAL; + + alts = &iface->altsetting[1]; diff --git a/queue-5.4/arm-davinci-select-config_reset_controller.patch b/queue-5.4/arm-davinci-select-config_reset_controller.patch new file mode 100644 index 00000000000..3e907848ee2 --- /dev/null +++ b/queue-5.4/arm-davinci-select-config_reset_controller.patch @@ -0,0 +1,41 @@ +From 7afec66e2bf5683d8bfc812cc295313d1b8473bc Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Tue, 10 Dec 2019 20:51:44 +0100 +Subject: ARM: davinci: select CONFIG_RESET_CONTROLLER + +From: Arnd Bergmann + +commit 7afec66e2bf5683d8bfc812cc295313d1b8473bc upstream. + +Selecting RESET_CONTROLLER is actually required, otherwise we +can get a link failure in the clock driver: + +drivers/clk/davinci/psc.o: In function `__davinci_psc_register_clocks': +psc.c:(.text+0x9a0): undefined reference to `devm_reset_controller_register' +drivers/clk/davinci/psc-da850.o: In function `da850_psc0_init': +psc-da850.c:(.text+0x24): undefined reference to `reset_controller_add_lookup' + +Link: https://lore.kernel.org/r/20191210195202.622734-1-arnd@arndb.de +Fixes: f962396ce292 ("ARM: davinci: support multiplatform build for ARM v5") +Cc: # v5.4 +Signed-off-by: Arnd Bergmann +Reviewed-by: Bartosz Golaszewski +Reviewed-by: Philipp Zabel +Acked-by: Sekhar Nori +Signed-off-by: Olof Johansson +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-davinci/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/mach-davinci/Kconfig ++++ b/arch/arm/mach-davinci/Kconfig +@@ -9,6 +9,7 @@ menuconfig ARCH_DAVINCI + select PM_GENERIC_DOMAINS if PM + select PM_GENERIC_DOMAINS_OF if PM && OF + select REGMAP_MMIO ++ select RESET_CONTROLLER + select HAVE_IDE + select PINCTRL_SINGLE + diff --git a/queue-5.4/arm-dts-am571x-idk-fix-gpios-property-to-have-the-correct-gpio-number.patch b/queue-5.4/arm-dts-am571x-idk-fix-gpios-property-to-have-the-correct-gpio-number.patch new file mode 100644 index 00000000000..8890d7ccf2f --- /dev/null +++ b/queue-5.4/arm-dts-am571x-idk-fix-gpios-property-to-have-the-correct-gpio-number.patch @@ -0,0 +1,38 @@ +From 0c4eb2a6b3c6b0facd0a3bccda5db22e7b3b6f96 Mon Sep 17 00:00:00 2001 +From: Kishon Vijay Abraham I +Date: Tue, 17 Dec 2019 14:21:23 +0530 +Subject: ARM: dts: am571x-idk: Fix gpios property to have the correct gpio number + +From: Kishon Vijay Abraham I + +commit 0c4eb2a6b3c6b0facd0a3bccda5db22e7b3b6f96 upstream. + +commit d23f3839fe97d8dce03d ("ARM: dts: DRA7: Add pcie1 dt node for +EP mode") while adding the dt node for EP mode for DRA7 platform, +added rc node for am571x-idk and populated gpios property with +"gpio3 23". However the GPIO_PCIE_SWRST line is actually connected +to "gpio5 18". Fix it here. (The patch adding "gpio3 23" was tested +with another am57x board in EP mode which doesn't rely on reset from +host). + +Cc: stable # 4.14+ +Fixes: d23f3839fe97d8dce03d ("ARM: dts: DRA7: Add pcie1 dt node for EP mode") +Signed-off-by: Kishon Vijay Abraham I +Signed-off-by: Tony Lindgren +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/boot/dts/am571x-idk.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/am571x-idk.dts ++++ b/arch/arm/boot/dts/am571x-idk.dts +@@ -167,7 +167,7 @@ + + &pcie1_rc { + status = "okay"; +- gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; ++ gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + }; + + &pcie1_ep { diff --git a/queue-5.4/arm-dts-imx6q-dhcom-fix-rtc-compatible.patch b/queue-5.4/arm-dts-imx6q-dhcom-fix-rtc-compatible.patch new file mode 100644 index 00000000000..057f6b5a459 --- /dev/null +++ b/queue-5.4/arm-dts-imx6q-dhcom-fix-rtc-compatible.patch @@ -0,0 +1,32 @@ +From 7d7778b1396bc9e2a3875009af522beb4ea9355a Mon Sep 17 00:00:00 2001 +From: Alexandre Belloni +Date: Fri, 13 Dec 2019 00:08:14 +0100 +Subject: ARM: dts: imx6q-dhcom: fix rtc compatible + +From: Alexandre Belloni + +commit 7d7778b1396bc9e2a3875009af522beb4ea9355a upstream. + +The only correct and documented compatible string for the rv3029 is +microcrystal,rv3029. Fix it up. + +Fixes: 52c7a088badd ("ARM: dts: imx6q: Add support for the DHCOM iMX6 SoM and PDK2") +Signed-off-by: Alexandre Belloni +Signed-off-by: Shawn Guo +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi ++++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi +@@ -206,7 +206,7 @@ + }; + + rtc@56 { +- compatible = "rv3029c2"; ++ compatible = "microcrystal,rv3029"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_hw300>; + reg = <0x56>; diff --git a/queue-5.4/arm-dts-imx6q-dhcom-fix-sgtl5000-vddio-regulator-connection.patch b/queue-5.4/arm-dts-imx6q-dhcom-fix-sgtl5000-vddio-regulator-connection.patch new file mode 100644 index 00000000000..ebe06f879f0 --- /dev/null +++ b/queue-5.4/arm-dts-imx6q-dhcom-fix-sgtl5000-vddio-regulator-connection.patch @@ -0,0 +1,36 @@ +From fe6a6689d1815b63528796886853890d8ee7f021 Mon Sep 17 00:00:00 2001 +From: Marek Vasut +Date: Fri, 20 Dec 2019 10:11:24 +0100 +Subject: ARM: dts: imx6q-dhcom: Fix SGTL5000 VDDIO regulator connection + +From: Marek Vasut + +commit fe6a6689d1815b63528796886853890d8ee7f021 upstream. + +The SGTL5000 VDDIO is connected to the PMIC SW2 output, not to +a fixed 3V3 rail. Describe this correctly in the DT. + +Fixes: 52c7a088badd ("ARM: dts: imx6q: Add support for the DHCOM iMX6 SoM and PDK2") +Signed-off-by: Marek Vasut +Cc: Fabio Estevam +Cc: Ludwig Zenz +Cc: NXP Linux Team +To: linux-arm-kernel@lists.infradead.org +Signed-off-by: Shawn Guo +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/boot/dts/imx6q-dhcom-pdk2.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts ++++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts +@@ -55,7 +55,7 @@ + #sound-dai-cells = <0>; + clocks = <&clk_ext_audio_codec>; + VDDA-supply = <®_3p3v>; +- VDDIO-supply = <®_3p3v>; ++ VDDIO-supply = <&sw2_reg>; + }; + }; + diff --git a/queue-5.4/arm-dts-imx7ulp-fix-reg-of-cpu-node.patch b/queue-5.4/arm-dts-imx7ulp-fix-reg-of-cpu-node.patch new file mode 100644 index 00000000000..e7a48341cf6 --- /dev/null +++ b/queue-5.4/arm-dts-imx7ulp-fix-reg-of-cpu-node.patch @@ -0,0 +1,50 @@ +From b8ab62ff7199fac8ce27fa4a149929034fabe7f8 Mon Sep 17 00:00:00 2001 +From: Peng Fan +Date: Wed, 18 Dec 2019 12:22:32 +0000 +Subject: ARM: dts: imx7ulp: fix reg of cpu node + +From: Peng Fan + +commit b8ab62ff7199fac8ce27fa4a149929034fabe7f8 upstream. + +According to arm cpus binding doc, +" + On 32-bit ARM v7 or later systems this property is + required and matches the CPU MPIDR[23:0] register + bits. + + Bits [23:0] in the reg cell must be set to + bits [23:0] in MPIDR. + + All other bits in the reg cell must be set to 0. +" + +In i.MX7ULP, the MPIDR[23:0] is 0xf00, not 0, so fix it. +Otherwise there will be warning: +"DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map" + +Fixes: 20434dc92c05 ("ARM: dts: imx: add common imx7ulp dtsi support") +Signed-off-by: Peng Fan +Reviewed-by: Fabio Estevam +Signed-off-by: Shawn Guo +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/boot/dts/imx7ulp.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm/boot/dts/imx7ulp.dtsi ++++ b/arch/arm/boot/dts/imx7ulp.dtsi +@@ -37,10 +37,10 @@ + #address-cells = <1>; + #size-cells = <0>; + +- cpu0: cpu@0 { ++ cpu0: cpu@f00 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; +- reg = <0>; ++ reg = <0xf00>; + }; + }; + diff --git a/queue-5.4/arm-dts-meson8-fix-the-size-of-the-pmu-registers.patch b/queue-5.4/arm-dts-meson8-fix-the-size-of-the-pmu-registers.patch new file mode 100644 index 00000000000..3f5aaaae52a --- /dev/null +++ b/queue-5.4/arm-dts-meson8-fix-the-size-of-the-pmu-registers.patch @@ -0,0 +1,54 @@ +From 46c9585ed4af688ff1be6d4e76d7ed2f04de4fba Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sun, 17 Nov 2019 16:41:54 +0100 +Subject: ARM: dts: meson8: fix the size of the PMU registers + +From: Martin Blumenstingl + +commit 46c9585ed4af688ff1be6d4e76d7ed2f04de4fba upstream. + +The PMU registers are at least 0x18 bytes wide. Meson8b already uses a +size of 0x18. The structure of the PMU registers on Meson8 and Meson8b +is similar but not identical. + +Meson8 and Meson8b have the following registers in common (starting at +AOBUS + 0xe0): + #define AO_RTI_PWR_A9_CNTL0 0xe0 (0x38 << 2) + #define AO_RTI_PWR_A9_CNTL1 0xe4 (0x39 << 2) + #define AO_RTI_GEN_PWR_SLEEP0 0xe8 (0x3a << 2) + #define AO_RTI_GEN_PWR_ISO0 0x4c (0x3b << 2) + +Meson8b additionally has these three registers: + #define AO_RTI_GEN_PWR_ACK0 0xf0 (0x3c << 2) + #define AO_RTI_PWR_A9_MEM_PD0 0xf4 (0x3d << 2) + #define AO_RTI_PWR_A9_MEM_PD1 0xf8 (0x3e << 2) + +Thus we can assume that the register size of the PMU IP blocks is +identical on both SoCs (and Meson8 just contains some reserved registers +in that area) because the CEC registers start right after the PMU +(AO_RTI_*) registers at AOBUS + 0x100 (0x40 << 2). + +The upcoming power domain driver will need to read and write the +AO_RTI_GEN_PWR_SLEEP0 and AO_RTI_GEN_PWR_ISO0 registers, so the updated +size is needed for that driver to work. + +Fixes: 4a5a27116b447d ("ARM: dts: meson8: add support for booting the secondary CPU cores") +Signed-off-by: Martin Blumenstingl +Signed-off-by: Kevin Hilman +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/boot/dts/meson8.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/meson8.dtsi ++++ b/arch/arm/boot/dts/meson8.dtsi +@@ -253,7 +253,7 @@ + &aobus { + pmu: pmu@e0 { + compatible = "amlogic,meson8-pmu", "syscon"; +- reg = <0xe0 0x8>; ++ reg = <0xe0 0x18>; + }; + + pinctrl_aobus: pinctrl@84 { diff --git a/queue-5.4/arm-omap2-fix-ti_sysc_find_one_clockdomain-to-check-for-to_clk_hw_omap.patch b/queue-5.4/arm-omap2-fix-ti_sysc_find_one_clockdomain-to-check-for-to_clk_hw_omap.patch new file mode 100644 index 00000000000..77034de4e8c --- /dev/null +++ b/queue-5.4/arm-omap2-fix-ti_sysc_find_one_clockdomain-to-check-for-to_clk_hw_omap.patch @@ -0,0 +1,47 @@ +From 90bdfa0b05e3cc809a7c1aa3b1f162b46ea1b330 Mon Sep 17 00:00:00 2001 +From: Tony Lindgren +Date: Mon, 16 Dec 2019 14:41:53 -0800 +Subject: ARM: OMAP2+: Fix ti_sysc_find_one_clockdomain to check for to_clk_hw_omap + +From: Tony Lindgren + +commit 90bdfa0b05e3cc809a7c1aa3b1f162b46ea1b330 upstream. + +We must bail out early if the clock is not hw_omap. Otherwise we will +try to access invalid address with hwclk->clkdm_name: + +Unable to handle kernel paging request at virtual address ffffffff +Internal error: Oops: 27 [#1] ARM +... +(strcmp) from [] (clkdm_lookup+0x40/0x60) +[] (clkdm_lookup) from [] (ti_sysc_clkdm_init+0x5c/0x64) +[] (ti_sysc_clkdm_init) from [] (sysc_probe+0x948/0x117c) +[] (sysc_probe) from [] (platform_drv_probe+0x48/0x98) +... + +Fixes: 2b2f7def058a ("bus: ti-sysc: Add support for missing clockdomain handling") +Signed-off-by: Tony Lindgren +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-omap2/pdata-quirks.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/arch/arm/mach-omap2/pdata-quirks.c ++++ b/arch/arm/mach-omap2/pdata-quirks.c +@@ -368,10 +368,14 @@ static void __init dra7x_evm_mmc_quirk(v + + static struct clockdomain *ti_sysc_find_one_clockdomain(struct clk *clk) + { ++ struct clk_hw *hw = __clk_get_hw(clk); + struct clockdomain *clkdm = NULL; + struct clk_hw_omap *hwclk; + +- hwclk = to_clk_hw_omap(__clk_get_hw(clk)); ++ hwclk = to_clk_hw_omap(hw); ++ if (!omap2_clk_is_hw_omap(hw)) ++ return NULL; ++ + if (hwclk && hwclk->clkdm_name) + clkdm = clkdm_lookup(hwclk->clkdm_name); + diff --git a/queue-5.4/arm64-dts-agilex-stratix10-fix-pmu-interrupt-numbers.patch b/queue-5.4/arm64-dts-agilex-stratix10-fix-pmu-interrupt-numbers.patch new file mode 100644 index 00000000000..1c0116f700c --- /dev/null +++ b/queue-5.4/arm64-dts-agilex-stratix10-fix-pmu-interrupt-numbers.patch @@ -0,0 +1,57 @@ +From 210de0e996aee8e360ccc9e173fe7f0a7ed2f695 Mon Sep 17 00:00:00 2001 +From: Dinh Nguyen +Date: Wed, 20 Nov 2019 09:15:17 -0600 +Subject: arm64: dts: agilex/stratix10: fix pmu interrupt numbers + +From: Dinh Nguyen + +commit 210de0e996aee8e360ccc9e173fe7f0a7ed2f695 upstream. + +Fix up the correct interrupt numbers for the PMU unit on Agilex +and Stratix10. + +Fixes: 78cd6a9d8e15 ("arm64: dts: Add base stratix 10 dtsi") +Cc: linux-stable +Reported-by: Meng Li +Signed-off-by: Dinh Nguyen +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++---- + arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 8 ++++---- + 2 files changed, 8 insertions(+), 8 deletions(-) + +--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi ++++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +@@ -61,10 +61,10 @@ + + pmu { + compatible = "arm,armv8-pmuv3"; +- interrupts = <0 120 8>, +- <0 121 8>, +- <0 122 8>, +- <0 123 8>; ++ interrupts = <0 170 4>, ++ <0 171 4>, ++ <0 172 4>, ++ <0 173 4>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, +--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi ++++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +@@ -47,10 +47,10 @@ + + pmu { + compatible = "arm,armv8-pmuv3"; +- interrupts = <0 120 8>, +- <0 121 8>, +- <0 122 8>, +- <0 123 8>; ++ interrupts = <0 170 4>, ++ <0 171 4>, ++ <0 172 4>, ++ <0 173 4>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, diff --git a/queue-5.4/arm64-dts-allwinner-a64-olinuxino-fix-emmc-supply-regulator.patch b/queue-5.4/arm64-dts-allwinner-a64-olinuxino-fix-emmc-supply-regulator.patch new file mode 100644 index 00000000000..60958a4218d --- /dev/null +++ b/queue-5.4/arm64-dts-allwinner-a64-olinuxino-fix-emmc-supply-regulator.patch @@ -0,0 +1,37 @@ +From 8467ebbf708e5c4574b4eb5f663558fc724945ac Mon Sep 17 00:00:00 2001 +From: Stefan Mavrodiev +Date: Fri, 29 Nov 2019 13:39:39 +0200 +Subject: arm64: dts: allwinner: a64: olinuxino: Fix eMMC supply regulator + +From: Stefan Mavrodiev + +commit 8467ebbf708e5c4574b4eb5f663558fc724945ac upstream. + +A64-OLinuXino-eMMC uses 1.8V for eMMC supply. This is done via a triple +jumper, which sets VCC-PL to either 1.8V or 3.3V. This setting is different +for boards with and without eMMC. + +This is not a big issue for DDR52 mode, however the eMMC will not work in +HS200/HS400, since these modes explicitly requires 1.8V. + +Fixes: 94f68f3a4b2a ("arm64: dts: allwinner: a64: Add A64 OlinuXino board (with eMMC)") +Cc: stable@vger.kernel.org # v5.4 +Signed-off-by: Stefan Mavrodiev +Signed-off-by: Maxime Ripard +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts +@@ -15,7 +15,7 @@ + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <®_dcdc1>; +- vqmmc-supply = <®_dcdc1>; ++ vqmmc-supply = <®_eldo1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; diff --git a/queue-5.4/arm64-dts-allwinner-a64-olinuxino-fix-sdio-supply-regulator.patch b/queue-5.4/arm64-dts-allwinner-a64-olinuxino-fix-sdio-supply-regulator.patch new file mode 100644 index 00000000000..8636d4818ee --- /dev/null +++ b/queue-5.4/arm64-dts-allwinner-a64-olinuxino-fix-sdio-supply-regulator.patch @@ -0,0 +1,37 @@ +From 3d615c2fc2d111b51d2e20516b920138d4ae29a2 Mon Sep 17 00:00:00 2001 +From: Stefan Mavrodiev +Date: Fri, 29 Nov 2019 13:39:41 +0200 +Subject: arm64: dts: allwinner: a64: olinuxino: Fix SDIO supply regulator + +From: Stefan Mavrodiev + +commit 3d615c2fc2d111b51d2e20516b920138d4ae29a2 upstream. + +A64-OLinuXino uses DCDC1 (VCC-IO) for MMC1 supply. In commit 916b68cfe4b5 +("arm64: dts: a64-olinuxino: Enable RTL8723BS WiFi") ALDO2 is set, which is +VCC-PL. Since DCDC1 is always present, the boards are working without a +problem. + +This patch sets the correct regulator. + +Fixes: 916b68cfe4b5 ("arm64: dts: a64-olinuxino: Enable RTL8723BS WiFi") +Cc: stable@vger.kernel.org # v4.16+ +Signed-off-by: Stefan Mavrodiev +Signed-off-by: Maxime Ripard +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +@@ -140,7 +140,7 @@ + &mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; +- vmmc-supply = <®_aldo2>; ++ vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dldo4>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; diff --git a/queue-5.4/arm64-dts-imx8mm-change-sdma1-ahb-clock-for-imx8mm.patch b/queue-5.4/arm64-dts-imx8mm-change-sdma1-ahb-clock-for-imx8mm.patch new file mode 100644 index 00000000000..8af620e5e05 --- /dev/null +++ b/queue-5.4/arm64-dts-imx8mm-change-sdma1-ahb-clock-for-imx8mm.patch @@ -0,0 +1,33 @@ +From 24a572bf67994223e722cadfe663e15ba221882a Mon Sep 17 00:00:00 2001 +From: Adam Ford +Date: Mon, 16 Dec 2019 05:15:30 -0600 +Subject: arm64: dts: imx8mm: Change SDMA1 ahb clock for imx8mm + +From: Adam Ford + +commit 24a572bf67994223e722cadfe663e15ba221882a upstream. + +Using SDMA1 with UART1 is causing a "Timeout waiting for CH0" error. +This patch changes to ahb clock from SDMA1_ROOT to AHB which +fixes the timeout error. + +Fixes: a05ea40eb384 ("arm64: dts: imx: Add i.mx8mm dtsi support") +Signed-off-by: Adam Ford +Signed-off-by: Shawn Guo +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi ++++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi +@@ -741,7 +741,7 @@ + reg = <0x30bd0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, +- <&clk IMX8MM_CLK_SDMA1_ROOT>; ++ <&clk IMX8MM_CLK_AHB>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; diff --git a/queue-5.4/arm64-dts-imx8mq-librem5-devkit-use-correct-interrupt-for-the-magnetometer.patch b/queue-5.4/arm64-dts-imx8mq-librem5-devkit-use-correct-interrupt-for-the-magnetometer.patch new file mode 100644 index 00000000000..d908dd4ce30 --- /dev/null +++ b/queue-5.4/arm64-dts-imx8mq-librem5-devkit-use-correct-interrupt-for-the-magnetometer.patch @@ -0,0 +1,32 @@ +From 106f7b3bf943d267eb657f34616adcaadb2ab07f Mon Sep 17 00:00:00 2001 +From: "Angus Ainslie (Purism)" +Date: Mon, 23 Dec 2019 09:12:53 +0100 +Subject: arm64: dts: imx8mq-librem5-devkit: use correct interrupt for the magnetometer + +From: Angus Ainslie (Purism) + +commit 106f7b3bf943d267eb657f34616adcaadb2ab07f upstream. + +The LSM9DS1 uses a high level interrupt. + +Signed-off-by: Angus Ainslie (Purism) +Signed-off-by: Martin Kepplinger +Fixes: eb4ea0857c83 ("arm64: dts: fsl: librem5: Add a device tree for the Librem5 devkit") +Signed-off-by: Shawn Guo +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts ++++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +@@ -421,7 +421,7 @@ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imu>; + interrupt-parent = <&gpio3>; +- interrupts = <19 IRQ_TYPE_LEVEL_LOW>; ++ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + vdd-supply = <®_3v3_p>; + vddio-supply = <®_3v3_p>; + }; diff --git a/queue-5.4/arm64-dts-ls1028a-fix-endian-setting-for-dcfg.patch b/queue-5.4/arm64-dts-ls1028a-fix-endian-setting-for-dcfg.patch new file mode 100644 index 00000000000..643e69b3fad --- /dev/null +++ b/queue-5.4/arm64-dts-ls1028a-fix-endian-setting-for-dcfg.patch @@ -0,0 +1,33 @@ +From 33eae7fb2e593fdbaac15d843e2558379c6d1149 Mon Sep 17 00:00:00 2001 +From: Yinbo Zhu +Date: Fri, 13 Dec 2019 10:18:39 +0800 +Subject: arm64: dts: ls1028a: fix endian setting for dcfg + +From: Yinbo Zhu + +commit 33eae7fb2e593fdbaac15d843e2558379c6d1149 upstream. + +DCFG block uses little endian. Fix it so that register access becomes +correct. + +Signed-off-by: Yinbo Zhu +Acked-by: Yangbo Lu +Fixes: 8897f3255c9c ("arm64: dts: Add support for NXP LS1028A SoC") +Signed-off-by: Shawn Guo +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +@@ -158,7 +158,7 @@ + dcfg: syscon@1e00000 { + compatible = "fsl,ls1028a-dcfg", "syscon"; + reg = <0x0 0x1e00000 0x0 0x10000>; +- big-endian; ++ little-endian; + }; + + rst: syscon@1e60000 { diff --git a/queue-5.4/asoc-intel-bytcht_es8316-fix-irbis-nb41-netbook-quirk.patch b/queue-5.4/asoc-intel-bytcht_es8316-fix-irbis-nb41-netbook-quirk.patch new file mode 100644 index 00000000000..2bfeab70e2a --- /dev/null +++ b/queue-5.4/asoc-intel-bytcht_es8316-fix-irbis-nb41-netbook-quirk.patch @@ -0,0 +1,42 @@ +From 869bced7a055665e3ddb1ba671a441ce6f997bf1 Mon Sep 17 00:00:00 2001 +From: Hans de Goede +Date: Mon, 6 Jan 2020 12:39:03 +0100 +Subject: ASoC: Intel: bytcht_es8316: Fix Irbis NB41 netbook quirk + +From: Hans de Goede + +commit 869bced7a055665e3ddb1ba671a441ce6f997bf1 upstream. + +When a quirk for the Irbis NB41 netbook was added, to override the defaults +for this device, I forgot to add/keep the BYT_CHT_ES8316_SSP0 part of the +defaults, completely breaking audio on this netbook. + +This commit adds the BYT_CHT_ES8316_SSP0 flag to the Irbis NB41 netbook +quirk, making audio work again. + +Cc: stable@vger.kernel.org +Cc: russianneuromancer@ya.ru +Fixes: aa2ba991c420 ("ASoC: Intel: bytcht_es8316: Add quirk for Irbis NB41 netbook") +Reported-and-tested-by: russianneuromancer@ya.ru +Signed-off-by: Hans de Goede +Acked-by: Pierre-Louis Bossart +Link: https://lore.kernel.org/r/20200106113903.279394-1-hdegoede@redhat.com +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman + +--- + sound/soc/intel/boards/bytcht_es8316.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/sound/soc/intel/boards/bytcht_es8316.c ++++ b/sound/soc/intel/boards/bytcht_es8316.c +@@ -442,7 +442,8 @@ static const struct dmi_system_id byt_ch + DMI_MATCH(DMI_SYS_VENDOR, "IRBIS"), + DMI_MATCH(DMI_PRODUCT_NAME, "NB41"), + }, +- .driver_data = (void *)(BYT_CHT_ES8316_INTMIC_IN2_MAP ++ .driver_data = (void *)(BYT_CHT_ES8316_SSP0 ++ | BYT_CHT_ES8316_INTMIC_IN2_MAP + | BYT_CHT_ES8316_JD_INVERTED), + }, + { /* Teclast X98 Plus II */ diff --git a/queue-5.4/asoc-msm8916-wcd-analog-fix-mic-bias-internal1.patch b/queue-5.4/asoc-msm8916-wcd-analog-fix-mic-bias-internal1.patch new file mode 100644 index 00000000000..5b97a7fde11 --- /dev/null +++ b/queue-5.4/asoc-msm8916-wcd-analog-fix-mic-bias-internal1.patch @@ -0,0 +1,67 @@ +From 057efcf9faea4769cf1020677d93d040db9b23f3 Mon Sep 17 00:00:00 2001 +From: Stephan Gerhold +Date: Sat, 11 Jan 2020 17:40:04 +0100 +Subject: ASoC: msm8916-wcd-analog: Fix MIC BIAS Internal1 + +From: Stephan Gerhold + +commit 057efcf9faea4769cf1020677d93d040db9b23f3 upstream. + +MIC BIAS Internal1 is broken at the moment because we always +enable the internal rbias resistor to the TX2 line (connected to +the headset microphone), rather than enabling the resistor connected +to TX1. + +Move the RBIAS code to pm8916_wcd_analog_enable_micbias_int1/2() +to fix this. + +Fixes: 585e881e5b9e ("ASoC: codecs: Add msm8916-wcd analog codec") +Cc: Srinivas Kandagatla +Signed-off-by: Stephan Gerhold +Link: https://lore.kernel.org/r/20200111164006.43074-3-stephan@gerhold.net +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman + +--- + sound/soc/codecs/msm8916-wcd-analog.c | 16 +++++++++++++--- + 1 file changed, 13 insertions(+), 3 deletions(-) + +--- a/sound/soc/codecs/msm8916-wcd-analog.c ++++ b/sound/soc/codecs/msm8916-wcd-analog.c +@@ -391,9 +391,6 @@ static int pm8916_wcd_analog_enable_micb + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: +- snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS, +- MICB_1_INT_TX2_INT_RBIAS_EN_MASK, +- MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE); + snd_soc_component_update_bits(component, reg, MICB_1_EN_PULL_DOWN_EN_MASK, 0); + snd_soc_component_update_bits(component, CDC_A_MICB_1_EN, + MICB_1_EN_OPA_STG2_TAIL_CURR_MASK, +@@ -443,6 +440,14 @@ static int pm8916_wcd_analog_enable_micb + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); + ++ switch (event) { ++ case SND_SOC_DAPM_PRE_PMU: ++ snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS, ++ MICB_1_INT_TX1_INT_RBIAS_EN_MASK, ++ MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE); ++ break; ++ } ++ + return pm8916_wcd_analog_enable_micbias_int(component, event, w->reg, + wcd->micbias1_cap_mode); + } +@@ -553,6 +558,11 @@ static int pm8916_wcd_analog_enable_micb + struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); + + switch (event) { ++ case SND_SOC_DAPM_PRE_PMU: ++ snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS, ++ MICB_1_INT_TX2_INT_RBIAS_EN_MASK, ++ MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE); ++ break; + case SND_SOC_DAPM_POST_PMU: + pm8916_mbhc_configure_bias(wcd, true); + break; diff --git a/queue-5.4/asoc-msm8916-wcd-analog-fix-selected-events-for-mic-bias-external1.patch b/queue-5.4/asoc-msm8916-wcd-analog-fix-selected-events-for-mic-bias-external1.patch new file mode 100644 index 00000000000..9ce97256c39 --- /dev/null +++ b/queue-5.4/asoc-msm8916-wcd-analog-fix-selected-events-for-mic-bias-external1.patch @@ -0,0 +1,44 @@ +From e0beec88397b163c7c4ea6fcfb67e8e07a2671dc Mon Sep 17 00:00:00 2001 +From: Stephan Gerhold +Date: Sat, 11 Jan 2020 17:40:03 +0100 +Subject: ASoC: msm8916-wcd-analog: Fix selected events for MIC BIAS External1 + +From: Stephan Gerhold + +commit e0beec88397b163c7c4ea6fcfb67e8e07a2671dc upstream. + +MIC BIAS External1 sets pm8916_wcd_analog_enable_micbias_ext1() +as event handler, which ends up in pm8916_wcd_analog_enable_micbias_ext(). + +But pm8916_wcd_analog_enable_micbias_ext() only handles the POST_PMU +event, which is not specified in the event flags for MIC BIAS External1. +This means that the code in the event handler is never actually run. + +Set SND_SOC_DAPM_POST_PMU as the only event for the handler to fix this. + +Fixes: 585e881e5b9e ("ASoC: codecs: Add msm8916-wcd analog codec") +Cc: Srinivas Kandagatla +Signed-off-by: Stephan Gerhold +Link: https://lore.kernel.org/r/20200111164006.43074-2-stephan@gerhold.net +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman + +--- + sound/soc/codecs/msm8916-wcd-analog.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/sound/soc/codecs/msm8916-wcd-analog.c ++++ b/sound/soc/codecs/msm8916-wcd-analog.c +@@ -888,10 +888,10 @@ static const struct snd_soc_dapm_widget + + SND_SOC_DAPM_SUPPLY("MIC BIAS External1", CDC_A_MICB_1_EN, 7, 0, + pm8916_wcd_analog_enable_micbias_ext1, +- SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), ++ SND_SOC_DAPM_POST_PMU), + SND_SOC_DAPM_SUPPLY("MIC BIAS External2", CDC_A_MICB_2_EN, 7, 0, + pm8916_wcd_analog_enable_micbias_ext2, +- SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), ++ SND_SOC_DAPM_POST_PMU), + + SND_SOC_DAPM_ADC_E("ADC1", NULL, CDC_A_TX_1_EN, 7, 0, + pm8916_wcd_analog_enable_adc, diff --git a/queue-5.4/asoc-msm8916-wcd-digital-reset-rx-interpolation-path-after-use.patch b/queue-5.4/asoc-msm8916-wcd-digital-reset-rx-interpolation-path-after-use.patch new file mode 100644 index 00000000000..d6624c91893 --- /dev/null +++ b/queue-5.4/asoc-msm8916-wcd-digital-reset-rx-interpolation-path-after-use.patch @@ -0,0 +1,52 @@ +From 85578bbd642f65065039b1765ebe1a867d5435b0 Mon Sep 17 00:00:00 2001 +From: Stephan Gerhold +Date: Sun, 5 Jan 2020 11:27:53 +0100 +Subject: ASoC: msm8916-wcd-digital: Reset RX interpolation path after use + +From: Stephan Gerhold + +commit 85578bbd642f65065039b1765ebe1a867d5435b0 upstream. + +For some reason, attempting to route audio through QDSP6 on MSM8916 +causes the RX interpolation path to get "stuck" after playing audio +a few times. In this situation, the analog codec part is still working, +but the RX path in the digital codec stops working, so you only hear +the analog parts powering up. After a reboot everything works again. + +So far I was not able to reproduce the problem when using lpass-cpu. + +The downstream kernel driver avoids this by resetting the RX +interpolation path after use. In mainline we do something similar +for the TX decimator (LPASS_CDC_CLK_TX_RESET_B1_CTL), but the +interpolator reset (LPASS_CDC_CLK_RX_RESET_CTL) got lost when the +msm8916-wcd driver was split into analog and digital. + +Fix this problem by adding the reset to +msm8916_wcd_digital_enable_interpolator(). + +Fixes: 150db8c5afa1 ("ASoC: codecs: Add msm8916-wcd digital codec") +Cc: Srinivas Kandagatla +Signed-off-by: Stephan Gerhold +Link: https://lore.kernel.org/r/20200105102753.83108-1-stephan@gerhold.net +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman + +--- + sound/soc/codecs/msm8916-wcd-digital.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/sound/soc/codecs/msm8916-wcd-digital.c ++++ b/sound/soc/codecs/msm8916-wcd-digital.c +@@ -586,6 +586,12 @@ static int msm8916_wcd_digital_enable_in + snd_soc_component_write(component, rx_gain_reg[w->shift], + snd_soc_component_read32(component, rx_gain_reg[w->shift])); + break; ++ case SND_SOC_DAPM_POST_PMD: ++ snd_soc_component_update_bits(component, LPASS_CDC_CLK_RX_RESET_CTL, ++ 1 << w->shift, 1 << w->shift); ++ snd_soc_component_update_bits(component, LPASS_CDC_CLK_RX_RESET_CTL, ++ 1 << w->shift, 0x0); ++ break; + } + return 0; + } diff --git a/queue-5.4/asoc-stm32-dfsdm-fix-16-bits-record.patch b/queue-5.4/asoc-stm32-dfsdm-fix-16-bits-record.patch new file mode 100644 index 00000000000..11d2fb4059f --- /dev/null +++ b/queue-5.4/asoc-stm32-dfsdm-fix-16-bits-record.patch @@ -0,0 +1,64 @@ +From 8e55ea19125b65cffe42747359af99d545e85f2f Mon Sep 17 00:00:00 2001 +From: Olivier Moysan +Date: Fri, 10 Jan 2020 14:11:31 +0100 +Subject: ASoC: stm32: dfsdm: fix 16 bits record + +From: Olivier Moysan + +commit 8e55ea19125b65cffe42747359af99d545e85f2f upstream. + +In stm32_afsdm_pcm_cb function, the transfer size is provided in bytes. +However, samples are copied as 16 bits words from iio buffer. +Divide by two the transfer size, to copy the right number of samples. + +Fixes: 1e7f6e1c69f0 ("ASoC: stm32: dfsdm: add 16 bits audio record support") + +Signed-off-by: Olivier Moysan +Link: https://lore.kernel.org/r/20200110131131.3191-1-olivier.moysan@st.com +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman + +--- + sound/soc/stm/stm32_adfsdm.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/sound/soc/stm/stm32_adfsdm.c ++++ b/sound/soc/stm/stm32_adfsdm.c +@@ -153,13 +153,13 @@ static const struct snd_soc_component_dr + .name = "stm32_dfsdm_audio", + }; + +-static void memcpy_32to16(void *dest, const void *src, size_t n) ++static void stm32_memcpy_32to16(void *dest, const void *src, size_t n) + { + unsigned int i = 0; + u16 *d = (u16 *)dest, *s = (u16 *)src; + + s++; +- for (i = n; i > 0; i--) { ++ for (i = n >> 1; i > 0; i--) { + *d++ = *s++; + s++; + } +@@ -186,8 +186,8 @@ static int stm32_afsdm_pcm_cb(const void + + if ((priv->pos + src_size) > buff_size) { + if (format == SNDRV_PCM_FORMAT_S16_LE) +- memcpy_32to16(&pcm_buff[priv->pos], src_buff, +- buff_size - priv->pos); ++ stm32_memcpy_32to16(&pcm_buff[priv->pos], src_buff, ++ buff_size - priv->pos); + else + memcpy(&pcm_buff[priv->pos], src_buff, + buff_size - priv->pos); +@@ -196,8 +196,8 @@ static int stm32_afsdm_pcm_cb(const void + } + + if (format == SNDRV_PCM_FORMAT_S16_LE) +- memcpy_32to16(&pcm_buff[priv->pos], +- &src_buff[src_size - cur_size], cur_size); ++ stm32_memcpy_32to16(&pcm_buff[priv->pos], ++ &src_buff[src_size - cur_size], cur_size); + else + memcpy(&pcm_buff[priv->pos], &src_buff[src_size - cur_size], + cur_size); diff --git a/queue-5.4/asoc-stm32-sai-fix-possible-circular-locking.patch b/queue-5.4/asoc-stm32-sai-fix-possible-circular-locking.patch new file mode 100644 index 00000000000..ce1baf4be46 --- /dev/null +++ b/queue-5.4/asoc-stm32-sai-fix-possible-circular-locking.patch @@ -0,0 +1,456 @@ +From a14bf98c045bf119b7e779f186528e38c6428830 Mon Sep 17 00:00:00 2001 +From: Olivier Moysan +Date: Thu, 9 Jan 2020 09:32:54 +0100 +Subject: ASoC: stm32: sai: fix possible circular locking + +From: Olivier Moysan + +commit a14bf98c045bf119b7e779f186528e38c6428830 upstream. + +In current driver, locks can be taken as follows: +- Register access: take a lock on regmap config and then on clock. +- Master clock provider: take a lock on clock and then on regmap config. +This can lead to the circular locking summarized below. + +Remove peripheral clock management through regmap framework, and manage +peripheral clock in driver instead. On register access, lock on clock +is taken first, which allows to avoid possible locking issue. + +[ 6696.561513] ====================================================== +[ 6696.567670] WARNING: possible circular locking dependency detected +[ 6696.573842] 4.19.49 #866 Not tainted +[ 6696.577397] ------------------------------------------------------ +[ 6696.583566] pulseaudio/6439 is trying to acquire lock: +[ 6696.588697] 87b0a25b (enable_lock){..-.}, at: clk_enable_lock+0x64/0x128 +[ 6696.595377] +[ 6696.595377] but task is already holding lock: +[ 6696.601197] d858f825 (stm32_sai_sub:1342:(sai->regmap_config)->lock){....} +... +[ 6696.812513] Possible unsafe locking scenario: +[ 6696.812513] +[ 6696.818418] CPU0 CPU1 +[ 6696.822935] ---- ---- +[ 6696.827451] lock(stm32_sai_sub:1342:(sai->regmap_config)->lock); +[ 6696.833618] lock(enable_lock); +[ 6696.839350] lock(stm32_sai_sub:1342: + (sai->regmap_config)->lock); +[ 6696.848035] lock(enable_lock); + +Fixes: 03e78a242a15 ("ASoC: stm32: sai: add h7 support") + +Signed-off-by: Olivier Moysan +Link: https://lore.kernel.org/r/20200109083254.478-1-olivier.moysan@st.com +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman + +--- + sound/soc/stm/stm32_sai_sub.c | 196 ++++++++++++++++++++++++++++++------------ + 1 file changed, 141 insertions(+), 55 deletions(-) + +--- a/sound/soc/stm/stm32_sai_sub.c ++++ b/sound/soc/stm/stm32_sai_sub.c +@@ -184,6 +184,56 @@ static bool stm32_sai_sub_writeable_reg( + } + } + ++static int stm32_sai_sub_reg_up(struct stm32_sai_sub_data *sai, ++ unsigned int reg, unsigned int mask, ++ unsigned int val) ++{ ++ int ret; ++ ++ ret = clk_enable(sai->pdata->pclk); ++ if (ret < 0) ++ return ret; ++ ++ ret = regmap_update_bits(sai->regmap, reg, mask, val); ++ ++ clk_disable(sai->pdata->pclk); ++ ++ return ret; ++} ++ ++static int stm32_sai_sub_reg_wr(struct stm32_sai_sub_data *sai, ++ unsigned int reg, unsigned int mask, ++ unsigned int val) ++{ ++ int ret; ++ ++ ret = clk_enable(sai->pdata->pclk); ++ if (ret < 0) ++ return ret; ++ ++ ret = regmap_write_bits(sai->regmap, reg, mask, val); ++ ++ clk_disable(sai->pdata->pclk); ++ ++ return ret; ++} ++ ++static int stm32_sai_sub_reg_rd(struct stm32_sai_sub_data *sai, ++ unsigned int reg, unsigned int *val) ++{ ++ int ret; ++ ++ ret = clk_enable(sai->pdata->pclk); ++ if (ret < 0) ++ return ret; ++ ++ ret = regmap_read(sai->regmap, reg, val); ++ ++ clk_disable(sai->pdata->pclk); ++ ++ return ret; ++} ++ + static const struct regmap_config stm32_sai_sub_regmap_config_f4 = { + .reg_bits = 32, + .reg_stride = 4, +@@ -295,7 +345,7 @@ static int stm32_sai_set_clk_div(struct + + mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version)); + cr1 = SAI_XCR1_MCKDIV_SET(div); +- ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1); ++ ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, mask, cr1); + if (ret < 0) + dev_err(&sai->pdev->dev, "Failed to update CR1 register\n"); + +@@ -372,8 +422,8 @@ static int stm32_sai_mclk_enable(struct + + dev_dbg(&sai->pdev->dev, "Enable master clock\n"); + +- return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, +- SAI_XCR1_MCKEN, SAI_XCR1_MCKEN); ++ return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, ++ SAI_XCR1_MCKEN, SAI_XCR1_MCKEN); + } + + static void stm32_sai_mclk_disable(struct clk_hw *hw) +@@ -383,7 +433,7 @@ static void stm32_sai_mclk_disable(struc + + dev_dbg(&sai->pdev->dev, "Disable master clock\n"); + +- regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0); ++ stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0); + } + + static const struct clk_ops mclk_ops = { +@@ -446,15 +496,15 @@ static irqreturn_t stm32_sai_isr(int irq + unsigned int sr, imr, flags; + snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING; + +- regmap_read(sai->regmap, STM_SAI_IMR_REGX, &imr); +- regmap_read(sai->regmap, STM_SAI_SR_REGX, &sr); ++ stm32_sai_sub_reg_rd(sai, STM_SAI_IMR_REGX, &imr); ++ stm32_sai_sub_reg_rd(sai, STM_SAI_SR_REGX, &sr); + + flags = sr & imr; + if (!flags) + return IRQ_NONE; + +- regmap_write_bits(sai->regmap, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK, +- SAI_XCLRFR_MASK); ++ stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK, ++ SAI_XCLRFR_MASK); + + if (!sai->substream) { + dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr); +@@ -503,8 +553,8 @@ static int stm32_sai_set_sysclk(struct s + int ret; + + if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) { +- ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, +- SAI_XCR1_NODIV, ++ ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, ++ SAI_XCR1_NODIV, + freq ? 0 : SAI_XCR1_NODIV); + if (ret < 0) + return ret; +@@ -583,7 +633,7 @@ static int stm32_sai_set_dai_tdm_slot(st + + slotr_mask |= SAI_XSLOTR_SLOTEN_MASK; + +- regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, slotr_mask, slotr); ++ stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, slotr_mask, slotr); + + sai->slot_width = slot_width; + sai->slots = slots; +@@ -665,7 +715,7 @@ static int stm32_sai_set_dai_fmt(struct + cr1_mask |= SAI_XCR1_CKSTR; + frcr_mask |= SAI_XFRCR_FSPOL; + +- regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr); ++ stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr); + + /* DAI clock master masks */ + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { +@@ -693,7 +743,7 @@ static int stm32_sai_set_dai_fmt(struct + cr1_mask |= SAI_XCR1_SLAVE; + + conf_update: +- ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); ++ ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1); + if (ret < 0) { + dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); + return ret; +@@ -730,12 +780,12 @@ static int stm32_sai_startup(struct snd_ + } + + /* Enable ITs */ +- regmap_write_bits(sai->regmap, STM_SAI_CLRFR_REGX, +- SAI_XCLRFR_MASK, SAI_XCLRFR_MASK); ++ stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX, ++ SAI_XCLRFR_MASK, SAI_XCLRFR_MASK); + + imr = SAI_XIMR_OVRUDRIE; + if (STM_SAI_IS_CAPTURE(sai)) { +- regmap_read(sai->regmap, STM_SAI_CR2_REGX, &cr2); ++ stm32_sai_sub_reg_rd(sai, STM_SAI_CR2_REGX, &cr2); + if (cr2 & SAI_XCR2_MUTECNT_MASK) + imr |= SAI_XIMR_MUTEDETIE; + } +@@ -745,8 +795,8 @@ static int stm32_sai_startup(struct snd_ + else + imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE; + +- regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, +- SAI_XIMR_MASK, imr); ++ stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, ++ SAI_XIMR_MASK, imr); + + return 0; + } +@@ -763,10 +813,10 @@ static int stm32_sai_set_config(struct s + * SAI fifo threshold is set to half fifo, to keep enough space + * for DMA incoming bursts. + */ +- regmap_write_bits(sai->regmap, STM_SAI_CR2_REGX, +- SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK, +- SAI_XCR2_FFLUSH | +- SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF)); ++ stm32_sai_sub_reg_wr(sai, STM_SAI_CR2_REGX, ++ SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK, ++ SAI_XCR2_FFLUSH | ++ SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF)); + + /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/ + if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { +@@ -795,7 +845,7 @@ static int stm32_sai_set_config(struct s + if ((sai->slots == 2) && (params_channels(params) == 1)) + cr1 |= SAI_XCR1_MONO; + +- ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); ++ ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1); + if (ret < 0) { + dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); + return ret; +@@ -809,7 +859,7 @@ static int stm32_sai_set_slots(struct sn + struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); + int slotr, slot_sz; + +- regmap_read(sai->regmap, STM_SAI_SLOTR_REGX, &slotr); ++ stm32_sai_sub_reg_rd(sai, STM_SAI_SLOTR_REGX, &slotr); + + /* + * If SLOTSZ is set to auto in SLOTR, align slot width on data size +@@ -831,16 +881,16 @@ static int stm32_sai_set_slots(struct sn + sai->slots = 2; + + /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/ +- regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, +- SAI_XSLOTR_NBSLOT_MASK, +- SAI_XSLOTR_NBSLOT_SET((sai->slots - 1))); ++ stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, ++ SAI_XSLOTR_NBSLOT_MASK, ++ SAI_XSLOTR_NBSLOT_SET((sai->slots - 1))); + + /* Set default slots mask if not already set from DT */ + if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) { + sai->slot_mask = (1 << sai->slots) - 1; +- regmap_update_bits(sai->regmap, +- STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK, +- SAI_XSLOTR_SLOTEN_SET(sai->slot_mask)); ++ stm32_sai_sub_reg_up(sai, ++ STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK, ++ SAI_XSLOTR_SLOTEN_SET(sai->slot_mask)); + } + + dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n", +@@ -870,14 +920,14 @@ static void stm32_sai_set_frame(struct s + dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n", + sai->fs_length, fs_active); + +- regmap_update_bits(sai->regmap, STM_SAI_FRCR_REGX, frcr_mask, frcr); ++ stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr); + + if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) { + offset = sai->slot_width - sai->data_size; + +- regmap_update_bits(sai->regmap, STM_SAI_SLOTR_REGX, +- SAI_XSLOTR_FBOFF_MASK, +- SAI_XSLOTR_FBOFF_SET(offset)); ++ stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, ++ SAI_XSLOTR_FBOFF_MASK, ++ SAI_XSLOTR_FBOFF_SET(offset)); + } + } + +@@ -994,9 +1044,9 @@ static int stm32_sai_configure_clock(str + return -EINVAL; + } + +- regmap_update_bits(sai->regmap, +- STM_SAI_CR1_REGX, +- SAI_XCR1_OSR, cr1); ++ stm32_sai_sub_reg_up(sai, ++ STM_SAI_CR1_REGX, ++ SAI_XCR1_OSR, cr1); + + div = stm32_sai_get_clk_div(sai, sai_clk_rate, + sai->mclk_rate); +@@ -1058,12 +1108,12 @@ static int stm32_sai_trigger(struct snd_ + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n"); + +- regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, +- SAI_XCR1_DMAEN, SAI_XCR1_DMAEN); ++ stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, ++ SAI_XCR1_DMAEN, SAI_XCR1_DMAEN); + + /* Enable SAI */ +- ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, +- SAI_XCR1_SAIEN, SAI_XCR1_SAIEN); ++ ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, ++ SAI_XCR1_SAIEN, SAI_XCR1_SAIEN); + if (ret < 0) + dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); + break; +@@ -1072,16 +1122,16 @@ static int stm32_sai_trigger(struct snd_ + case SNDRV_PCM_TRIGGER_STOP: + dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n"); + +- regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, +- SAI_XIMR_MASK, 0); ++ stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, ++ SAI_XIMR_MASK, 0); + +- regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, +- SAI_XCR1_SAIEN, +- (unsigned int)~SAI_XCR1_SAIEN); +- +- ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, +- SAI_XCR1_DMAEN, +- (unsigned int)~SAI_XCR1_DMAEN); ++ stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, ++ SAI_XCR1_SAIEN, ++ (unsigned int)~SAI_XCR1_SAIEN); ++ ++ ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, ++ SAI_XCR1_DMAEN, ++ (unsigned int)~SAI_XCR1_DMAEN); + if (ret < 0) + dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); + +@@ -1101,7 +1151,7 @@ static void stm32_sai_shutdown(struct sn + struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); + unsigned long flags; + +- regmap_update_bits(sai->regmap, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0); ++ stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0); + + clk_disable_unprepare(sai->sai_ck); + +@@ -1169,7 +1219,7 @@ static int stm32_sai_dai_probe(struct sn + cr1_mask |= SAI_XCR1_SYNCEN_MASK; + cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync); + +- return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, cr1_mask, cr1); ++ return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1); + } + + static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = { +@@ -1322,8 +1372,13 @@ static int stm32_sai_sub_parse_of(struct + if (STM_SAI_HAS_PDM(sai) && STM_SAI_IS_SUB_A(sai)) + sai->regmap_config = &stm32_sai_sub_regmap_config_h7; + +- sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "sai_ck", +- base, sai->regmap_config); ++ /* ++ * Do not manage peripheral clock through regmap framework as this ++ * can lead to circular locking issue with sai master clock provider. ++ * Manage peripheral clock directly in driver instead. ++ */ ++ sai->regmap = devm_regmap_init_mmio(&pdev->dev, base, ++ sai->regmap_config); + if (IS_ERR(sai->regmap)) { + dev_err(&pdev->dev, "Failed to initialize MMIO\n"); + return PTR_ERR(sai->regmap); +@@ -1420,6 +1475,10 @@ static int stm32_sai_sub_parse_of(struct + return PTR_ERR(sai->sai_ck); + } + ++ ret = clk_prepare(sai->pdata->pclk); ++ if (ret < 0) ++ return ret; ++ + if (STM_SAI_IS_F4(sai->pdata)) + return 0; + +@@ -1501,22 +1560,48 @@ static int stm32_sai_sub_probe(struct pl + return 0; + } + ++static int stm32_sai_sub_remove(struct platform_device *pdev) ++{ ++ struct stm32_sai_sub_data *sai = dev_get_drvdata(&pdev->dev); ++ ++ clk_unprepare(sai->pdata->pclk); ++ ++ return 0; ++} ++ + #ifdef CONFIG_PM_SLEEP + static int stm32_sai_sub_suspend(struct device *dev) + { + struct stm32_sai_sub_data *sai = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = clk_enable(sai->pdata->pclk); ++ if (ret < 0) ++ return ret; + + regcache_cache_only(sai->regmap, true); + regcache_mark_dirty(sai->regmap); ++ ++ clk_disable(sai->pdata->pclk); ++ + return 0; + } + + static int stm32_sai_sub_resume(struct device *dev) + { + struct stm32_sai_sub_data *sai = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = clk_enable(sai->pdata->pclk); ++ if (ret < 0) ++ return ret; + + regcache_cache_only(sai->regmap, false); +- return regcache_sync(sai->regmap); ++ ret = regcache_sync(sai->regmap); ++ ++ clk_disable(sai->pdata->pclk); ++ ++ return ret; + } + #endif /* CONFIG_PM_SLEEP */ + +@@ -1531,6 +1616,7 @@ static struct platform_driver stm32_sai_ + .pm = &stm32_sai_sub_pm_ops, + }, + .probe = stm32_sai_sub_probe, ++ .remove = stm32_sai_sub_remove, + }; + + module_platform_driver(stm32_sai_sub_driver); diff --git a/queue-5.4/block-fix-an-integer-overflow-in-logical-block-size.patch b/queue-5.4/block-fix-an-integer-overflow-in-logical-block-size.patch new file mode 100644 index 00000000000..5bfef4f36ef --- /dev/null +++ b/queue-5.4/block-fix-an-integer-overflow-in-logical-block-size.patch @@ -0,0 +1,116 @@ +From ad6bf88a6c19a39fb3b0045d78ea880325dfcf15 Mon Sep 17 00:00:00 2001 +From: Mikulas Patocka +Date: Wed, 15 Jan 2020 08:35:25 -0500 +Subject: block: fix an integer overflow in logical block size + +From: Mikulas Patocka + +commit ad6bf88a6c19a39fb3b0045d78ea880325dfcf15 upstream. + +Logical block size has type unsigned short. That means that it can be at +most 32768. However, there are architectures that can run with 64k pages +(for example arm64) and on these architectures, it may be possible to +create block devices with 64k block size. + +For exmaple (run this on an architecture with 64k pages): + +Mount will fail with this error because it tries to read the superblock using 2-sector +access: + device-mapper: writecache: I/O is not aligned, sector 2, size 1024, block size 65536 + EXT4-fs (dm-0): unable to read superblock + +This patch changes the logical block size from unsigned short to unsigned +int to avoid the overflow. + +Cc: stable@vger.kernel.org +Reviewed-by: Martin K. Petersen +Reviewed-by: Ming Lei +Signed-off-by: Mikulas Patocka +Signed-off-by: Jens Axboe +Signed-off-by: Greg Kroah-Hartman + +--- + block/blk-settings.c | 2 +- + drivers/md/dm-snap-persistent.c | 2 +- + drivers/md/raid0.c | 2 +- + include/linux/blkdev.h | 8 ++++---- + 4 files changed, 7 insertions(+), 7 deletions(-) + +--- a/block/blk-settings.c ++++ b/block/blk-settings.c +@@ -328,7 +328,7 @@ EXPORT_SYMBOL(blk_queue_max_segment_size + * storage device can address. The default of 512 covers most + * hardware. + **/ +-void blk_queue_logical_block_size(struct request_queue *q, unsigned short size) ++void blk_queue_logical_block_size(struct request_queue *q, unsigned int size) + { + q->limits.logical_block_size = size; + +--- a/drivers/md/dm-snap-persistent.c ++++ b/drivers/md/dm-snap-persistent.c +@@ -17,7 +17,7 @@ + #include + + #define DM_MSG_PREFIX "persistent snapshot" +-#define DM_CHUNK_SIZE_DEFAULT_SECTORS 32 /* 16KB */ ++#define DM_CHUNK_SIZE_DEFAULT_SECTORS 32U /* 16KB */ + + #define DM_PREFETCH_CHUNKS 12 + +--- a/drivers/md/raid0.c ++++ b/drivers/md/raid0.c +@@ -87,7 +87,7 @@ static int create_strip_zones(struct mdd + char b[BDEVNAME_SIZE]; + char b2[BDEVNAME_SIZE]; + struct r0conf *conf = kzalloc(sizeof(*conf), GFP_KERNEL); +- unsigned short blksize = 512; ++ unsigned blksize = 512; + + *private_conf = ERR_PTR(-ENOMEM); + if (!conf) +--- a/include/linux/blkdev.h ++++ b/include/linux/blkdev.h +@@ -328,6 +328,7 @@ struct queue_limits { + unsigned int max_sectors; + unsigned int max_segment_size; + unsigned int physical_block_size; ++ unsigned int logical_block_size; + unsigned int alignment_offset; + unsigned int io_min; + unsigned int io_opt; +@@ -338,7 +339,6 @@ struct queue_limits { + unsigned int discard_granularity; + unsigned int discard_alignment; + +- unsigned short logical_block_size; + unsigned short max_segments; + unsigned short max_integrity_segments; + unsigned short max_discard_segments; +@@ -1080,7 +1080,7 @@ extern void blk_queue_max_write_same_sec + unsigned int max_write_same_sectors); + extern void blk_queue_max_write_zeroes_sectors(struct request_queue *q, + unsigned int max_write_same_sectors); +-extern void blk_queue_logical_block_size(struct request_queue *, unsigned short); ++extern void blk_queue_logical_block_size(struct request_queue *, unsigned int); + extern void blk_queue_physical_block_size(struct request_queue *, unsigned int); + extern void blk_queue_alignment_offset(struct request_queue *q, + unsigned int alignment); +@@ -1294,7 +1294,7 @@ static inline unsigned int queue_max_seg + return q->limits.max_segment_size; + } + +-static inline unsigned short queue_logical_block_size(const struct request_queue *q) ++static inline unsigned queue_logical_block_size(const struct request_queue *q) + { + int retval = 512; + +@@ -1304,7 +1304,7 @@ static inline unsigned short queue_logic + return retval; + } + +-static inline unsigned short bdev_logical_block_size(struct block_device *bdev) ++static inline unsigned int bdev_logical_block_size(struct block_device *bdev) + { + return queue_logical_block_size(bdev_get_queue(bdev)); + } diff --git a/queue-5.4/bus-ti-sysc-fix-iterating-over-clocks.patch b/queue-5.4/bus-ti-sysc-fix-iterating-over-clocks.patch new file mode 100644 index 00000000000..ff0bbd96028 --- /dev/null +++ b/queue-5.4/bus-ti-sysc-fix-iterating-over-clocks.patch @@ -0,0 +1,64 @@ +From 2c81f0f6d3f52ac222a5dc07a6e5c06e1543e88b Mon Sep 17 00:00:00 2001 +From: Tony Lindgren +Date: Mon, 16 Dec 2019 14:41:53 -0800 +Subject: bus: ti-sysc: Fix iterating over clocks + +From: Tony Lindgren + +commit 2c81f0f6d3f52ac222a5dc07a6e5c06e1543e88b upstream. + +Commit d878970f6ce1 ("bus: ti-sysc: Add separate functions for handling +clocks") separated handling of optional clocks from the main clocks, but +introduced an issue where we do not necessarily allocate a slot for both +fck and ick clocks, but still assume fixed slots for enumerating over the +clocks. + +Let's fix the issue by ensuring we always have slots for both fck and ick +even if we don't use ick, and don't attempt to enumerate optional clocks +if not allocated. + +In the long run we might want to simplify things a bit by only allocating +space only for the optional clocks as we have only few devices with +optional clocks. + +Fixes: d878970f6ce1 ("bus: ti-sysc: Add separate functions for handling clocks") +Signed-off-by: Tony Lindgren +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/bus/ti-sysc.c | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +--- a/drivers/bus/ti-sysc.c ++++ b/drivers/bus/ti-sysc.c +@@ -343,6 +343,12 @@ static int sysc_get_clocks(struct sysc * + return -EINVAL; + } + ++ /* Always add a slot for main clocks fck and ick even if unused */ ++ if (!nr_fck) ++ ddata->nr_clocks++; ++ if (!nr_ick) ++ ddata->nr_clocks++; ++ + ddata->clocks = devm_kcalloc(ddata->dev, + ddata->nr_clocks, sizeof(*ddata->clocks), + GFP_KERNEL); +@@ -421,7 +427,7 @@ static int sysc_enable_opt_clocks(struct + struct clk *clock; + int i, error; + +- if (!ddata->clocks) ++ if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) + return 0; + + for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { +@@ -455,7 +461,7 @@ static void sysc_disable_opt_clocks(stru + struct clk *clock; + int i; + +- if (!ddata->clocks) ++ if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) + return; + + for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { diff --git a/queue-5.4/clk-don-t-try-to-enable-critical-clocks-if-prepare-failed.patch b/queue-5.4/clk-don-t-try-to-enable-critical-clocks-if-prepare-failed.patch new file mode 100644 index 00000000000..c6c856b029c --- /dev/null +++ b/queue-5.4/clk-don-t-try-to-enable-critical-clocks-if-prepare-failed.patch @@ -0,0 +1,65 @@ +From 12ead77432f2ce32dea797742316d15c5800cb32 Mon Sep 17 00:00:00 2001 +From: Guenter Roeck +Date: Wed, 25 Dec 2019 08:34:29 -0800 +Subject: clk: Don't try to enable critical clocks if prepare failed + +From: Guenter Roeck + +commit 12ead77432f2ce32dea797742316d15c5800cb32 upstream. + +The following traceback is seen if a critical clock fails to prepare. + +bcm2835-clk 3f101000.cprman: plld: couldn't lock PLL +------------[ cut here ]------------ +Enabling unprepared plld_per +WARNING: CPU: 1 PID: 1 at drivers/clk/clk.c:1014 clk_core_enable+0xcc/0x2c0 +... +Call trace: + clk_core_enable+0xcc/0x2c0 + __clk_register+0x5c4/0x788 + devm_clk_hw_register+0x4c/0xb0 + bcm2835_register_pll_divider+0xc0/0x150 + bcm2835_clk_probe+0x134/0x1e8 + platform_drv_probe+0x50/0xa0 + really_probe+0xd4/0x308 + driver_probe_device+0x54/0xe8 + device_driver_attach+0x6c/0x78 + __driver_attach+0x54/0xd8 +... + +Check return values from clk_core_prepare() and clk_core_enable() and +bail out if any of those functions returns an error. + +Cc: Jerome Brunet +Fixes: 99652a469df1 ("clk: migrate the count of orphaned clocks at init") +Signed-off-by: Guenter Roeck +Link: https://lkml.kernel.org/r/20191225163429.29694-1-linux@roeck-us.net +Signed-off-by: Stephen Boyd +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/clk/clk.c | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +--- a/drivers/clk/clk.c ++++ b/drivers/clk/clk.c +@@ -3408,11 +3408,17 @@ static int __clk_core_init(struct clk_co + if (core->flags & CLK_IS_CRITICAL) { + unsigned long flags; + +- clk_core_prepare(core); ++ ret = clk_core_prepare(core); ++ if (ret) ++ goto out; + + flags = clk_enable_lock(); +- clk_core_enable(core); ++ ret = clk_core_enable(core); + clk_enable_unlock(flags); ++ if (ret) { ++ clk_core_unprepare(core); ++ goto out; ++ } + } + + clk_core_reparent_orphans_nolock(); diff --git a/queue-5.4/clk-qcom-gcc-sdm845-add-missing-flag-to-votable-gdscs.patch b/queue-5.4/clk-qcom-gcc-sdm845-add-missing-flag-to-votable-gdscs.patch new file mode 100644 index 00000000000..91fd3c12d81 --- /dev/null +++ b/queue-5.4/clk-qcom-gcc-sdm845-add-missing-flag-to-votable-gdscs.patch @@ -0,0 +1,96 @@ +From 5e82548e26ef62e257dc2ff37c11acb5eb72728e Mon Sep 17 00:00:00 2001 +From: Georgi Djakov +Date: Tue, 26 Nov 2019 17:34:37 +0200 +Subject: clk: qcom: gcc-sdm845: Add missing flag to votable GDSCs + +From: Georgi Djakov + +commit 5e82548e26ef62e257dc2ff37c11acb5eb72728e upstream. + +On sdm845 devices, during boot we see the following warnings (unless we +have added 'pd_ignore_unused' to the kernel command line): + hlos1_vote_mmnoc_mmu_tbu_sf_gdsc status stuck at 'on' + hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc status stuck at 'on' + hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc status stuck at 'on' + hlos1_vote_aggre_noc_mmu_tbu2_gdsc status stuck at 'on' + hlos1_vote_aggre_noc_mmu_tbu1_gdsc status stuck at 'on' + hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc status stuck at 'on' + hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc status stuck at 'on' + +As the name of these GDSCs suggests, they are "votable" and in downstream +DT, they all have the property "qcom,no-status-check-on-disable", which +means that we should not poll the status bit when we disable them. + +Luckily the VOTABLE flag already exists and it does exactly what we need, +so let's make use of it to make the warnings disappear. + +Fixes: 06391eddb60a ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845") +Reported-by: Rob Clark +Signed-off-by: Georgi Djakov +Link: https://lkml.kernel.org/r/20191126153437.11808-1-georgi.djakov@linaro.org +Tested-by: Rob Clark +Signed-off-by: Stephen Boyd +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/clk/qcom/gcc-sdm845.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/drivers/clk/qcom/gcc-sdm845.c ++++ b/drivers/clk/qcom/gcc-sdm845.c +@@ -3255,6 +3255,7 @@ static struct gdsc hlos1_vote_aggre_noc_ + .name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, ++ .flags = VOTABLE, + }; + + static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = { +@@ -3263,6 +3264,7 @@ static struct gdsc hlos1_vote_aggre_noc_ + .name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, ++ .flags = VOTABLE, + }; + + static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = { +@@ -3271,6 +3273,7 @@ static struct gdsc hlos1_vote_aggre_noc_ + .name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, ++ .flags = VOTABLE, + }; + + static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = { +@@ -3279,6 +3282,7 @@ static struct gdsc hlos1_vote_aggre_noc_ + .name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, ++ .flags = VOTABLE, + }; + + static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = { +@@ -3287,6 +3291,7 @@ static struct gdsc hlos1_vote_mmnoc_mmu_ + .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, ++ .flags = VOTABLE, + }; + + static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = { +@@ -3295,6 +3300,7 @@ static struct gdsc hlos1_vote_mmnoc_mmu_ + .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, ++ .flags = VOTABLE, + }; + + static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = { +@@ -3303,6 +3309,7 @@ static struct gdsc hlos1_vote_mmnoc_mmu_ + .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, ++ .flags = VOTABLE, + }; + + static struct clk_regmap *gcc_sdm845_clocks[] = { diff --git a/queue-5.4/clk-sunxi-ng-r40-allow-setting-parent-rate-for-external-clock-outputs.patch b/queue-5.4/clk-sunxi-ng-r40-allow-setting-parent-rate-for-external-clock-outputs.patch new file mode 100644 index 00000000000..192fa699f42 --- /dev/null +++ b/queue-5.4/clk-sunxi-ng-r40-allow-setting-parent-rate-for-external-clock-outputs.patch @@ -0,0 +1,50 @@ +From c7b305267eb77fe47498676e9337324c9653494c Mon Sep 17 00:00:00 2001 +From: Chen-Yu Tsai +Date: Wed, 18 Dec 2019 11:04:31 +0800 +Subject: clk: sunxi-ng: r40: Allow setting parent rate for external clock outputs + +From: Chen-Yu Tsai + +commit c7b305267eb77fe47498676e9337324c9653494c upstream. + +One of the uses of the external clock outputs is to provide a stable +32768 Hz clock signal to WiFi and Bluetooth chips. On the R40, the RTC +has an internal RC oscillator that is muxed with the external crystal. + +Allow setting the parent rate for the external clock outputs so that +requests for 32768 Hz get passed to the RTC's clock driver to mux in +the external crystal if it isn't already muxed correctly. + +Fixes: cd030a78f7aa ("clk: sunxi-ng: support R40 SoC") +Fixes: 01a7ea763fc4 ("clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output") +Cc: +Signed-off-by: Chen-Yu Tsai +Signed-off-by: Maxime Ripard +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c ++++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c +@@ -761,7 +761,8 @@ static struct ccu_mp outa_clk = { + .reg = 0x1f0, + .features = CCU_FEATURE_FIXED_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("outa", out_parents, +- &ccu_mp_ops, 0), ++ &ccu_mp_ops, ++ CLK_SET_RATE_PARENT), + } + }; + +@@ -779,7 +780,8 @@ static struct ccu_mp outb_clk = { + .reg = 0x1f4, + .features = CCU_FEATURE_FIXED_PREDIV, + .hw.init = CLK_HW_INIT_PARENTS("outb", out_parents, +- &ccu_mp_ops, 0), ++ &ccu_mp_ops, ++ CLK_SET_RATE_PARENT), + } + }; + diff --git a/queue-5.4/cpuidle-teo-fix-intervals-array-indexing-bug.patch b/queue-5.4/cpuidle-teo-fix-intervals-array-indexing-bug.patch new file mode 100644 index 00000000000..0c54c913d29 --- /dev/null +++ b/queue-5.4/cpuidle-teo-fix-intervals-array-indexing-bug.patch @@ -0,0 +1,32 @@ +From 57388a2ccb6c2f554fee39772886c69b796dde53 Mon Sep 17 00:00:00 2001 +From: Ikjoon Jang +Date: Sat, 11 Jan 2020 01:47:12 +0800 +Subject: cpuidle: teo: Fix intervals[] array indexing bug + +From: Ikjoon Jang + +commit 57388a2ccb6c2f554fee39772886c69b796dde53 upstream. + +Fix a simple bug in rotating array index. + +Fixes: b26bf6ab716f ("cpuidle: New timer events oriented governor for tickless systems") +Signed-off-by: Ikjoon Jang +Cc: 5.1+ # 5.1+ +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/cpuidle/governors/teo.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/cpuidle/governors/teo.c ++++ b/drivers/cpuidle/governors/teo.c +@@ -194,7 +194,7 @@ static void teo_update(struct cpuidle_dr + * pattern detection. + */ + cpu_data->intervals[cpu_data->interval_idx++] = measured_us; +- if (cpu_data->interval_idx > INTERVALS) ++ if (cpu_data->interval_idx >= INTERVALS) + cpu_data->interval_idx = 0; + } + diff --git a/queue-5.4/dt-bindings-reset-meson8b-fix-duplicate-reset-ids.patch b/queue-5.4/dt-bindings-reset-meson8b-fix-duplicate-reset-ids.patch new file mode 100644 index 00000000000..07d239cc81d --- /dev/null +++ b/queue-5.4/dt-bindings-reset-meson8b-fix-duplicate-reset-ids.patch @@ -0,0 +1,42 @@ +From 4881873f4cc1460f63d85fa81363d56be328ccdc Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sat, 30 Nov 2019 19:53:37 +0100 +Subject: dt-bindings: reset: meson8b: fix duplicate reset IDs + +From: Martin Blumenstingl + +commit 4881873f4cc1460f63d85fa81363d56be328ccdc upstream. + +According to the public S805 datasheet the RESET2 register uses the +following bits for the PIC_DC, PSC and NAND reset lines: +- PIC_DC is at bit 3 (meaning: RESET_VD_RMEM + 3) +- PSC is at bit 4 (meaning: RESET_VD_RMEM + 4) +- NAND is at bit 5 (meaning: RESET_VD_RMEM + 4) + +Update the reset IDs of these three reset lines so they don't conflict +with PIC_DC and map to the actual hardware reset lines. + +Fixes: 79795e20a184eb ("dt-bindings: reset: Add bindings for the Meson SoC Reset Controller") +Signed-off-by: Martin Blumenstingl +Signed-off-by: Kevin Hilman +Signed-off-by: Greg Kroah-Hartman + +--- + include/dt-bindings/reset/amlogic,meson8b-reset.h | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/include/dt-bindings/reset/amlogic,meson8b-reset.h ++++ b/include/dt-bindings/reset/amlogic,meson8b-reset.h +@@ -46,9 +46,9 @@ + #define RESET_VD_RMEM 64 + #define RESET_AUDIN 65 + #define RESET_DBLK 66 +-#define RESET_PIC_DC 66 +-#define RESET_PSC 66 +-#define RESET_NAND 66 ++#define RESET_PIC_DC 67 ++#define RESET_PSC 68 ++#define RESET_NAND 69 + #define RESET_GE2D 70 + #define RESET_PARSER_REG 71 + #define RESET_PARSER_FETCH 72 diff --git a/queue-5.4/fix-built-in-early-load-intel-microcode-alignment.patch b/queue-5.4/fix-built-in-early-load-intel-microcode-alignment.patch new file mode 100644 index 00000000000..22414426854 --- /dev/null +++ b/queue-5.4/fix-built-in-early-load-intel-microcode-alignment.patch @@ -0,0 +1,54 @@ +From f5ae2ea6347a308cfe91f53b53682ce635497d0d Mon Sep 17 00:00:00 2001 +From: Jari Ruusu +Date: Sun, 12 Jan 2020 15:00:53 +0200 +Subject: Fix built-in early-load Intel microcode alignment + +From: Jari Ruusu + +commit f5ae2ea6347a308cfe91f53b53682ce635497d0d upstream. + +Intel Software Developer's Manual, volume 3, chapter 9.11.6 says: + + "Note that the microcode update must be aligned on a 16-byte boundary + and the size of the microcode update must be 1-KByte granular" + +When early-load Intel microcode is loaded from initramfs, userspace tool +'iucode_tool' has already 16-byte aligned those microcode bits in that +initramfs image. Image that was created something like this: + + iucode_tool --write-earlyfw=FOO.cpio microcode-files... + +However, when early-load Intel microcode is loaded from built-in +firmware BLOB using CONFIG_EXTRA_FIRMWARE= kernel config option, that +16-byte alignment is not guaranteed. + +Fix this by forcing all built-in firmware BLOBs to 16-byte alignment. + +[ If we end up having other firmware with much bigger alignment + requirements, we might need to introduce some method for the firmware + to specify it, this is the minimal "just increase the alignment a bit + to account for this one special case" patch - Linus ] + +Signed-off-by: Jari Ruusu +Cc: Borislav Petkov +Cc: Fenghua Yu +Cc: Luis Chamberlain +Cc: stable@kernel.org +Signed-off-by: Linus Torvalds +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/base/firmware_loader/builtin/Makefile | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/base/firmware_loader/builtin/Makefile ++++ b/drivers/base/firmware_loader/builtin/Makefile +@@ -17,7 +17,7 @@ PROGBITS = $(if $(CONFIG_ARM),%,@)progb + filechk_fwbin = \ + echo "/* Generated by $(src)/Makefile */" ;\ + echo " .section .rodata" ;\ +- echo " .p2align $(ASM_ALIGN)" ;\ ++ echo " .p2align 4" ;\ + echo "_fw_$(FWSTR)_bin:" ;\ + echo " .incbin \"$(fwdir)/$(FWNAME)\"" ;\ + echo "_fw_end:" ;\ diff --git a/queue-5.4/fuse-fix-fuse_send_readpages-in-the-syncronous-read-case.patch b/queue-5.4/fuse-fix-fuse_send_readpages-in-the-syncronous-read-case.patch new file mode 100644 index 00000000000..dec48717758 --- /dev/null +++ b/queue-5.4/fuse-fix-fuse_send_readpages-in-the-syncronous-read-case.patch @@ -0,0 +1,61 @@ +From 7df1e988c723a066754090b22d047c3225342152 Mon Sep 17 00:00:00 2001 +From: Miklos Szeredi +Date: Thu, 16 Jan 2020 11:09:36 +0100 +Subject: fuse: fix fuse_send_readpages() in the syncronous read case + +From: Miklos Szeredi + +commit 7df1e988c723a066754090b22d047c3225342152 upstream. + +Buffered read in fuse normally goes via: + + -> generic_file_buffered_read() + -> fuse_readpages() + -> fuse_send_readpages() + ->fuse_simple_request() [called since v5.4] + +In the case of a read request, fuse_simple_request() will return a +non-negative bytecount on success or a negative error value. A positive +bytecount was taken to be an error and the PG_error flag set on the page. +This resulted in generic_file_buffered_read() falling back to ->readpage(), +which would repeat the read request and succeed. Because of the repeated +read succeeding the bug was not detected with regression tests or other use +cases. + +The FTP module in GVFS however fails the second read due to the +non-seekable nature of FTP downloads. + +Fix by checking and ignoring positive return value from +fuse_simple_request(). + +Reported-by: Ondrej Holy +Link: https://gitlab.gnome.org/GNOME/gvfs/issues/441 +Fixes: 134831e36bbd ("fuse: convert readpages to simple api") +Cc: # v5.4 +Signed-off-by: Miklos Szeredi +Signed-off-by: Greg Kroah-Hartman + +--- + fs/fuse/file.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/fs/fuse/file.c ++++ b/fs/fuse/file.c +@@ -882,6 +882,7 @@ static void fuse_send_readpages(struct f + struct fuse_args_pages *ap = &ia->ap; + loff_t pos = page_offset(ap->pages[0]); + size_t count = ap->num_pages << PAGE_SHIFT; ++ ssize_t res; + int err; + + ap->args.out_pages = true; +@@ -896,7 +897,8 @@ static void fuse_send_readpages(struct f + if (!err) + return; + } else { +- err = fuse_simple_request(fc, &ap->args); ++ res = fuse_simple_request(fc, &ap->args); ++ err = res < 0 ? res : 0; + } + fuse_readpages_end(fc, &ap->args, err); + } diff --git a/queue-5.4/io_uring-only-allow-submit-from-owning-task.patch b/queue-5.4/io_uring-only-allow-submit-from-owning-task.patch new file mode 100644 index 00000000000..bbcc47b4ce3 --- /dev/null +++ b/queue-5.4/io_uring-only-allow-submit-from-owning-task.patch @@ -0,0 +1,39 @@ +From 44d282796f81eb1debc1d7cb53245b4cb3214cb5 Mon Sep 17 00:00:00 2001 +From: Jens Axboe +Date: Thu, 16 Jan 2020 19:00:24 -0700 +Subject: io_uring: only allow submit from owning task + +From: Jens Axboe + +commit 44d282796f81eb1debc1d7cb53245b4cb3214cb5 upstream. + +If the credentials or the mm doesn't match, don't allow the task to +submit anything on behalf of this ring. The task that owns the ring can +pass the file descriptor to another task, but we don't want to allow +that task to submit an SQE that then assumes the ring mm and creds if +it needs to go async. + +Cc: stable@vger.kernel.org +Suggested-by: Stefan Metzmacher +Signed-off-by: Jens Axboe +Signed-off-by: Greg Kroah-Hartman + +--- + fs/io_uring.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/fs/io_uring.c ++++ b/fs/io_uring.c +@@ -2798,6 +2798,12 @@ static int io_sq_thread(void *data) + } + } + ++ if (current->mm != ctx->sqo_mm || ++ current_cred() != ctx->creds) { ++ ret = -EPERM; ++ goto out; ++ } ++ + to_submit = min(to_submit, ctx->sq_entries); + inflight += io_submit_sqes(ctx, to_submit, cur_mm != NULL, + mm_fault); diff --git a/queue-5.4/revert-gpio-thunderx-switch-to-gpiolib_irqchip.patch b/queue-5.4/revert-gpio-thunderx-switch-to-gpiolib_irqchip.patch new file mode 100644 index 00000000000..cda7ef08cc4 --- /dev/null +++ b/queue-5.4/revert-gpio-thunderx-switch-to-gpiolib_irqchip.patch @@ -0,0 +1,307 @@ +From a564ac35d60564dd5b509e32afdc04e7aafee40e Mon Sep 17 00:00:00 2001 +From: Kevin Hao +Date: Tue, 14 Jan 2020 16:28:18 +0800 +Subject: Revert "gpio: thunderx: Switch to GPIOLIB_IRQCHIP" + +From: Kevin Hao + +commit a564ac35d60564dd5b509e32afdc04e7aafee40e upstream. + +This reverts commit a7fc89f9d5fcc10a5474cfe555f5a9e5df8b0f1f because +there are some bugs in this commit, and we don't have a simple way to +fix these bugs. So revert this commit to make the thunderx gpio work +on the stable kernel at least. We will switch to GPIOLIB_IRQCHIP +for thunderx gpio by following patches. + +Fixes: a7fc89f9d5fc ("gpio: thunderx: Switch to GPIOLIB_IRQCHIP") +Signed-off-by: Kevin Hao +Link: https://lore.kernel.org/r/20200114082821.14015-2-haokexin@gmail.com +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpio/Kconfig | 1 + drivers/gpio/gpio-thunderx.c | 163 ++++++++++++++++++++++++++++--------------- + 2 files changed, 107 insertions(+), 57 deletions(-) + +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -546,7 +546,6 @@ config GPIO_THUNDERX + tristate "Cavium ThunderX/OCTEON-TX GPIO" + depends on ARCH_THUNDER || (64BIT && COMPILE_TEST) + depends on PCI_MSI +- select GPIOLIB_IRQCHIP + select IRQ_DOMAIN_HIERARCHY + select IRQ_FASTEOI_HIERARCHY_HANDLERS + help +--- a/drivers/gpio/gpio-thunderx.c ++++ b/drivers/gpio/gpio-thunderx.c +@@ -53,6 +53,7 @@ struct thunderx_line { + struct thunderx_gpio { + struct gpio_chip chip; + u8 __iomem *register_base; ++ struct irq_domain *irqd; + struct msix_entry *msix_entries; /* per line MSI-X */ + struct thunderx_line *line_entries; /* per line irq info */ + raw_spinlock_t lock; +@@ -282,60 +283,54 @@ static void thunderx_gpio_set_multiple(s + } + } + +-static void thunderx_gpio_irq_ack(struct irq_data *d) ++static void thunderx_gpio_irq_ack(struct irq_data *data) + { +- struct gpio_chip *gc = irq_data_get_irq_chip_data(d); +- struct thunderx_gpio *txgpio = gpiochip_get_data(gc); ++ struct thunderx_line *txline = irq_data_get_irq_chip_data(data); + + writeq(GPIO_INTR_INTR, +- txgpio->register_base + intr_reg(irqd_to_hwirq(d))); ++ txline->txgpio->register_base + intr_reg(txline->line)); + } + +-static void thunderx_gpio_irq_mask(struct irq_data *d) ++static void thunderx_gpio_irq_mask(struct irq_data *data) + { +- struct gpio_chip *gc = irq_data_get_irq_chip_data(d); +- struct thunderx_gpio *txgpio = gpiochip_get_data(gc); ++ struct thunderx_line *txline = irq_data_get_irq_chip_data(data); + + writeq(GPIO_INTR_ENA_W1C, +- txgpio->register_base + intr_reg(irqd_to_hwirq(d))); ++ txline->txgpio->register_base + intr_reg(txline->line)); + } + +-static void thunderx_gpio_irq_mask_ack(struct irq_data *d) ++static void thunderx_gpio_irq_mask_ack(struct irq_data *data) + { +- struct gpio_chip *gc = irq_data_get_irq_chip_data(d); +- struct thunderx_gpio *txgpio = gpiochip_get_data(gc); ++ struct thunderx_line *txline = irq_data_get_irq_chip_data(data); + + writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR, +- txgpio->register_base + intr_reg(irqd_to_hwirq(d))); ++ txline->txgpio->register_base + intr_reg(txline->line)); + } + +-static void thunderx_gpio_irq_unmask(struct irq_data *d) ++static void thunderx_gpio_irq_unmask(struct irq_data *data) + { +- struct gpio_chip *gc = irq_data_get_irq_chip_data(d); +- struct thunderx_gpio *txgpio = gpiochip_get_data(gc); ++ struct thunderx_line *txline = irq_data_get_irq_chip_data(data); + + writeq(GPIO_INTR_ENA_W1S, +- txgpio->register_base + intr_reg(irqd_to_hwirq(d))); ++ txline->txgpio->register_base + intr_reg(txline->line)); + } + +-static int thunderx_gpio_irq_set_type(struct irq_data *d, ++static int thunderx_gpio_irq_set_type(struct irq_data *data, + unsigned int flow_type) + { +- struct gpio_chip *gc = irq_data_get_irq_chip_data(d); +- struct thunderx_gpio *txgpio = gpiochip_get_data(gc); +- struct thunderx_line *txline = +- &txgpio->line_entries[irqd_to_hwirq(d)]; ++ struct thunderx_line *txline = irq_data_get_irq_chip_data(data); ++ struct thunderx_gpio *txgpio = txline->txgpio; + u64 bit_cfg; + +- irqd_set_trigger_type(d, flow_type); ++ irqd_set_trigger_type(data, flow_type); + + bit_cfg = txline->fil_bits | GPIO_BIT_CFG_INT_EN; + + if (flow_type & IRQ_TYPE_EDGE_BOTH) { +- irq_set_handler_locked(d, handle_fasteoi_ack_irq); ++ irq_set_handler_locked(data, handle_fasteoi_ack_irq); + bit_cfg |= GPIO_BIT_CFG_INT_TYPE; + } else { +- irq_set_handler_locked(d, handle_fasteoi_mask_irq); ++ irq_set_handler_locked(data, handle_fasteoi_mask_irq); + } + + raw_spin_lock(&txgpio->lock); +@@ -364,6 +359,33 @@ static void thunderx_gpio_irq_disable(st + irq_chip_disable_parent(data); + } + ++static int thunderx_gpio_irq_request_resources(struct irq_data *data) ++{ ++ struct thunderx_line *txline = irq_data_get_irq_chip_data(data); ++ struct thunderx_gpio *txgpio = txline->txgpio; ++ int r; ++ ++ r = gpiochip_lock_as_irq(&txgpio->chip, txline->line); ++ if (r) ++ return r; ++ ++ r = irq_chip_request_resources_parent(data); ++ if (r) ++ gpiochip_unlock_as_irq(&txgpio->chip, txline->line); ++ ++ return r; ++} ++ ++static void thunderx_gpio_irq_release_resources(struct irq_data *data) ++{ ++ struct thunderx_line *txline = irq_data_get_irq_chip_data(data); ++ struct thunderx_gpio *txgpio = txline->txgpio; ++ ++ irq_chip_release_resources_parent(data); ++ ++ gpiochip_unlock_as_irq(&txgpio->chip, txline->line); ++} ++ + /* + * Interrupts are chained from underlying MSI-X vectors. We have + * these irq_chip functions to be able to handle level triggering +@@ -380,22 +402,48 @@ static struct irq_chip thunderx_gpio_irq + .irq_unmask = thunderx_gpio_irq_unmask, + .irq_eoi = irq_chip_eoi_parent, + .irq_set_affinity = irq_chip_set_affinity_parent, ++ .irq_request_resources = thunderx_gpio_irq_request_resources, ++ .irq_release_resources = thunderx_gpio_irq_release_resources, + .irq_set_type = thunderx_gpio_irq_set_type, + + .flags = IRQCHIP_SET_TYPE_MASKED + }; + +-static int thunderx_gpio_child_to_parent_hwirq(struct gpio_chip *gc, +- unsigned int child, +- unsigned int child_type, +- unsigned int *parent, +- unsigned int *parent_type) ++static int thunderx_gpio_irq_translate(struct irq_domain *d, ++ struct irq_fwspec *fwspec, ++ irq_hw_number_t *hwirq, ++ unsigned int *type) ++{ ++ struct thunderx_gpio *txgpio = d->host_data; ++ ++ if (WARN_ON(fwspec->param_count < 2)) ++ return -EINVAL; ++ if (fwspec->param[0] >= txgpio->chip.ngpio) ++ return -EINVAL; ++ *hwirq = fwspec->param[0]; ++ *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; ++ return 0; ++} ++ ++static int thunderx_gpio_irq_alloc(struct irq_domain *d, unsigned int virq, ++ unsigned int nr_irqs, void *arg) + { +- struct thunderx_gpio *txgpio = gpiochip_get_data(gc); ++ struct thunderx_line *txline = arg; + +- *parent = txgpio->base_msi + (2 * child); +- *parent_type = IRQ_TYPE_LEVEL_HIGH; +- return 0; ++ return irq_domain_set_hwirq_and_chip(d, virq, txline->line, ++ &thunderx_gpio_irq_chip, txline); ++} ++ ++static const struct irq_domain_ops thunderx_gpio_irqd_ops = { ++ .alloc = thunderx_gpio_irq_alloc, ++ .translate = thunderx_gpio_irq_translate ++}; ++ ++static int thunderx_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) ++{ ++ struct thunderx_gpio *txgpio = gpiochip_get_data(chip); ++ ++ return irq_find_mapping(txgpio->irqd, offset); + } + + static int thunderx_gpio_probe(struct pci_dev *pdev, +@@ -405,7 +453,6 @@ static int thunderx_gpio_probe(struct pc + struct device *dev = &pdev->dev; + struct thunderx_gpio *txgpio; + struct gpio_chip *chip; +- struct gpio_irq_chip *girq; + int ngpio, i; + int err = 0; + +@@ -450,8 +497,8 @@ static int thunderx_gpio_probe(struct pc + } + + txgpio->msix_entries = devm_kcalloc(dev, +- ngpio, sizeof(struct msix_entry), +- GFP_KERNEL); ++ ngpio, sizeof(struct msix_entry), ++ GFP_KERNEL); + if (!txgpio->msix_entries) { + err = -ENOMEM; + goto out; +@@ -492,6 +539,27 @@ static int thunderx_gpio_probe(struct pc + if (err < 0) + goto out; + ++ /* ++ * Push GPIO specific irqdomain on hierarchy created as a side ++ * effect of the pci_enable_msix() ++ */ ++ txgpio->irqd = irq_domain_create_hierarchy(irq_get_irq_data(txgpio->msix_entries[0].vector)->domain, ++ 0, 0, of_node_to_fwnode(dev->of_node), ++ &thunderx_gpio_irqd_ops, txgpio); ++ if (!txgpio->irqd) { ++ err = -ENOMEM; ++ goto out; ++ } ++ ++ /* Push on irq_data and the domain for each line. */ ++ for (i = 0; i < ngpio; i++) { ++ err = irq_domain_push_irq(txgpio->irqd, ++ txgpio->msix_entries[i].vector, ++ &txgpio->line_entries[i]); ++ if (err < 0) ++ dev_err(dev, "irq_domain_push_irq: %d\n", err); ++ } ++ + chip->label = KBUILD_MODNAME; + chip->parent = dev; + chip->owner = THIS_MODULE; +@@ -506,28 +574,11 @@ static int thunderx_gpio_probe(struct pc + chip->set = thunderx_gpio_set; + chip->set_multiple = thunderx_gpio_set_multiple; + chip->set_config = thunderx_gpio_set_config; +- girq = &chip->irq; +- girq->chip = &thunderx_gpio_irq_chip; +- girq->fwnode = of_node_to_fwnode(dev->of_node); +- girq->parent_domain = +- irq_get_irq_data(txgpio->msix_entries[0].vector)->domain; +- girq->child_to_parent_hwirq = thunderx_gpio_child_to_parent_hwirq; +- girq->handler = handle_bad_irq; +- girq->default_type = IRQ_TYPE_NONE; +- ++ chip->to_irq = thunderx_gpio_to_irq; + err = devm_gpiochip_add_data(dev, chip, txgpio); + if (err) + goto out; + +- /* Push on irq_data and the domain for each line. */ +- for (i = 0; i < ngpio; i++) { +- err = irq_domain_push_irq(chip->irq.domain, +- txgpio->msix_entries[i].vector, +- chip); +- if (err < 0) +- dev_err(dev, "irq_domain_push_irq: %d\n", err); +- } +- + dev_info(dev, "ThunderX GPIO: %d lines with base %d.\n", + ngpio, chip->base); + return 0; +@@ -542,10 +593,10 @@ static void thunderx_gpio_remove(struct + struct thunderx_gpio *txgpio = pci_get_drvdata(pdev); + + for (i = 0; i < txgpio->chip.ngpio; i++) +- irq_domain_pop_irq(txgpio->chip.irq.domain, ++ irq_domain_pop_irq(txgpio->irqd, + txgpio->msix_entries[i].vector); + +- irq_domain_remove(txgpio->chip.irq.domain); ++ irq_domain_remove(txgpio->irqd); + + pci_set_drvdata(pdev, NULL); + } diff --git a/queue-5.4/soc-amlogic-meson-ee-pwrc-propagate-errors-from-pm_genpd_init.patch b/queue-5.4/soc-amlogic-meson-ee-pwrc-propagate-errors-from-pm_genpd_init.patch new file mode 100644 index 00000000000..0d0f612f4b2 --- /dev/null +++ b/queue-5.4/soc-amlogic-meson-ee-pwrc-propagate-errors-from-pm_genpd_init.patch @@ -0,0 +1,61 @@ +From c67aafd60d7e323fe74bf45fab60148f84cf9b95 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sat, 30 Nov 2019 15:58:21 +0100 +Subject: soc: amlogic: meson-ee-pwrc: propagate errors from pm_genpd_init() + +From: Martin Blumenstingl + +commit c67aafd60d7e323fe74bf45fab60148f84cf9b95 upstream. + +pm_genpd_init() can return an error. Propagate the error code to prevent +the driver from indicating that it successfully probed while there were +errors during pm_genpd_init(). + +Fixes: eef3c2ba0a42a6 ("soc: amlogic: Add support for Everything-Else power domains controller") +Signed-off-by: Martin Blumenstingl +Signed-off-by: Kevin Hilman +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/soc/amlogic/meson-ee-pwrc.c | 20 ++++++++++++++------ + 1 file changed, 14 insertions(+), 6 deletions(-) + +--- a/drivers/soc/amlogic/meson-ee-pwrc.c ++++ b/drivers/soc/amlogic/meson-ee-pwrc.c +@@ -323,6 +323,8 @@ static int meson_ee_pwrc_init_domain(str + struct meson_ee_pwrc *pwrc, + struct meson_ee_pwrc_domain *dom) + { ++ int ret; ++ + dom->pwrc = pwrc; + dom->num_rstc = dom->desc.reset_names_count; + dom->num_clks = dom->desc.clk_names_count; +@@ -368,15 +370,21 @@ static int meson_ee_pwrc_init_domain(str + * prepare/enable counters won't be in sync. + */ + if (dom->num_clks && dom->desc.get_power && !dom->desc.get_power(dom)) { +- int ret = clk_bulk_prepare_enable(dom->num_clks, dom->clks); ++ ret = clk_bulk_prepare_enable(dom->num_clks, dom->clks); + if (ret) + return ret; + +- pm_genpd_init(&dom->base, &pm_domain_always_on_gov, false); +- } else +- pm_genpd_init(&dom->base, NULL, +- (dom->desc.get_power ? +- dom->desc.get_power(dom) : true)); ++ ret = pm_genpd_init(&dom->base, &pm_domain_always_on_gov, ++ false); ++ if (ret) ++ return ret; ++ } else { ++ ret = pm_genpd_init(&dom->base, NULL, ++ (dom->desc.get_power ? ++ dom->desc.get_power(dom) : true)); ++ if (ret) ++ return ret; ++ } + + return 0; + } diff --git a/queue-5.4/soc-amlogic-meson-ee-pwrc-propagate-pd-provider-registration-errors.patch b/queue-5.4/soc-amlogic-meson-ee-pwrc-propagate-pd-provider-registration-errors.patch new file mode 100644 index 00000000000..f72506e086f --- /dev/null +++ b/queue-5.4/soc-amlogic-meson-ee-pwrc-propagate-pd-provider-registration-errors.patch @@ -0,0 +1,35 @@ +From 0766d65e6afaea8b80205a468207de9f18cd7ec8 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sat, 30 Nov 2019 15:58:20 +0100 +Subject: soc: amlogic: meson-ee-pwrc: propagate PD provider registration errors + +From: Martin Blumenstingl + +commit 0766d65e6afaea8b80205a468207de9f18cd7ec8 upstream. + +of_genpd_add_provider_onecell() can return an error. Propagate the error +so the driver registration fails when of_genpd_add_provider_onecell() +did not work. + +Fixes: eef3c2ba0a42a6 ("soc: amlogic: Add support for Everything-Else power domains controller") +Signed-off-by: Martin Blumenstingl +Signed-off-by: Kevin Hilman +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/soc/amlogic/meson-ee-pwrc.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +--- a/drivers/soc/amlogic/meson-ee-pwrc.c ++++ b/drivers/soc/amlogic/meson-ee-pwrc.c +@@ -441,9 +441,7 @@ static int meson_ee_pwrc_probe(struct pl + pwrc->xlate.domains[i] = &dom->base; + } + +- of_genpd_add_provider_onecell(pdev->dev.of_node, &pwrc->xlate); +- +- return 0; ++ return of_genpd_add_provider_onecell(pdev->dev.of_node, &pwrc->xlate); + } + + static void meson_ee_pwrc_shutdown(struct platform_device *pdev)