From: Greg Kroah-Hartman Date: Mon, 25 Nov 2013 22:50:11 +0000 (-0800) Subject: 3.11-stable patches X-Git-Tag: v3.11.10~33 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=c9e140292e61904d7761fa8a7018fa3466e7a9bb;p=thirdparty%2Fkernel%2Fstable-queue.git 3.11-stable patches added patches: pci-allow-pcie-capability-link-related-register-access-for-switches.patch pci-remove-pcie-capability-version-checks.patch pci-support-pcie-capability-slot-registers-only-for-ports-with-slots.patch --- diff --git a/queue-3.11/pci-allow-pcie-capability-link-related-register-access-for-switches.patch b/queue-3.11/pci-allow-pcie-capability-link-related-register-access-for-switches.patch new file mode 100644 index 00000000000..04767bfde77 --- /dev/null +++ b/queue-3.11/pci-allow-pcie-capability-link-related-register-access-for-switches.patch @@ -0,0 +1,43 @@ +From d3694d4fa3f44f6a295f8ab064937c8a1549d174 Mon Sep 17 00:00:00 2001 +From: Bjorn Helgaas +Date: Tue, 27 Aug 2013 09:54:40 -0600 +Subject: PCI: Allow PCIe Capability link-related register access for switches + +From: Bjorn Helgaas + +commit d3694d4fa3f44f6a295f8ab064937c8a1549d174 upstream. + +Every PCIe device has a link, except Root Complex Integrated Endpoints +and Root Complex Event Collectors. Previously we didn't give access +to PCIe capability link-related registers for Upstream Ports, Downstream +Ports, and Bridges, so attempts to read PCI_EXP_LNKCTL incorrectly +returned zero. See PCIe spec r3.0, sec 7.8 and 1.3.2.3. + +Reference: http://lkml.kernel.org/r/979A8436335E3744ADCD3A9F2A2B68A52AD136BE@SJEXCHMB10.corp.ad.broadcom.com +Reported-by: Yuval Mintz +Signed-off-by: Bjorn Helgaas +Reviewed-By: Jiang Liu +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pci/access.c | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +--- a/drivers/pci/access.c ++++ b/drivers/pci/access.c +@@ -485,9 +485,13 @@ static inline bool pcie_cap_has_lnkctl(c + int type = pci_pcie_type(dev); + + return pcie_cap_version(dev) > 1 || +- type == PCI_EXP_TYPE_ROOT_PORT || + type == PCI_EXP_TYPE_ENDPOINT || +- type == PCI_EXP_TYPE_LEG_END; ++ type == PCI_EXP_TYPE_LEG_END || ++ type == PCI_EXP_TYPE_ROOT_PORT || ++ type == PCI_EXP_TYPE_UPSTREAM || ++ type == PCI_EXP_TYPE_DOWNSTREAM || ++ type == PCI_EXP_TYPE_PCI_BRIDGE || ++ type == PCI_EXP_TYPE_PCIE_BRIDGE; + } + + static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev) diff --git a/queue-3.11/pci-remove-pcie-capability-version-checks.patch b/queue-3.11/pci-remove-pcie-capability-version-checks.patch new file mode 100644 index 00000000000..9400770056a --- /dev/null +++ b/queue-3.11/pci-remove-pcie-capability-version-checks.patch @@ -0,0 +1,59 @@ +From c8b303d0206b28c4ff3aecada47108d1655ae00f Mon Sep 17 00:00:00 2001 +From: Bjorn Helgaas +Date: Wed, 28 Aug 2013 11:33:53 -0600 +Subject: PCI: Remove PCIe Capability version checks + +From: Bjorn Helgaas + +commit c8b303d0206b28c4ff3aecada47108d1655ae00f upstream. + +Previously we relied on the PCIe r3.0, sec 7.8, spec language that says +"For Functions that do not implement the [Link, Slot, Root] registers, +these spaces must be hardwired to 0b," which means that for v2 PCIe +capabilities, we don't need to check the device type at all. + +But it's simpler if we don't need to check the capability version at all, +and I think the spec is explicit enough about which registers are required +for which types that we can remove the version checks. + +Signed-off-by: Bjorn Helgaas +Reviewed-By: Jiang Liu +Acked-by: Myron Stowe +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pci/access.c | 9 +++------ + 1 file changed, 3 insertions(+), 6 deletions(-) + +--- a/drivers/pci/access.c ++++ b/drivers/pci/access.c +@@ -484,8 +484,7 @@ static inline bool pcie_cap_has_lnkctl(c + { + int type = pci_pcie_type(dev); + +- return pcie_cap_version(dev) > 1 || +- type == PCI_EXP_TYPE_ENDPOINT || ++ return type == PCI_EXP_TYPE_ENDPOINT || + type == PCI_EXP_TYPE_LEG_END || + type == PCI_EXP_TYPE_ROOT_PORT || + type == PCI_EXP_TYPE_UPSTREAM || +@@ -498,8 +497,7 @@ static inline bool pcie_cap_has_sltctl(c + { + int type = pci_pcie_type(dev); + +- return pcie_cap_version(dev) > 1 || +- type == PCI_EXP_TYPE_ROOT_PORT || ++ return type == PCI_EXP_TYPE_ROOT_PORT || + (type == PCI_EXP_TYPE_DOWNSTREAM && + pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT); + } +@@ -508,8 +506,7 @@ static inline bool pcie_cap_has_rtctl(co + { + int type = pci_pcie_type(dev); + +- return pcie_cap_version(dev) > 1 || +- type == PCI_EXP_TYPE_ROOT_PORT || ++ return type == PCI_EXP_TYPE_ROOT_PORT || + type == PCI_EXP_TYPE_RC_EC; + } + diff --git a/queue-3.11/pci-support-pcie-capability-slot-registers-only-for-ports-with-slots.patch b/queue-3.11/pci-support-pcie-capability-slot-registers-only-for-ports-with-slots.patch new file mode 100644 index 00000000000..a7c52a4d10e --- /dev/null +++ b/queue-3.11/pci-support-pcie-capability-slot-registers-only-for-ports-with-slots.patch @@ -0,0 +1,44 @@ +From 6d3a1741f1e648cfbd5a0cc94477a0d5004c6f5e Mon Sep 17 00:00:00 2001 +From: Bjorn Helgaas +Date: Wed, 28 Aug 2013 12:01:03 -0600 +Subject: PCI: Support PCIe Capability Slot registers only for ports with slots + +From: Bjorn Helgaas + +commit 6d3a1741f1e648cfbd5a0cc94477a0d5004c6f5e upstream. + +Previously we allowed callers to access Slot Capabilities, Status, and +Control for Root Ports even if the Root Port did not implement a slot. +This seems dubious because the spec only requires these registers if a +slot is implemented. + +It's true that even Root Ports without slots must have *space* for these +slot registers, because the Root Capabilities, Status, and Control +registers are after the slot registers in the capability. However, +for a v1 PCIe Capability, the *semantics* of the slot registers are +undefined unless a slot is implemented. + +Signed-off-by: Bjorn Helgaas +Reviewed-By: Jiang Liu +Acked-by: Myron Stowe +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pci/access.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/pci/access.c ++++ b/drivers/pci/access.c +@@ -497,9 +497,9 @@ static inline bool pcie_cap_has_sltctl(c + { + int type = pci_pcie_type(dev); + +- return type == PCI_EXP_TYPE_ROOT_PORT || +- (type == PCI_EXP_TYPE_DOWNSTREAM && +- pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT); ++ return (type == PCI_EXP_TYPE_ROOT_PORT || ++ type == PCI_EXP_TYPE_DOWNSTREAM) && ++ pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT; + } + + static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev) diff --git a/queue-3.11/series b/queue-3.11/series index 093f222695f..4b781e1e3af 100644 --- a/queue-3.11/series +++ b/queue-3.11/series @@ -16,3 +16,6 @@ drm-nvc0-gr-fix-a-number-of-missing-explicit-array-terminators.patch thinkpad_acpi-fix-build-error-when-config_snd_max_cards-32.patch sunrpc-don-t-map-ekeyexpired-to-eacces-in-call_refreshresult.patch sched-idle-fix-the-idle-polling-state-logic.patch +pci-allow-pcie-capability-link-related-register-access-for-switches.patch +pci-remove-pcie-capability-version-checks.patch +pci-support-pcie-capability-slot-registers-only-for-ports-with-slots.patch