From: Greg Kroah-Hartman Date: Wed, 27 Mar 2024 10:39:24 +0000 (+0100) Subject: 6.6-stable patches X-Git-Tag: v6.7.12~233 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=c9ee8a9516ed52fa407b0b2a99bd9faf21038492;p=thirdparty%2Fkernel%2Fstable-queue.git 6.6-stable patches added patches: kvm-x86-advertise-cpuid.-eax-7-ecx-2-edx-to-userspace.patch --- diff --git a/queue-6.6/kvm-x86-advertise-cpuid.-eax-7-ecx-2-edx-to-userspace.patch b/queue-6.6/kvm-x86-advertise-cpuid.-eax-7-ecx-2-edx-to-userspace.patch new file mode 100644 index 00000000000..6644fde4757 --- /dev/null +++ b/queue-6.6/kvm-x86-advertise-cpuid.-eax-7-ecx-2-edx-to-userspace.patch @@ -0,0 +1,120 @@ +From eefe5e6682099445f77f2d97d4c525f9ac9d9b07 Mon Sep 17 00:00:00 2001 +From: Jim Mattson +Date: Mon, 23 Oct 2023 17:16:35 -0700 +Subject: KVM: x86: Advertise CPUID.(EAX=7,ECX=2):EDX[5:0] to userspace + +From: Jim Mattson + +commit eefe5e6682099445f77f2d97d4c525f9ac9d9b07 upstream. + +The low five bits {INTEL_PSFD, IPRED_CTRL, RRSBA_CTRL, DDPD_U, BHI_CTRL} +advertise the availability of specific bits in IA32_SPEC_CTRL. Since KVM +dynamically determines the legal IA32_SPEC_CTRL bits for the underlying +hardware, the hard work has already been done. Just let userspace know +that a guest can use these IA32_SPEC_CTRL bits. + +The sixth bit (MCDT_NO) states that the processor does not exhibit MXCSR +Configuration Dependent Timing (MCDT) behavior. This is an inherent +property of the physical processor that is inherited by the virtual +CPU. Pass that information on to userspace. + +Signed-off-by: Jim Mattson +Reviewed-by: Chao Gao +Link: https://lore.kernel.org/r/20231024001636.890236-1-jmattson@google.com +Signed-off-by: Sean Christopherson +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/kvm/cpuid.c | 21 ++++++++++++++++++--- + arch/x86/kvm/reverse_cpuid.h | 12 ++++++++++++ + 2 files changed, 30 insertions(+), 3 deletions(-) + +--- a/arch/x86/kvm/cpuid.c ++++ b/arch/x86/kvm/cpuid.c +@@ -677,6 +677,11 @@ void kvm_set_cpu_caps(void) + F(AMX_COMPLEX) + ); + ++ kvm_cpu_cap_init_kvm_defined(CPUID_7_2_EDX, ++ F(INTEL_PSFD) | F(IPRED_CTRL) | F(RRSBA_CTRL) | F(DDPD_U) | ++ F(BHI_CTRL) | F(MCDT_NO) ++ ); ++ + kvm_cpu_cap_mask(CPUID_D_1_EAX, + F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd + ); +@@ -956,13 +961,13 @@ static inline int __do_cpuid_func(struct + break; + /* function 7 has additional index. */ + case 7: +- entry->eax = min(entry->eax, 1u); ++ max_idx = entry->eax = min(entry->eax, 2u); + cpuid_entry_override(entry, CPUID_7_0_EBX); + cpuid_entry_override(entry, CPUID_7_ECX); + cpuid_entry_override(entry, CPUID_7_EDX); + +- /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */ +- if (entry->eax == 1) { ++ /* KVM only supports up to 0x7.2, capped above via min(). */ ++ if (max_idx >= 1) { + entry = do_host_cpuid(array, function, 1); + if (!entry) + goto out; +@@ -972,6 +977,16 @@ static inline int __do_cpuid_func(struct + entry->ebx = 0; + entry->ecx = 0; + } ++ if (max_idx >= 2) { ++ entry = do_host_cpuid(array, function, 2); ++ if (!entry) ++ goto out; ++ ++ cpuid_entry_override(entry, CPUID_7_2_EDX); ++ entry->ecx = 0; ++ entry->ebx = 0; ++ entry->eax = 0; ++ } + break; + case 0xa: { /* Architectural Performance Monitoring */ + union cpuid10_eax eax; +--- a/arch/x86/kvm/reverse_cpuid.h ++++ b/arch/x86/kvm/reverse_cpuid.h +@@ -16,6 +16,7 @@ enum kvm_only_cpuid_leafs { + CPUID_7_1_EDX, + CPUID_8000_0007_EDX, + CPUID_8000_0022_EAX, ++ CPUID_7_2_EDX, + NR_KVM_CPU_CAPS, + + NKVMCAPINTS = NR_KVM_CPU_CAPS - NCAPINTS, +@@ -46,6 +47,14 @@ enum kvm_only_cpuid_leafs { + #define X86_FEATURE_AMX_COMPLEX KVM_X86_FEATURE(CPUID_7_1_EDX, 8) + #define X86_FEATURE_PREFETCHITI KVM_X86_FEATURE(CPUID_7_1_EDX, 14) + ++/* Intel-defined sub-features, CPUID level 0x00000007:2 (EDX) */ ++#define X86_FEATURE_INTEL_PSFD KVM_X86_FEATURE(CPUID_7_2_EDX, 0) ++#define X86_FEATURE_IPRED_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 1) ++#define KVM_X86_FEATURE_RRSBA_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 2) ++#define X86_FEATURE_DDPD_U KVM_X86_FEATURE(CPUID_7_2_EDX, 3) ++#define X86_FEATURE_BHI_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 4) ++#define X86_FEATURE_MCDT_NO KVM_X86_FEATURE(CPUID_7_2_EDX, 5) ++ + /* CPUID level 0x80000007 (EDX). */ + #define KVM_X86_FEATURE_CONSTANT_TSC KVM_X86_FEATURE(CPUID_8000_0007_EDX, 8) + +@@ -80,6 +89,7 @@ static const struct cpuid_reg reverse_cp + [CPUID_8000_0007_EDX] = {0x80000007, 0, CPUID_EDX}, + [CPUID_8000_0021_EAX] = {0x80000021, 0, CPUID_EAX}, + [CPUID_8000_0022_EAX] = {0x80000022, 0, CPUID_EAX}, ++ [CPUID_7_2_EDX] = { 7, 2, CPUID_EDX}, + }; + + /* +@@ -116,6 +126,8 @@ static __always_inline u32 __feature_tra + return KVM_X86_FEATURE_CONSTANT_TSC; + else if (x86_feature == X86_FEATURE_PERFMON_V2) + return KVM_X86_FEATURE_PERFMON_V2; ++ else if (x86_feature == X86_FEATURE_RRSBA_CTRL) ++ return KVM_X86_FEATURE_RRSBA_CTRL; + + return x86_feature; + } diff --git a/queue-6.6/series b/queue-6.6/series index e69de29bb2d..b2e4c15b04f 100644 --- a/queue-6.6/series +++ b/queue-6.6/series @@ -0,0 +1 @@ +kvm-x86-advertise-cpuid.-eax-7-ecx-2-edx-to-userspace.patch