From: Greg Kroah-Hartman Date: Mon, 5 Jun 2023 15:38:46 +0000 (+0200) Subject: 6.3-stable patches X-Git-Tag: v4.14.317~71 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ca432dd19ea6a357b53320b50c452407f4c507f9;p=thirdparty%2Fkernel%2Fstable-queue.git 6.3-stable patches added patches: ata-libata-scsi-use-correct-device-no-in-ata_find_dev.patch drm-amd-pm-resolve-reboot-exception-for-si-oland.patch drm-amd-pm-reverse-mclk-and-fclk-clocks-levels-for-renoir.patch drm-amd-pm-reverse-mclk-and-fclk-clocks-levels-for-smu-v13.0.4.patch drm-amd-pm-reverse-mclk-and-fclk-clocks-levels-for-vangogh.patch drm-amd-pm-reverse-mclk-and-fclk-clocks-levels-for-yellow-carp.patch drm-amd-pm-reverse-mclk-clocks-levels-for-smu-v13.0.5.patch drm-amdgpu-enable-tmz-by-default-for-gc-11.0.1.patch scsi-stex-fix-gcc-13-warnings.patch --- diff --git a/queue-6.3/ata-libata-scsi-use-correct-device-no-in-ata_find_dev.patch b/queue-6.3/ata-libata-scsi-use-correct-device-no-in-ata_find_dev.patch new file mode 100644 index 00000000000..22deb89a403 --- /dev/null +++ b/queue-6.3/ata-libata-scsi-use-correct-device-no-in-ata_find_dev.patch @@ -0,0 +1,96 @@ +From 7f875850f20a42f488840c9df7af91ef7db2d576 Mon Sep 17 00:00:00 2001 +From: Damien Le Moal +Date: Mon, 22 May 2023 20:09:57 +0900 +Subject: ata: libata-scsi: Use correct device no in ata_find_dev() + +From: Damien Le Moal + +commit 7f875850f20a42f488840c9df7af91ef7db2d576 upstream. + +For devices not attached to a port multiplier and managed directly by +libata, the device number passed to ata_find_dev() must always be lower +than the maximum number of devices returned by ata_link_max_devices(). +That is 1 for SATA devices or 2 for an IDE link with master+slave +devices. This device number is the SCSI device ID which matches these +constraints as the IDs are generated per port and so never exceed the +maximum number of devices for the link being used. + +However, for libsas managed devices, SCSI device IDs are assigned per +struct scsi_host, leading to device IDs for SATA devices that can be +well in excess of libata per-link maximum number of devices. This +results in ata_find_dev() to always return NULL for libsas managed +devices except for the first device of the target scsi_host with ID +(device number) equal to 0. This issue is visible by executing the +hdparm utility, which fails. E.g.: + +hdparm -i /dev/sdX +/dev/sdX: + HDIO_GET_IDENTITY failed: No message of desired type + +Fix this by rewriting ata_find_dev() to ignore the device number for +non-PMP attached devices with a link with at most 1 device, that is SATA +devices. For these, the device number 0 is always used to +return the correct pointer to the struct ata_device of the port link. +This change excludes IDE master/slave setups (maximum number of devices +per link is 2) and port-multiplier attached devices. Also, to be +consistant with the fact that SCSI device IDs and channel numbers used +as device numbers are both unsigned int, change the devno argument of +ata_find_dev() to unsigned int. + +Reported-by: Xingui Yang +Fixes: 41bda9c98035 ("libata-link: update hotplug to handle PMP links") +Cc: stable@vger.kernel.org +Signed-off-by: Damien Le Moal +Reviewed-by: Jason Yan +Signed-off-by: Greg Kroah-Hartman +--- + drivers/ata/libata-scsi.c | 34 ++++++++++++++++++++++++++-------- + 1 file changed, 26 insertions(+), 8 deletions(-) + +--- a/drivers/ata/libata-scsi.c ++++ b/drivers/ata/libata-scsi.c +@@ -2694,18 +2694,36 @@ static unsigned int atapi_xlat(struct at + return 0; + } + +-static struct ata_device *ata_find_dev(struct ata_port *ap, int devno) ++static struct ata_device *ata_find_dev(struct ata_port *ap, unsigned int devno) + { +- if (!sata_pmp_attached(ap)) { +- if (likely(devno >= 0 && +- devno < ata_link_max_devices(&ap->link))) ++ /* ++ * For the non-PMP case, ata_link_max_devices() returns 1 (SATA case), ++ * or 2 (IDE master + slave case). However, the former case includes ++ * libsas hosted devices which are numbered per scsi host, leading ++ * to devno potentially being larger than 0 but with each struct ++ * ata_device having its own struct ata_port and struct ata_link. ++ * To accommodate these, ignore devno and always use device number 0. ++ */ ++ if (likely(!sata_pmp_attached(ap))) { ++ int link_max_devices = ata_link_max_devices(&ap->link); ++ ++ if (link_max_devices == 1) ++ return &ap->link.device[0]; ++ ++ if (devno < link_max_devices) + return &ap->link.device[devno]; +- } else { +- if (likely(devno >= 0 && +- devno < ap->nr_pmp_links)) +- return &ap->pmp_link[devno].device[0]; ++ ++ return NULL; + } + ++ /* ++ * For PMP-attached devices, the device number corresponds to C ++ * (channel) of SCSI [H:C:I:L], indicating the port pmp link ++ * for the device. ++ */ ++ if (devno < ap->nr_pmp_links) ++ return &ap->pmp_link[devno].device[0]; ++ + return NULL; + } + diff --git a/queue-6.3/drm-amd-pm-resolve-reboot-exception-for-si-oland.patch b/queue-6.3/drm-amd-pm-resolve-reboot-exception-for-si-oland.patch new file mode 100644 index 00000000000..7a64ce45b8d --- /dev/null +++ b/queue-6.3/drm-amd-pm-resolve-reboot-exception-for-si-oland.patch @@ -0,0 +1,74 @@ +From e490d60a2f76bff636c68ce4fe34c1b6c34bbd86 Mon Sep 17 00:00:00 2001 +From: Guchun Chen +Date: Wed, 24 May 2023 15:03:02 +0800 +Subject: drm/amd/pm: resolve reboot exception for si oland + +From: Guchun Chen + +commit e490d60a2f76bff636c68ce4fe34c1b6c34bbd86 upstream. + +During reboot test on arm64 platform, it may failure on boot. + +The error message are as follows: +[ 1.706570][ 3] [ T273] [drm:si_thermal_enable_alert [amdgpu]] *ERROR* Could not enable thermal interrupts. +[ 1.716547][ 3] [ T273] [drm:amdgpu_device_ip_late_init [amdgpu]] *ERROR* late_init of IP block failed -22 +[ 1.727064][ 3] [ T273] amdgpu 0000:02:00.0: amdgpu_device_ip_late_init failed +[ 1.734367][ 3] [ T273] amdgpu 0000:02:00.0: Fatal error during GPU init + +v2: squash in built warning fix (Alex) + +Signed-off-by: Zhenneng Li +Reviewed-by: Guchun Chen +Signed-off-by: Guchun Chen +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 29 ----------------------------- + 1 file changed, 29 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c ++++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +@@ -6925,23 +6925,6 @@ static int si_dpm_enable(struct amdgpu_d + return 0; + } + +-static int si_set_temperature_range(struct amdgpu_device *adev) +-{ +- int ret; +- +- ret = si_thermal_enable_alert(adev, false); +- if (ret) +- return ret; +- ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); +- if (ret) +- return ret; +- ret = si_thermal_enable_alert(adev, true); +- if (ret) +- return ret; +- +- return ret; +-} +- + static void si_dpm_disable(struct amdgpu_device *adev) + { + struct rv7xx_power_info *pi = rv770_get_pi(adev); +@@ -7626,18 +7609,6 @@ static int si_dpm_process_interrupt(stru + + static int si_dpm_late_init(void *handle) + { +- int ret; +- struct amdgpu_device *adev = (struct amdgpu_device *)handle; +- +- if (!adev->pm.dpm_enabled) +- return 0; +- +- ret = si_set_temperature_range(adev); +- if (ret) +- return ret; +-#if 0 //TODO ? +- si_dpm_powergate_uvd(adev, true); +-#endif + return 0; + } + diff --git a/queue-6.3/drm-amd-pm-reverse-mclk-and-fclk-clocks-levels-for-renoir.patch b/queue-6.3/drm-amd-pm-reverse-mclk-and-fclk-clocks-levels-for-renoir.patch new file mode 100644 index 00000000000..f31acc9037a --- /dev/null +++ b/queue-6.3/drm-amd-pm-reverse-mclk-and-fclk-clocks-levels-for-renoir.patch @@ -0,0 +1,54 @@ +From 55e02c14f9b5fd973ba32a16a715baa42617f9c6 Mon Sep 17 00:00:00 2001 +From: Tim Huang +Date: Mon, 22 May 2023 23:17:28 +0800 +Subject: drm/amd/pm: reverse mclk and fclk clocks levels for renoir + +From: Tim Huang + +commit 55e02c14f9b5fd973ba32a16a715baa42617f9c6 upstream. + +This patch reverses the DPM clocks levels output of pp_dpm_mclk +and pp_dpm_fclk for renoir. + +On dGPUs and older APUs we expose the levels from lowest clocks +to highest clocks. But for some APUs, the clocks levels are +given the reversed orders by PMFW. Like the memory DPM clocks +that are exposed by pp_dpm_mclk. + +It's not intuitive that they are reversed on these APUs. All tools +and software that talks to the driver then has to know different ways +to interpret the data depending on the asic. + +So we need to reverse them to expose the clocks levels from the +driver consistently. + +Signed-off-by: Tim Huang +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c +@@ -494,7 +494,7 @@ static int renoir_set_fine_grain_gfx_fre + static int renoir_print_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, char *buf) + { +- int i, size = 0, ret = 0; ++ int i, idx, size = 0, ret = 0; + uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; + SmuMetrics_t metrics; + struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); +@@ -594,7 +594,8 @@ static int renoir_print_clk_levels(struc + case SMU_VCLK: + case SMU_DCLK: + for (i = 0; i < count; i++) { +- ret = renoir_get_dpm_clk_limited(smu, clk_type, i, &value); ++ idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i; ++ ret = renoir_get_dpm_clk_limited(smu, clk_type, idx, &value); + if (ret) + return ret; + if (!value) diff --git a/queue-6.3/drm-amd-pm-reverse-mclk-and-fclk-clocks-levels-for-smu-v13.0.4.patch b/queue-6.3/drm-amd-pm-reverse-mclk-and-fclk-clocks-levels-for-smu-v13.0.4.patch new file mode 100644 index 00000000000..e736ec33784 --- /dev/null +++ b/queue-6.3/drm-amd-pm-reverse-mclk-and-fclk-clocks-levels-for-smu-v13.0.4.patch @@ -0,0 +1,54 @@ +From 6a07826f2057b5fa1c479ba56460195882464270 Mon Sep 17 00:00:00 2001 +From: Tim Huang +Date: Sun, 21 May 2023 09:24:00 +0800 +Subject: drm/amd/pm: reverse mclk and fclk clocks levels for SMU v13.0.4 + +From: Tim Huang + +commit 6a07826f2057b5fa1c479ba56460195882464270 upstream. + +This patch reverses the DPM clocks levels output of pp_dpm_mclk +and pp_dpm_fclk. + +On dGPUs and older APUs we expose the levels from lowest clocks +to highest clocks. But for some APUs, the clocks levels that from +the DFPstateTable are given the reversed orders by PMFW. Like the +memory DPM clocks that are exposed by pp_dpm_mclk. + +It's not intuitive that they are reversed on these APUs. All tools +and software that talks to the driver then has to know different ways +to interpret the data depending on the asic. + +So we need to reverse them to expose the clocks levels from the +driver consistently. + +Signed-off-by: Tim Huang +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c +@@ -478,7 +478,7 @@ static int smu_v13_0_4_get_dpm_level_cou + static int smu_v13_0_4_print_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, char *buf) + { +- int i, size = 0, ret = 0; ++ int i, idx, size = 0, ret = 0; + uint32_t cur_value = 0, value = 0, count = 0; + uint32_t min, max; + +@@ -512,7 +512,8 @@ static int smu_v13_0_4_print_clk_levels( + break; + + for (i = 0; i < count; i++) { +- ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, i, &value); ++ idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i; ++ ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, idx, &value); + if (ret) + break; + diff --git a/queue-6.3/drm-amd-pm-reverse-mclk-and-fclk-clocks-levels-for-vangogh.patch b/queue-6.3/drm-amd-pm-reverse-mclk-and-fclk-clocks-levels-for-vangogh.patch new file mode 100644 index 00000000000..9b3f8b0a0d1 --- /dev/null +++ b/queue-6.3/drm-amd-pm-reverse-mclk-and-fclk-clocks-levels-for-vangogh.patch @@ -0,0 +1,73 @@ +From bfc03568d9d81332382c73a1985a90c4506bd36c Mon Sep 17 00:00:00 2001 +From: Tim Huang +Date: Sun, 21 May 2023 11:10:19 +0800 +Subject: drm/amd/pm: reverse mclk and fclk clocks levels for vangogh + +From: Tim Huang + +commit bfc03568d9d81332382c73a1985a90c4506bd36c upstream. + +This patch reverses the DPM clocks levels output of pp_dpm_mclk +and pp_dpm_fclk. + +On dGPUs and older APUs we expose the levels from lowest clocks +to highest clocks. But for some APUs, the clocks levels that from +the DFPstateTable are given the reversed orders by PMFW. Like the +memory DPM clocks that are exposed by pp_dpm_mclk. + +It's not intuitive that they are reversed on these APUs. All tools +and software that talks to the driver then has to know different ways +to interpret the data depending on the asic. + +So we need to reverse them to expose the clocks levels from the +driver consistently. + +Signed-off-by: Tim Huang +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 10 ++++++---- + 1 file changed, 6 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +@@ -580,7 +580,7 @@ static int vangogh_print_legacy_clk_leve + DpmClocks_t *clk_table = smu->smu_table.clocks_table; + SmuMetrics_legacy_t metrics; + struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); +- int i, size = 0, ret = 0; ++ int i, idx, size = 0, ret = 0; + uint32_t cur_value = 0, value = 0, count = 0; + bool cur_value_match_level = false; + +@@ -654,7 +654,8 @@ static int vangogh_print_legacy_clk_leve + case SMU_MCLK: + case SMU_FCLK: + for (i = 0; i < count; i++) { +- ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value); ++ idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i; ++ ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value); + if (ret) + return ret; + if (!value) +@@ -681,7 +682,7 @@ static int vangogh_print_clk_levels(stru + DpmClocks_t *clk_table = smu->smu_table.clocks_table; + SmuMetrics_t metrics; + struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); +- int i, size = 0, ret = 0; ++ int i, idx, size = 0, ret = 0; + uint32_t cur_value = 0, value = 0, count = 0; + bool cur_value_match_level = false; + uint32_t min, max; +@@ -763,7 +764,8 @@ static int vangogh_print_clk_levels(stru + case SMU_MCLK: + case SMU_FCLK: + for (i = 0; i < count; i++) { +- ret = vangogh_get_dpm_clk_limited(smu, clk_type, i, &value); ++ idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i; ++ ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value); + if (ret) + return ret; + if (!value) diff --git a/queue-6.3/drm-amd-pm-reverse-mclk-and-fclk-clocks-levels-for-yellow-carp.patch b/queue-6.3/drm-amd-pm-reverse-mclk-and-fclk-clocks-levels-for-yellow-carp.patch new file mode 100644 index 00000000000..7d299414808 --- /dev/null +++ b/queue-6.3/drm-amd-pm-reverse-mclk-and-fclk-clocks-levels-for-yellow-carp.patch @@ -0,0 +1,54 @@ +From f1373a97a41f429e0095d4be388092ffa3c1a157 Mon Sep 17 00:00:00 2001 +From: Tim Huang +Date: Sun, 21 May 2023 10:35:59 +0800 +Subject: drm/amd/pm: reverse mclk and fclk clocks levels for yellow carp + +From: Tim Huang + +commit f1373a97a41f429e0095d4be388092ffa3c1a157 upstream. + +This patch reverses the DPM clocks levels output of pp_dpm_mclk +and pp_dpm_fclk. + +On dGPUs and older APUs we expose the levels from lowest clocks +to highest clocks. But for some APUs, the clocks levels that from +the DFPstateTable are given the reversed orders by PMFW. Like the +memory DPM clocks that are exposed by pp_dpm_mclk. + +It's not intuitive that they are reversed on these APUs. All tools +and software that talks to the driver then has to know different ways +to interpret the data depending on the asic. + +So we need to reverse them to expose the clocks levels from the +driver consistently. + +Signed-off-by: Tim Huang +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c +@@ -1000,7 +1000,7 @@ out: + static int yellow_carp_print_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, char *buf) + { +- int i, size = 0, ret = 0; ++ int i, idx, size = 0, ret = 0; + uint32_t cur_value = 0, value = 0, count = 0; + uint32_t min, max; + +@@ -1033,7 +1033,8 @@ static int yellow_carp_print_clk_levels( + goto print_clk_out; + + for (i = 0; i < count; i++) { +- ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, i, &value); ++ idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i; ++ ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, idx, &value); + if (ret) + goto print_clk_out; + diff --git a/queue-6.3/drm-amd-pm-reverse-mclk-clocks-levels-for-smu-v13.0.5.patch b/queue-6.3/drm-amd-pm-reverse-mclk-clocks-levels-for-smu-v13.0.5.patch new file mode 100644 index 00000000000..359f269b3ce --- /dev/null +++ b/queue-6.3/drm-amd-pm-reverse-mclk-clocks-levels-for-smu-v13.0.5.patch @@ -0,0 +1,53 @@ +From c1d35412b3e826ae8119e3fb5f51dd0fa5b6b567 Mon Sep 17 00:00:00 2001 +From: Tim Huang +Date: Sun, 21 May 2023 10:28:05 +0800 +Subject: drm/amd/pm: reverse mclk clocks levels for SMU v13.0.5 + +From: Tim Huang + +commit c1d35412b3e826ae8119e3fb5f51dd0fa5b6b567 upstream. + +This patch reverses the DPM clocks levels output of pp_dpm_mclk. + +On dGPUs and older APUs we expose the levels from lowest clocks +to highest clocks. But for some APUs, the clocks levels that from +the DFPstateTable are given the reversed orders by PMFW. Like the +memory DPM clocks that are exposed by pp_dpm_mclk. + +It's not intuitive that they are reversed on these APUs. All tools +and software that talks to the driver then has to know different ways +to interpret the data depending on the asic. + +So we need to reverse them to expose the clocks levels from the +driver consistently. + +Signed-off-by: Tim Huang +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c +@@ -866,7 +866,7 @@ out: + static int smu_v13_0_5_print_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, char *buf) + { +- int i, size = 0, ret = 0; ++ int i, idx, size = 0, ret = 0; + uint32_t cur_value = 0, value = 0, count = 0; + uint32_t min = 0, max = 0; + +@@ -898,7 +898,8 @@ static int smu_v13_0_5_print_clk_levels( + goto print_clk_out; + + for (i = 0; i < count; i++) { +- ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, i, &value); ++ idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i; ++ ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, idx, &value); + if (ret) + goto print_clk_out; + diff --git a/queue-6.3/drm-amdgpu-enable-tmz-by-default-for-gc-11.0.1.patch b/queue-6.3/drm-amdgpu-enable-tmz-by-default-for-gc-11.0.1.patch new file mode 100644 index 00000000000..b7646a2d073 --- /dev/null +++ b/queue-6.3/drm-amdgpu-enable-tmz-by-default-for-gc-11.0.1.patch @@ -0,0 +1,40 @@ +From 663b930e24842f3d3bb79418bb5cd8d01b40c559 Mon Sep 17 00:00:00 2001 +From: Ikshwaku Chauhan +Date: Thu, 25 May 2023 10:57:26 +0530 +Subject: drm/amdgpu: enable tmz by default for GC 11.0.1 + +From: Ikshwaku Chauhan + +commit 663b930e24842f3d3bb79418bb5cd8d01b40c559 upstream. + +Add IP GC 11.0.1 in the list of target to have +tmz enabled by default. + +Signed-off-by: Ikshwaku Chauhan +Reviewed-by: Alex Deucher +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org # 6.1.x +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +@@ -534,6 +534,8 @@ void amdgpu_gmc_tmz_set(struct amdgpu_de + case IP_VERSION(9, 3, 0): + /* GC 10.3.7 */ + case IP_VERSION(10, 3, 7): ++ /* GC 11.0.1 */ ++ case IP_VERSION(11, 0, 1): + if (amdgpu_tmz == 0) { + adev->gmc.tmz_enabled = false; + dev_info(adev->dev, +@@ -557,7 +559,6 @@ void amdgpu_gmc_tmz_set(struct amdgpu_de + case IP_VERSION(10, 3, 1): + /* YELLOW_CARP*/ + case IP_VERSION(10, 3, 3): +- case IP_VERSION(11, 0, 1): + case IP_VERSION(11, 0, 4): + /* Don't enable it by default yet. + */ diff --git a/queue-6.3/scsi-stex-fix-gcc-13-warnings.patch b/queue-6.3/scsi-stex-fix-gcc-13-warnings.patch new file mode 100644 index 00000000000..c3f47c3d75d --- /dev/null +++ b/queue-6.3/scsi-stex-fix-gcc-13-warnings.patch @@ -0,0 +1,66 @@ +From 6d074ce231772c66e648a61f6bd2245e7129d1f5 Mon Sep 17 00:00:00 2001 +From: Bart Van Assche +Date: Mon, 29 May 2023 12:50:34 -0700 +Subject: scsi: stex: Fix gcc 13 warnings +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Bart Van Assche + +commit 6d074ce231772c66e648a61f6bd2245e7129d1f5 upstream. + +gcc 13 may assign another type to enumeration constants than gcc 12. Split +the large enum at the top of source file stex.c such that the type of the +constants used in time expressions is changed back to the same type chosen +by gcc 12. This patch suppresses compiler warnings like this one: + +In file included from ./include/linux/bitops.h:7, + from ./include/linux/kernel.h:22, + from drivers/scsi/stex.c:13: +drivers/scsi/stex.c: In function ‘stex_common_handshake’: +./include/linux/typecheck.h:12:25: error: comparison of distinct pointer types lacks a cast [-Werror] + 12 | (void)(&__dummy == &__dummy2); \ + | ^~ +./include/linux/jiffies.h:106:10: note: in expansion of macro ‘typecheck’ + 106 | typecheck(unsigned long, b) && \ + | ^~~~~~~~~ +drivers/scsi/stex.c:1035:29: note: in expansion of macro ‘time_after’ + 1035 | if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { + | ^~~~~~~~~~ + +See also https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107405. + +Cc: stable@vger.kernel.org +Acked-by: Randy Dunlap +Tested-by: Randy Dunlap # build-tested +Signed-off-by: Bart Van Assche +Link: https://lore.kernel.org/r/20230529195034.3077-1-bvanassche@acm.org +Signed-off-by: Martin K. Petersen +Signed-off-by: Greg Kroah-Hartman +--- + drivers/scsi/stex.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/scsi/stex.c ++++ b/drivers/scsi/stex.c +@@ -109,7 +109,9 @@ enum { + TASK_ATTRIBUTE_HEADOFQUEUE = 0x1, + TASK_ATTRIBUTE_ORDERED = 0x2, + TASK_ATTRIBUTE_ACA = 0x4, ++}; + ++enum { + SS_STS_NORMAL = 0x80000000, + SS_STS_DONE = 0x40000000, + SS_STS_HANDSHAKE = 0x20000000, +@@ -121,7 +123,9 @@ enum { + SS_I2H_REQUEST_RESET = 0x2000, + + SS_MU_OPERATIONAL = 0x80000000, ++}; + ++enum { + STEX_CDB_LENGTH = 16, + STATUS_VAR_LEN = 128, + diff --git a/queue-6.3/series b/queue-6.3/series index c21da58c29e..40595c94162 100644 --- a/queue-6.3/series +++ b/queue-6.3/series @@ -213,3 +213,12 @@ md-raid5-fix-miscalculation-of-end_sector-in-raid5_read_one_chunk.patch misc-fastrpc-reassign-memory-ownership-only-for-remote-heap.patch misc-fastrpc-return-epipe-to-invocations-on-device-removal.patch misc-fastrpc-reject-new-invocations-during-device-removal.patch +scsi-stex-fix-gcc-13-warnings.patch +ata-libata-scsi-use-correct-device-no-in-ata_find_dev.patch +drm-amdgpu-enable-tmz-by-default-for-gc-11.0.1.patch +drm-amd-pm-reverse-mclk-and-fclk-clocks-levels-for-smu-v13.0.4.patch +drm-amd-pm-reverse-mclk-and-fclk-clocks-levels-for-vangogh.patch +drm-amd-pm-resolve-reboot-exception-for-si-oland.patch +drm-amd-pm-reverse-mclk-clocks-levels-for-smu-v13.0.5.patch +drm-amd-pm-reverse-mclk-and-fclk-clocks-levels-for-yellow-carp.patch +drm-amd-pm-reverse-mclk-and-fclk-clocks-levels-for-renoir.patch