From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date: Tue, 19 Dec 2023 04:16:33 +0000 (+0800)
Subject: RISC-V: Remove 256/512/1024 VLS vectors
X-Git-Tag: basepoints/gcc-15~3466
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=caa2d2a588c028393fa153ddddb893040f8f9833;p=thirdparty%2Fgcc.git

RISC-V: Remove 256/512/1024 VLS vectors

Since https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=2e7abd09621a4401d44f4513adf126bce4b4828b
we only allow VLSmodes with size <= TARGET_MIN_VLEN * TARGET_MAX_LMUL.

So when -march=rv64gcv default LMUL = 1, we don't have VLS modes of 256/512/1024 vectors.

Disable them in vect test which fixes the following FAILs in the regression:

FAIL: gcc.dg/vect/bb-slp-pr65935.c -flto -ffat-lto-objects  scan-tree-dump-times slp1 "optimized: basic block" 11
FAIL: gcc.dg/vect/bb-slp-pr65935.c scan-tree-dump-times slp1 "optimized: basic block" 11
FAIL: gcc.dg/vect/bb-slp-subgroups-2.c -flto -ffat-lto-objects  scan-tree-dump-times slp2 "optimized: basic block" 1
FAIL: gcc.dg/vect/bb-slp-subgroups-2.c scan-tree-dump-times slp2 "optimized: basic block" 1

gcc/testsuite/ChangeLog:

	* lib/target-supports.exp: Remove 256/512/1024 vectors.
---

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 370df10978db..7f13ff0ca565 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -9033,7 +9033,7 @@ proc available_vector_sizes { } {
 	lappend result 4096 2048 1024 512 256 128 64 32 16 8 4 2
     } elseif { [istarget riscv*-*-*] } {
 	if { [check_effective_target_riscv_v] } {
-	    lappend result 0 32 64 128 256 512 1024
+	    lappend result 0 32 64 128
 	}
 	lappend result 128
     } else {