From: Hrushikesh Salunke <h-salunke@ti.com>
Date: Fri, 17 Oct 2025 08:46:53 +0000 (+0530)
Subject: arm64: dts: ti: k3-j784s4-j742s2-evm-common: Add bootph-all tag to SERDES0
X-Git-Tag: v6.19-rc1~100^2~18^2~21
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=cadd9234aedc9d4c5b4342f96a1ebe02314adeb2;p=thirdparty%2Fkernel%2Fstable.git

arm64: dts: ti: k3-j784s4-j742s2-evm-common: Add bootph-all tag to SERDES0

J784S4 SoC has two instances of PCIe which are PCIe0 and PCIe1. PCIe1
instance is used for PCIe boot process. J784S4 SoC has four instances
of 4-lane SERDES. Out of which SERDES0 is used as PHY for PCIe1. So it
needs to be functional at all stages of PCIe boot process. Thus add the
"bootph-all" boot phase tag to nodes required to enable SERDES0 at all
boot stages.

Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Link: https://patch.msgid.link/20251017084654.2929945-3-h-salunke@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
index 2834f0a8bbee..ed5146b69d56 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
@@ -970,6 +970,7 @@
 &serdes_refclk {
 	status = "okay";
 	clock-frequency = <100000000>;
+	bootph-all;
 };
 
 &dss {
@@ -984,6 +985,10 @@
 				 <&k3_clks 218 22>;
 };
 
+&serdes_ln_ctrl {
+	bootph-all;
+};
+
 &serdes0 {
 	status = "okay";
 
@@ -993,6 +998,7 @@
 		#phy-cells = <0>;
 		cdns,phy-type = <PHY_TYPE_PCIE>;
 		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
+		bootph-all;
 	};
 
 	serdes0_usb_link: phy@3 {