From: Greg Kroah-Hartman Date: Mon, 10 Feb 2014 20:02:52 +0000 (-0800) Subject: 3.10-stable patches X-Git-Tag: v3.4.80~37 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=cb0dfc8c26815a5b959e40184d42a155e36ba8d7;p=thirdparty%2Fkernel%2Fstable-queue.git 3.10-stable patches added patches: drm-radeon-dce4-clear-bios-scratch-dpms-bit-v2.patch drm-radeon-disable-ss-on-dp-for-dce3.x.patch drm-radeon-fix-dac-interrupt-handling-on-dce5.patch drm-radeon-fix-surface-sync-in-fence-on-cayman-v2.patch drm-radeon-set-the-full-cache-bit-for-fences-on-r7xx.patch drm-radeon-skip-colorbuffer-checking-if-color_info.format-is-set-to-invalid.patch --- diff --git a/queue-3.10/drm-radeon-dce4-clear-bios-scratch-dpms-bit-v2.patch b/queue-3.10/drm-radeon-dce4-clear-bios-scratch-dpms-bit-v2.patch new file mode 100644 index 00000000000..88b12dcffa8 --- /dev/null +++ b/queue-3.10/drm-radeon-dce4-clear-bios-scratch-dpms-bit-v2.patch @@ -0,0 +1,38 @@ +From 6802d4bad83f50081b2788698570218aaff8d10e Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Mon, 27 Jan 2014 18:29:35 -0500 +Subject: drm/radeon/DCE4+: clear bios scratch dpms bit (v2) + +From: Alex Deucher + +commit 6802d4bad83f50081b2788698570218aaff8d10e upstream. + +The BlankCrtc table in some DCE8 boards has some +logic shortcuts for the vbios when this bit is set. +Clear it for driver use. + +v2: fix typo + +Bug: +https://bugs.freedesktop.org/show_bug.cgi?id=73420 + +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/radeon_atombios.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/gpu/drm/radeon/radeon_atombios.c ++++ b/drivers/gpu/drm/radeon/radeon_atombios.c +@@ -2926,6 +2926,10 @@ void radeon_atom_initialize_bios_scratch + /* tell the bios not to handle mode switching */ + bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; + ++ /* clear the vbios dpms state */ ++ if (ASIC_IS_DCE4(rdev)) ++ bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE; ++ + if (rdev->family >= CHIP_R600) { + WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); + WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); diff --git a/queue-3.10/drm-radeon-disable-ss-on-dp-for-dce3.x.patch b/queue-3.10/drm-radeon-disable-ss-on-dp-for-dce3.x.patch new file mode 100644 index 00000000000..007025b1736 --- /dev/null +++ b/queue-3.10/drm-radeon-disable-ss-on-dp-for-dce3.x.patch @@ -0,0 +1,39 @@ +From d8e24525094200601236fa64a54cf73e3d682f2e Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Mon, 13 Jan 2014 16:47:05 -0500 +Subject: drm/radeon: disable ss on DP for DCE3.x + +From: Alex Deucher + +commit d8e24525094200601236fa64a54cf73e3d682f2e upstream. + +Seems to cause problems with certain DP monitors. + +Bug: +https://bugs.freedesktop.org/show_bug.cgi?id=40699 + +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/atombios_crtc.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/radeon/atombios_crtc.c ++++ b/drivers/gpu/drm/radeon/atombios_crtc.c +@@ -938,11 +938,14 @@ static bool atombios_crtc_prepare_pll(st + radeon_atombios_get_ppll_ss_info(rdev, + &radeon_crtc->ss, + ATOM_DP_SS_ID1); +- } else ++ } else { + radeon_crtc->ss_enabled = + radeon_atombios_get_ppll_ss_info(rdev, + &radeon_crtc->ss, + ATOM_DP_SS_ID1); ++ } ++ /* disable spread spectrum on DCE3 DP */ ++ radeon_crtc->ss_enabled = false; + } + break; + case ATOM_ENCODER_MODE_LVDS: diff --git a/queue-3.10/drm-radeon-fix-dac-interrupt-handling-on-dce5.patch b/queue-3.10/drm-radeon-fix-dac-interrupt-handling-on-dce5.patch new file mode 100644 index 00000000000..701e32e3298 --- /dev/null +++ b/queue-3.10/drm-radeon-fix-dac-interrupt-handling-on-dce5.patch @@ -0,0 +1,57 @@ +From e9a321c6b2ac954a7dbf235f419c255a424a1273 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Mon, 27 Jan 2014 11:54:44 -0500 +Subject: drm/radeon: fix DAC interrupt handling on DCE5+ + +From: Alex Deucher + +commit e9a321c6b2ac954a7dbf235f419c255a424a1273 upstream. + +DCE5 and newer hardware only has 1 DAC. Use the correct +offset. This may fix display problems on certain board +configurations. + +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/evergreen.c | 4 ++-- + drivers/gpu/drm/radeon/si.c | 2 +- + drivers/gpu/drm/radeon/sid.h | 2 +- + 3 files changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/radeon/evergreen.c ++++ b/drivers/gpu/drm/radeon/evergreen.c +@@ -3792,8 +3792,8 @@ void evergreen_disable_interrupt_state(s + WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); + } + +- /* only one DAC on DCE6 */ +- if (!ASIC_IS_DCE6(rdev)) ++ /* only one DAC on DCE5 */ ++ if (!ASIC_IS_DCE5(rdev)) + WREG32(DACA_AUTODETECT_INT_CONTROL, 0); + WREG32(DACB_AUTODETECT_INT_CONTROL, 0); + +--- a/drivers/gpu/drm/radeon/si.c ++++ b/drivers/gpu/drm/radeon/si.c +@@ -4519,7 +4519,7 @@ static void si_disable_interrupt_state(s + } + + if (!ASIC_IS_NODCE(rdev)) { +- WREG32(DACA_AUTODETECT_INT_CONTROL, 0); ++ WREG32(DAC_AUTODETECT_INT_CONTROL, 0); + + tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; + WREG32(DC_HPD1_INT_CONTROL, tmp); +--- a/drivers/gpu/drm/radeon/sid.h ++++ b/drivers/gpu/drm/radeon/sid.h +@@ -394,7 +394,7 @@ + # define GRPH_PFLIP_INT_MASK (1 << 0) + # define GRPH_PFLIP_INT_TYPE (1 << 8) + +-#define DACA_AUTODETECT_INT_CONTROL 0x66c8 ++#define DAC_AUTODETECT_INT_CONTROL 0x67c8 + + #define DC_HPD1_INT_STATUS 0x601c + #define DC_HPD2_INT_STATUS 0x6028 diff --git a/queue-3.10/drm-radeon-fix-surface-sync-in-fence-on-cayman-v2.patch b/queue-3.10/drm-radeon-fix-surface-sync-in-fence-on-cayman-v2.patch new file mode 100644 index 00000000000..b20b37d6a32 --- /dev/null +++ b/queue-3.10/drm-radeon-fix-surface-sync-in-fence-on-cayman-v2.patch @@ -0,0 +1,78 @@ +From 10e9ffae463396c5a25fdfe8a48d7c98a87f6b85 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Thu, 16 Jan 2014 18:02:59 -0500 +Subject: drm/radeon: fix surface sync in fence on cayman (v2) + +From: Alex Deucher + +commit 10e9ffae463396c5a25fdfe8a48d7c98a87f6b85 upstream. + +We need to set the engine bit to select the ME and +also set the full cache bit. Should help stability +on TN and cayman. + +V2: fix up surface sync in ib execute as well + +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/ni.c | 16 +++++++--------- + drivers/gpu/drm/radeon/nid.h | 1 + + 2 files changed, 8 insertions(+), 9 deletions(-) + +--- a/drivers/gpu/drm/radeon/ni.c ++++ b/drivers/gpu/drm/radeon/ni.c +@@ -1178,13 +1178,12 @@ void cayman_fence_ring_emit(struct radeo + { + struct radeon_ring *ring = &rdev->ring[fence->ring]; + u64 addr = rdev->fence_drv[fence->ring].gpu_addr; ++ u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA | ++ PACKET3_SH_ACTION_ENA; + + /* flush read cache over gart for this vmid */ +- radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); +- radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); +- radeon_ring_write(ring, 0); + radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); +- radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA); ++ radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); + radeon_ring_write(ring, 0xFFFFFFFF); + radeon_ring_write(ring, 0); + radeon_ring_write(ring, 10); /* poll interval */ +@@ -1200,6 +1199,8 @@ void cayman_fence_ring_emit(struct radeo + void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) + { + struct radeon_ring *ring = &rdev->ring[ib->ring]; ++ u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA | ++ PACKET3_SH_ACTION_ENA; + + /* set to DX10/11 mode */ + radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); +@@ -1224,14 +1225,11 @@ void cayman_ring_ib_execute(struct radeo + (ib->vm ? (ib->vm->id << 24) : 0)); + + /* flush read cache over gart for this vmid */ +- radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); +- radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); +- radeon_ring_write(ring, ib->vm ? ib->vm->id : 0); + radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); +- radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA); ++ radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); + radeon_ring_write(ring, 0xFFFFFFFF); + radeon_ring_write(ring, 0); +- radeon_ring_write(ring, 10); /* poll interval */ ++ radeon_ring_write(ring, ((ib->vm ? ib->vm->id : 0) << 24) | 10); /* poll interval */ + } + + void cayman_uvd_semaphore_emit(struct radeon_device *rdev, +--- a/drivers/gpu/drm/radeon/nid.h ++++ b/drivers/gpu/drm/radeon/nid.h +@@ -573,6 +573,7 @@ + # define PACKET3_DB_ACTION_ENA (1 << 26) + # define PACKET3_SH_ACTION_ENA (1 << 27) + # define PACKET3_SX_ACTION_ENA (1 << 28) ++# define PACKET3_ENGINE_ME (1 << 31) + #define PACKET3_ME_INITIALIZE 0x44 + #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) + #define PACKET3_COND_WRITE 0x45 diff --git a/queue-3.10/drm-radeon-set-the-full-cache-bit-for-fences-on-r7xx.patch b/queue-3.10/drm-radeon-set-the-full-cache-bit-for-fences-on-r7xx.patch new file mode 100644 index 00000000000..e3287a38905 --- /dev/null +++ b/queue-3.10/drm-radeon-set-the-full-cache-bit-for-fences-on-r7xx.patch @@ -0,0 +1,63 @@ +From d45b964a22cad962d3ede1eba8d24f5cee7b2a92 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Thu, 16 Jan 2014 18:11:47 -0500 +Subject: drm/radeon: set the full cache bit for fences on r7xx+ + +From: Alex Deucher + +commit d45b964a22cad962d3ede1eba8d24f5cee7b2a92 upstream. + +Needed to properly flush the read caches for fences. + +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/r600.c | 13 +++++++------ + drivers/gpu/drm/radeon/r600d.h | 1 + + 2 files changed, 8 insertions(+), 6 deletions(-) + +--- a/drivers/gpu/drm/radeon/r600.c ++++ b/drivers/gpu/drm/radeon/r600.c +@@ -2957,14 +2957,17 @@ void r600_fence_ring_emit(struct radeon_ + struct radeon_fence *fence) + { + struct radeon_ring *ring = &rdev->ring[fence->ring]; ++ u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA | ++ PACKET3_SH_ACTION_ENA; ++ ++ if (rdev->family >= CHIP_RV770) ++ cp_coher_cntl |= PACKET3_FULL_CACHE_ENA; + + if (rdev->wb.use_event) { + u64 addr = rdev->fence_drv[fence->ring].gpu_addr; + /* flush read cache over gart */ + radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); +- radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | +- PACKET3_VC_ACTION_ENA | +- PACKET3_SH_ACTION_ENA); ++ radeon_ring_write(ring, cp_coher_cntl); + radeon_ring_write(ring, 0xFFFFFFFF); + radeon_ring_write(ring, 0); + radeon_ring_write(ring, 10); /* poll interval */ +@@ -2978,9 +2981,7 @@ void r600_fence_ring_emit(struct radeon_ + } else { + /* flush read cache over gart */ + radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); +- radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | +- PACKET3_VC_ACTION_ENA | +- PACKET3_SH_ACTION_ENA); ++ radeon_ring_write(ring, cp_coher_cntl); + radeon_ring_write(ring, 0xFFFFFFFF); + radeon_ring_write(ring, 0); + radeon_ring_write(ring, 10); /* poll interval */ +--- a/drivers/gpu/drm/radeon/r600d.h ++++ b/drivers/gpu/drm/radeon/r600d.h +@@ -1283,6 +1283,7 @@ + # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) + #define PACKET3_SURFACE_SYNC 0x43 + # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) ++# define PACKET3_FULL_CACHE_ENA (1 << 20) /* r7xx+ only */ + # define PACKET3_TC_ACTION_ENA (1 << 23) + # define PACKET3_VC_ACTION_ENA (1 << 24) + # define PACKET3_CB_ACTION_ENA (1 << 25) diff --git a/queue-3.10/drm-radeon-skip-colorbuffer-checking-if-color_info.format-is-set-to-invalid.patch b/queue-3.10/drm-radeon-skip-colorbuffer-checking-if-color_info.format-is-set-to-invalid.patch new file mode 100644 index 00000000000..a77f224f815 --- /dev/null +++ b/queue-3.10/drm-radeon-skip-colorbuffer-checking-if-color_info.format-is-set-to-invalid.patch @@ -0,0 +1,52 @@ +From 56492e0fac2dbaf7735ffd66b206a90624917789 Mon Sep 17 00:00:00 2001 +From: Marek Olšák +Date: Wed, 8 Jan 2014 18:16:26 +0100 +Subject: drm/radeon: skip colorbuffer checking if COLOR_INFO.FORMAT is set to INVALID +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Marek Olšák + +commit 56492e0fac2dbaf7735ffd66b206a90624917789 upstream. + +This fixes a bug which was causing rejections of valid GPU commands +from userspace. + +Signed-off-by: Marek Olšák +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/evergreen_cs.c | 5 ++++- + drivers/gpu/drm/radeon/r600_cs.c | 5 ++++- + 2 files changed, 8 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/radeon/evergreen_cs.c ++++ b/drivers/gpu/drm/radeon/evergreen_cs.c +@@ -967,7 +967,10 @@ static int evergreen_cs_track_check(stru + if (track->cb_dirty) { + tmp = track->cb_target_mask; + for (i = 0; i < 8; i++) { +- if ((tmp >> (i * 4)) & 0xF) { ++ u32 format = G_028C70_FORMAT(track->cb_color_info[i]); ++ ++ if (format != V_028C70_COLOR_INVALID && ++ (tmp >> (i * 4)) & 0xF) { + /* at least one component is enabled */ + if (track->cb_color_bo[i] == NULL) { + dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", +--- a/drivers/gpu/drm/radeon/r600_cs.c ++++ b/drivers/gpu/drm/radeon/r600_cs.c +@@ -749,7 +749,10 @@ static int r600_cs_track_check(struct ra + } + + for (i = 0; i < 8; i++) { +- if ((tmp >> (i * 4)) & 0xF) { ++ u32 format = G_0280A0_FORMAT(track->cb_color_info[i]); ++ ++ if (format != V_0280A0_COLOR_INVALID && ++ (tmp >> (i * 4)) & 0xF) { + /* at least one component is enabled */ + if (track->cb_color_bo[i] == NULL) { + dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", diff --git a/queue-3.10/series b/queue-3.10/series index b6cd48d23b9..ba0e8cc0007 100644 --- a/queue-3.10/series +++ b/queue-3.10/series @@ -49,3 +49,9 @@ nxt200x-increase-write-buffer-size.patch dib8000-fix-regression-with-dib807x.patch m88rs2000-add-m88rs2000_set_carrieroffset.patch m88rs2000-set-symbol-rate-accurately.patch +drm-radeon-skip-colorbuffer-checking-if-color_info.format-is-set-to-invalid.patch +drm-radeon-disable-ss-on-dp-for-dce3.x.patch +drm-radeon-fix-surface-sync-in-fence-on-cayman-v2.patch +drm-radeon-set-the-full-cache-bit-for-fences-on-r7xx.patch +drm-radeon-fix-dac-interrupt-handling-on-dce5.patch +drm-radeon-dce4-clear-bios-scratch-dpms-bit-v2.patch