From: Jennifer Schmitz Date: Fri, 11 Jul 2025 13:07:30 +0000 (-0700) Subject: AArch64: Annotate SVE instructions with new instruction attribute. X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=cb80cdbef47fa06538c763315e563216ace3673d;p=thirdparty%2Fgcc.git AArch64: Annotate SVE instructions with new instruction attribute. In this patch, we add the new instruction attribute "sve_type" and use it to annotate the SVE instructions in aarch64-sve.md and aarch64-sve2.md. This allows us to use instruction attributes to group instructions into dispatch groups for dispatch scheduling. While there had already been fine-grained annotation of scalar and neon instructions (mostly using the "type"-attribute), annotation was missing for SVE instructions. The values of the attribute "sve_type" are comparatively coarse-grained, but fulfill the two criteria we aimed for with regard to dispatch scheduling: - the annotation allows the definition of CPU-specific high-level attributes mapping instructions to dispatch constraints - the annotation is by itself CPU-independent and consistent, i.e. all instructions fulfilling certain criteria are tagged with the corresponding value The patch was bootstrapped and tested on aarch64-linux-gnu, no regression. Signed-off-by: Jennifer Schmitz gcc/ChangeLog: * config/aarch64/aarch64-sve.md: Annotate instructions with attribute sve_type. * config/aarch64/aarch64-sve2.md: Likewise. * config/aarch64/aarch64.md (sve_type): New attribute sve_type. * config/aarch64/iterators.md (sve_type_unspec): New int attribute. (sve_type_int): New code attribute. (sve_type_fp): New int attribute. --- diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 1ebcffe88a3..8c47d441c3f 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -696,11 +696,11 @@ && ((lra_in_progress || reload_completed) || (register_operand (operands[0], mode) && nonmemory_operand (operands[1], mode)))" - {@ [ cons: =0 , 1 ] - [ w , Utr ] ldr\t%0, %1 - [ Utr , w ] str\t%1, %0 - [ w , w ] mov\t%0.d, %1.d - [ w , Dn ] << aarch64_output_sve_mov_immediate (operands[1]); + {@ [ cons: =0 , 1 ; attrs: sve_type ] + [ w , Utr ; sve_load_1reg ] ldr\t%0, %1 + [ Utr , w ; sve_store_1reg ] str\t%1, %0 + [ w , w ; * ] mov\t%0.d, %1.d + [ w , Dn ; * ] << aarch64_output_sve_mov_immediate (operands[1]); } ) @@ -719,7 +719,10 @@ "#" "&& 1" [(set (match_dup 0) - (match_dup 2))]) + (match_dup 2))] + {} + [(set_attr "sve_type" "sve_load_1reg,sve_store_1reg")] +) ;; Unpredicated moves that cannot use LDR and STR, i.e. partial vectors ;; or vectors for which little-endian ordering isn't acceptable. Memory @@ -772,10 +775,10 @@ "TARGET_SVE && (register_operand (operands[0], mode) || register_operand (operands[2], mode))" - {@ [ cons: =0 , 1 , 2 ] - [ w , Upl , w ] # - [ w , Upl , m ] ld1\t%0., %1/z, %2 - [ m , Upl , w ] st1\t%2., %1, %0 + {@ [ cons: =0 , 1 , 2 ; attrs: sve_type ] + [ w , Upl , w ; * ] # + [ w , Upl , m ; sve_load_1reg ] ld1\t%0., %1/z, %2 + [ m , Upl , w ; sve_store_1reg ] st1\t%2., %1, %0 } "&& register_operand (operands[0], mode) && register_operand (operands[2], mode)" @@ -976,11 +979,11 @@ "TARGET_SVE && (register_operand (operands[0], mode) || register_operand (operands[1], mode))" - {@ [ cons: =0 , 1 ] - [ Upa , Upa ] mov\t%0.b, %1.b - [ m , Upa ] str\t%1, %0 - [ Upa , m ] ldr\t%0, %1 - [ Upa , Dn ] << aarch64_output_sve_mov_immediate (operands[1]); + {@ [ cons: =0 , 1 ; attrs: sve_type ] + [ Upa , Upa ; sve_pred_misc ] mov\t%0.b, %1.b + [ m , Upa ; sve_store_pred ] str\t%1, %0 + [ Upa , m ; sve_load_pred ] ldr\t%0, %1 + [ Upa , Dn ; sve_pred_misc ] << aarch64_output_sve_mov_immediate (operands[1]); } ) @@ -1007,6 +1010,7 @@ { operands[2] = operands[3] = CONSTM1_RTX (VNx16BImode); } + [(set_attr "sve_type" "sve_pred_misc")] ) ;; Match PTRUES Pn.[HSD] when both the predicate and flags are useful. @@ -1034,6 +1038,7 @@ operands[2] = CONSTM1_RTX (VNx16BImode); operands[3] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_pred_misc")] ) ;; Match PTRUES Pn.B when only the flags result is useful (which is @@ -1059,6 +1064,7 @@ { operands[2] = operands[3] = CONSTM1_RTX (VNx16BImode); } + [(set_attr "sve_type" "sve_pred_misc")] ) ;; Match PTRUES Pn.[HWD] when only the flags result is useful (which is @@ -1086,6 +1092,7 @@ operands[2] = CONSTM1_RTX (VNx16BImode); operands[3] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_pred_misc")] ) ;; ------------------------------------------------------------------------- @@ -1131,6 +1138,7 @@ [ Dm ] setffr [ Upa ] wrffr\t%0.b } + [(set_attr "sve_type" "sve_ffr")] ) ;; [L2 in the block comment above about FFR handling] @@ -1170,6 +1178,7 @@ (reg:VNx16BI FFRT_REGNUM))] "TARGET_SVE && TARGET_NON_STREAMING" "rdffr\t%0.b" + [(set_attr "sve_type" "sve_ffr")] ) ;; Likewise with zero predication. @@ -1184,6 +1193,7 @@ [ ?Upa , 0Upa; yes ] ^ [ Upa , Upa ; no ] ^ } + [(set_attr "sve_type" "sve_ffr")] ) ;; Read the FFR to test for a fault, without using the predicate result. @@ -1204,6 +1214,7 @@ [ ?Upa , 0Upa; yes ] ^ [ Upa , Upa ; no ] ^ } + [(set_attr "sve_type" "sve_ffr")] ) ;; Same for unpredicated RDFFR when tested with a known PTRUE. @@ -1222,6 +1233,7 @@ [ ?Upa , 0Upa; yes ] ^ [ Upa , Upa ; no ] ^ } + [(set_attr "sve_type" "sve_ffr")] ) ;; Read the FFR with zero predication and test the result. @@ -1245,6 +1257,7 @@ [ ?Upa , 0Upa; yes ] ^ [ Upa , Upa ; no ] ^ } + [(set_attr "sve_type" "sve_ffr")] ) ;; Same for unpredicated RDFFR when tested with a known PTRUE. @@ -1264,6 +1277,7 @@ [ ?Upa , 0Upa; yes ] ^ [ Upa , Upa ; no ] ^ } + [(set_attr "sve_type" "sve_ffr")] ) ;; [R3 in the block comment above about FFR handling] @@ -1331,6 +1345,7 @@ UNSPEC_LD1_SVE))] "TARGET_SVE" "ld1\t%0., %2/z, %1" + [(set_attr "sve_type" "sve_load_1reg")] ) ;; Unpredicated LD[234]. @@ -1358,6 +1373,7 @@ UNSPEC_LDN))] "TARGET_SVE" "ld\t%0, %2/z, %1" + [(set_attr "sve_type" "sve_load_reg")] ) ;; ------------------------------------------------------------------------- @@ -1390,6 +1406,7 @@ { operands[3] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_load_1reg")] ) ;; Same as above without the maskload_else_operand to still allow combine to @@ -1410,6 +1427,7 @@ { operands[3] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_load_1reg")] ) ;; ------------------------------------------------------------------------- @@ -1436,6 +1454,7 @@ SVE_LDFF1_LDNF1))] "TARGET_SVE && TARGET_NON_STREAMING" "ldf1\t%0., %2/z, %1" + [(set_attr "sve_type" "sve_load_1reg")] ) ;; ------------------------------------------------------------------------- @@ -1476,6 +1495,7 @@ { operands[3] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_load_1reg")] ) ;; ------------------------------------------------------------------------- @@ -1498,6 +1518,7 @@ UNSPEC_LDNT1_SVE))] "TARGET_SVE" "ldnt1\t%0., %2/z, %1" + [(set_attr "sve_type" "sve_load_1reg")] ) ;; ------------------------------------------------------------------------- @@ -1555,6 +1576,7 @@ [&w, rk, w, Ui1, i, Upl] ld1\t%0.s, %5/z, [%1, %2.s, uxtw %p4] [?w, rk, 0, Ui1, i, Upl] ^ } + [(set_attr "sve_type" "sve_gatherload_32")] ) ;; Predicated gather loads for 64-bit elements. The value of operand 3 @@ -1581,6 +1603,7 @@ [&w, rk, w, i, i, Upl] ld1\t%0.d, %5/z, [%1, %2.d, lsl %p4] [?w, rk, 0, i, i, Upl] ^ } + [(set_attr "sve_type" "sve_gatherload_64")] ) ;; Likewise, but with the offset being extended from 32 bits. @@ -1610,6 +1633,7 @@ { operands[6] = CONSTM1_RTX (VNx2BImode); } + [(set_attr "sve_type" "sve_gatherload_64")] ) ;; Likewise, but with the offset being truncated to 32 bits and then @@ -1641,6 +1665,7 @@ { operands[6] = CONSTM1_RTX (VNx2BImode); } + [(set_attr "sve_type" "sve_gatherload_64")] ) ;; Likewise, but with the offset being truncated to 32 bits and then @@ -1665,6 +1690,7 @@ [&w, rk, w, i, i, Upl ] ld1\t%0.d, %5/z, [%1, %2.d, uxtw %p4] [?w, rk, 0, i, i, Upl ] ^ } + [(set_attr "sve_type" "sve_gatherload_64")] ) ;; ------------------------------------------------------------------------- @@ -1717,6 +1743,7 @@ { operands[6] = CONSTM1_RTX (VNx4BImode); } + [(set_attr "sve_type" "sve_gatherload_32")] ) ;; Predicated extending gather loads for 64-bit elements. The value of @@ -1753,6 +1780,7 @@ { operands[6] = CONSTM1_RTX (VNx2BImode); } + [(set_attr "sve_type" "sve_gatherload_64")] ) ;; Likewise, but with the offset being extended from 32 bits. @@ -1789,6 +1817,7 @@ operands[6] = CONSTM1_RTX (VNx2BImode); operands[7] = CONSTM1_RTX (VNx2BImode); } + [(set_attr "sve_type" "sve_gatherload_64")] ) ;; Likewise, but with the offset being truncated to 32 bits and then @@ -1827,6 +1856,7 @@ operands[6] = CONSTM1_RTX (VNx2BImode); operands[7] = CONSTM1_RTX (VNx2BImode); } + [(set_attr "sve_type" "sve_gatherload_64")] ) ;; Likewise, but with the offset being truncated to 32 bits and then @@ -1861,6 +1891,7 @@ { operands[7] = CONSTM1_RTX (VNx2BImode); } + [(set_attr "sve_type" "sve_gatherload_64")] ) ;; ------------------------------------------------------------------------- @@ -1899,6 +1930,7 @@ [&w, rk, w, Ui1, i, Upl] ldff1w\t%0.s, %5/z, [%1, %2.s, uxtw %p4] [?w, rk, 0, Ui1, i, Upl] ^ } + [(set_attr "sve_type" "sve_gatherload_32")] ) ;; Predicated first-faulting gather loads for 64-bit elements. The value @@ -1925,6 +1957,7 @@ [&w, rk, w, i, i, Upl ] ldff1d\t%0.d, %5/z, [%1, %2.d, lsl %p4] [?w, rk, 0, i, i, Upl ] ^ } + [(set_attr "sve_type" "sve_gatherload_64")] ) ;; Likewise, but with the offset being sign-extended from 32 bits. @@ -1955,6 +1988,7 @@ { operands[6] = CONSTM1_RTX (VNx2BImode); } + [(set_attr "sve_type" "sve_gatherload_64")] ) ;; Likewise, but with the offset being zero-extended from 32 bits. @@ -1978,6 +2012,7 @@ [&w, rk, w, i, i, Upl ] ldff1d\t%0.d, %5/z, [%1, %2.d, uxtw %p4] [?w, rk, 0, i, i, Upl ] ^ } + [(set_attr "sve_type" "sve_gatherload_64")] ) ;; ------------------------------------------------------------------------- @@ -2028,6 +2063,7 @@ { operands[6] = CONSTM1_RTX (VNx4BImode); } + [(set_attr "sve_type" "sve_gatherload_32")] ) ;; Predicated extending first-faulting gather loads for 64-bit elements. @@ -2062,6 +2098,7 @@ { operands[6] = CONSTM1_RTX (VNx2BImode); } + [(set_attr "sve_type" "sve_gatherload_64")] ) ;; Likewise, but with the offset being sign-extended from 32 bits. @@ -2097,6 +2134,7 @@ operands[6] = CONSTM1_RTX (VNx2BImode); operands[7] = CONSTM1_RTX (VNx2BImode); } + [(set_attr "sve_type" "sve_gatherload_64")] ) ;; Likewise, but with the offset being zero-extended from 32 bits. @@ -2128,6 +2166,7 @@ { operands[7] = CONSTM1_RTX (VNx2BImode); } + [(set_attr "sve_type" "sve_gatherload_64")] ) ;; ========================================================================= @@ -2349,6 +2388,7 @@ UNSPEC_ST1_SVE))] "TARGET_SVE" "st1\t%1., %2, %0" + [(set_attr "sve_type" "sve_store_1reg")] ) ;; Unpredicated ST[234]. This is always a full update, so the dependence @@ -2379,6 +2419,7 @@ UNSPEC_STN))] "TARGET_SVE" "st\t%1, %2, %0" + [(set_attr "sve_type" "sve_store_reg")] ) ;; ------------------------------------------------------------------------- @@ -2401,6 +2442,7 @@ UNSPEC_ST1_SVE))] "TARGET_SVE" "st1\t%1., %2, %0" + [(set_attr "sve_type" "sve_store_1reg")] ) ;; Predicated truncate and store, with 4 elements per 128-bit block. @@ -2414,6 +2456,7 @@ UNSPEC_ST1_SVE))] "TARGET_SVE" "st1\t%1., %2, %0" + [(set_attr "sve_type" "sve_store_1reg")] ) ;; Predicated truncate and store, with 2 elements per 128-bit block. @@ -2427,6 +2470,7 @@ UNSPEC_ST1_SVE))] "TARGET_SVE" "st1\t%1., %2, %0" + [(set_attr "sve_type" "sve_store_1reg")] ) ;; ------------------------------------------------------------------------- @@ -2448,6 +2492,7 @@ UNSPEC_STNT1_SVE))] "TARGET_SVE" "stnt1\t%1., %2, %0" + [(set_attr "sve_type" "sve_store_1reg")] ) ;; ------------------------------------------------------------------------- @@ -2496,6 +2541,7 @@ [ rk , w , Z , i , w , Upl ] st1\t%4.s, %5, [%0, %1.s, sxtw %p3] [ rk , w , Ui1 , i , w , Upl ] st1\t%4.s, %5, [%0, %1.s, uxtw %p3] } + [(set_attr "sve_type" "sve_scatterstore_32")] ) ;; Predicated scatter stores for 64-bit elements. The value of operand 2 @@ -2517,6 +2563,7 @@ [ rk , w , Ui1 , w , Upl ] st1\t%4.d, %5, [%0, %1.d] [ rk , w , i , w , Upl ] st1\t%4.d, %5, [%0, %1.d, lsl %p3] } + [(set_attr "sve_type" "sve_scatterstore_64")] ) ;; Likewise, but with the offset being extended from 32 bits. @@ -2543,6 +2590,7 @@ { operands[6] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_scatterstore_64")] ) ;; Likewise, but with the offset being truncated to 32 bits and then @@ -2571,6 +2619,7 @@ { operands[6] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_scatterstore_64")] ) ;; Likewise, but with the offset being truncated to 32 bits and then @@ -2592,6 +2641,7 @@ [ rk , w , Ui1 , w , Upl ] st1\t%4.d, %5, [%0, %1.d, uxtw] [ rk , w , i , w , Upl ] st1\t%4.d, %5, [%0, %1.d, uxtw %p3] } + [(set_attr "sve_type" "sve_scatterstore_64")] ) ;; ------------------------------------------------------------------------- @@ -2625,6 +2675,7 @@ [ w , Z , w , Upl ] st1\t%4.s, %5, [%0, %1.s, sxtw %p3] [ w , Ui1 , w , Upl ] st1\t%4.s, %5, [%0, %1.s, uxtw %p3] } + [(set_attr "sve_type" "sve_scatterstore_32")] ) ;; Predicated truncating scatter stores for 64-bit elements. The value of @@ -2647,6 +2698,7 @@ [ w , w , Upl ] st1\t%4.d, %5, [%0, %1.d] [ w , w , Upl ] st1\t%4.d, %5, [%0, %1.d, lsl %p3] } + [(set_attr "sve_type" "sve_scatterstore_64")] ) ;; Likewise, but with the offset being sign-extended from 32 bits. @@ -2675,6 +2727,7 @@ { operands[6] = copy_rtx (operands[5]); } + [(set_attr "sve_type" "sve_scatterstore_64")] ) ;; Likewise, but with the offset being zero-extended from 32 bits. @@ -2696,6 +2749,7 @@ [ rk , w , w , Upl ] st1\t%4.d, %5, [%0, %1.d, uxtw] [ rk , w , w , Upl ] st1\t%4.d, %5, [%0, %1.d, uxtw %p3] } + [(set_attr "sve_type" "sve_scatterstore_64")] ) ;; ========================================================================= @@ -2808,6 +2862,7 @@ emit_insn (gen_aarch64_sve_ld1rq (operands[0], operands[1], gp)); DONE; } + [(set_attr "sve_type" "sve_int_general")] ) ;; Duplicate an Advanced SIMD vector to fill an SVE vector (BE version). @@ -2829,6 +2884,7 @@ operands[1] = gen_rtx_REG (mode, REGNO (operands[1])); return "dup\t%0.q, %1.q[0]"; } + [(set_attr "sve_type" "sve_int_general")] ) ;; This is used for vec_duplicates from memory, but can also @@ -2844,6 +2900,7 @@ UNSPEC_SEL))] "TARGET_SVE" "ld1r\t%0., %1/z, %2" + [(set_attr "sve_type" "sve_load_1reg")] ) ;; Load 128 bits from memory under predicate control and duplicate to @@ -2859,6 +2916,7 @@ operands[1] = gen_rtx_MEM (mode, XEXP (operands[1], 0)); return "ld1rq\t%0., %2/z, %1"; } + [(set_attr "sve_type" "sve_load_1reg")] ) (define_insn "@aarch64_sve_ld1ro" @@ -2873,6 +2931,7 @@ operands[1] = gen_rtx_MEM (mode, XEXP (operands[1], 0)); return "ld1ro\t%0., %2/z, %1"; } + [(set_attr "sve_type" "sve_load_1reg")] ) ;; ------------------------------------------------------------------------- @@ -2939,6 +2998,7 @@ [ ??&w , w , rZ ; yes ] movprfx\t%0, %1\;insr\t%0., %2 [ ?&w , w , w ; yes ] movprfx\t%0, %1\;insr\t%0., %2 } + [(set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -2954,10 +3014,10 @@ (match_operand: 1 "aarch64_sve_index_operand") (match_operand: 2 "aarch64_sve_index_operand")))] "TARGET_SVE" - {@ [ cons: =0 , 1 , 2 ] - [ w , Usi , r ] index\t%0., #%1, %2 - [ w , r , Usi ] index\t%0., %1, #%2 - [ w , r , r ] index\t%0., %1, %2 + {@ [ cons: =0 , 1 , 2 ; attrs: sve_type ] + [ w , Usi , r ; sve_int_index ] index\t%0., #%1, %2 + [ w , r , Usi ; sve_int_index ] index\t%0., %1, #%2 + [ w , r , r ; sve_int_index ] index\t%0., %1, %2 } ) @@ -2974,6 +3034,7 @@ operands[2] = aarch64_check_zero_based_sve_index_immediate (operands[2]); return "index\t%0., %1, #%2"; } + [(set_attr "sve_type" "sve_int_index")] ) ;; ------------------------------------------------------------------------- @@ -3124,6 +3185,7 @@ operands[0] = gen_rtx_REG (mode, REGNO (operands[0])); return "dup\t%0., %1.[%2]"; } + [(set_attr "sve_type" "sve_int_general")] ) ;; Extract an element outside the range of DUP. This pattern requires the @@ -3141,7 +3203,8 @@ ? "ext\t%0.b, %0.b, %0.b, #%2" : "movprfx\t%0, %1\;ext\t%0.b, %0.b, %1.b, #%2"); } - [(set_attr "movprfx" "*,yes")] + [(set_attr "movprfx" "*,yes") + (set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -3161,9 +3224,9 @@ (match_operand:SVE_ALL 2 "register_operand")] LAST))] "TARGET_SVE" - {@ [ cons: =0 , 1 , 2 ] - [ ?r , Upl , w ] last\t%0, %1, %2. - [ w , Upl , w ] last\t%0, %1, %2. + {@ [ cons: =0 , 1 , 2 ; attrs: sve_type ] + [ ?r , Upl , w ; sve_int_extract ] last\t%0, %1, %2. + [ w , Upl , w ; sve_int_extract ] last\t%0, %1, %2. } ) @@ -3253,6 +3316,7 @@ [ w , Upl , 0 ; * ] \t%Z0., %1/m, %Z2. [ ?&w , Upl , w ; yes ] movprfx\t%Z0, %Z2\;\t%Z0., %1/m, %Z2. } + [(set_attr "sve_type" "sve_int_general")] ) ;; Predicated integer unary arithmetic with merging. @@ -3281,6 +3345,7 @@ [ w , Upl , 0 ; * ] \t%0., %1/m, %0. [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_int_general")] ) ;; Predicated integer unary arithmetic, merging with an independent value. @@ -3304,6 +3369,7 @@ [ ?&w , Upl , w , Dz ; yes ] movprfx\t%0., %1/z, %2.\;\t%0., %1/m, %2. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_int_general")] ) @@ -3385,6 +3451,7 @@ [ w , Upl , 0 ; * ] \t%0., %1/m, %2. [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_int_general")] ) ;; Another way of expressing the REVB, REVH and REVW patterns, with this @@ -3404,6 +3471,7 @@ [ w , Upl , 0 ; * ] rev\t%0., %1/m, %2. [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;rev\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_int_general")] ) ;; Predicated integer unary operations with merging. @@ -3422,6 +3490,7 @@ [ ?&w , Upl , w , Dz ; yes ] movprfx\t%0., %1/z, %2.\;\t%0., %1/m, %2. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -3463,6 +3532,7 @@ [ w , Upl , 0 ; * ] xt\t%0., %1/m, %2. [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;xt\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_int_extend")] ) ;; Predicated truncate-and-sign-extend operations. @@ -3480,6 +3550,7 @@ [ w , Upl , 0 ; * ] sxt\t%0., %1/m, %2. [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;sxt\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_int_extend")] ) ;; Predicated truncate-and-sign-extend operations with merging. @@ -3499,6 +3570,7 @@ [ ?&w , Upl , w , Dz ; yes ] movprfx\t%0., %1/z, %2.\;sxt\t%0., %1/m, %2. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;sxt\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_int_extend")] ) ;; Predicated truncate-and-zero-extend operations, merging with the @@ -3520,6 +3592,7 @@ [ w , Upl , 0 ; * ] uxt%e3\t%0., %1/m, %0. [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;uxt%e3\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_int_extend")] ) ;; Predicated truncate-and-zero-extend operations, merging with an @@ -3545,6 +3618,7 @@ [ ?&w , Upl , w , Dz ; yes ] movprfx\t%0., %1/z, %2.\;uxt%e3\t%0., %1/m, %2. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %4\;uxt%e3\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_int_extend")] ) ;; ------------------------------------------------------------------------- @@ -3616,6 +3690,7 @@ [ w , Upl , 0 ; * ] cnot\t%0., %1/m, %2. [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;cnot\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_int_general")] ) ;; Predicated logical inverse with merging. @@ -3672,6 +3747,7 @@ { operands[5] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_int_general")] ) ;; Predicated logical inverse, merging with an independent value. @@ -3709,6 +3785,7 @@ { operands[5] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -3726,6 +3803,7 @@ SVE_FP_UNARY_INT))] "TARGET_SVE" "\t%0., %1." + [(set_attr "sve_type" "sve_fp_exp")] ) ;; ------------------------------------------------------------------------- @@ -3755,6 +3833,7 @@ SVE_FP_UNARY))] "TARGET_SVE" "\t%0., %1." + [(set_attr "sve_type" "sve_")] ) ;; Unpredicated floating-point unary operations. @@ -3800,6 +3879,7 @@ [ w , Upl , 0 ; * ] \t%0., %1/m, %2. [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_")] ) ;; Predicated floating-point unary arithmetic with merging. @@ -3838,6 +3918,7 @@ { operands[3] = copy_rtx (operands[1]); } + [(set_attr "sve_type" "sve_")] ) (define_insn "*cond__2_strict" @@ -3856,6 +3937,7 @@ [ w , Upl , 0 ; * ] \t%0., %1/m, %0. [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_")] ) ;; Predicated floating-point unary arithmetic, merging with an independent @@ -3887,6 +3969,7 @@ { operands[4] = copy_rtx (operands[1]); } + [(set_attr "sve_type" "sve_")] ) (define_insn "*cond__any_strict" @@ -3906,6 +3989,7 @@ [ ?&w , Upl , w , Dz ; yes ] movprfx\t%0., %1/z, %2.\;\t%0., %1/m, %2. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_")] ) ;; ------------------------------------------------------------------------- @@ -3986,6 +4070,7 @@ (match_operand:PRED_ALL 1 "register_operand" "Upa")))] "TARGET_SVE" "not\t%0.b, %1/z, %2.b" + [(set_attr "sve_type" "sve_pred_logical")] ) ;; Predicated predicate inverse in which the flags are set in the same @@ -4005,6 +4090,7 @@ (and:PRED_ALL (not:PRED_ALL (match_dup 2)) (match_dup 3)))] "TARGET_SVE" "nots\t%0.b, %1/z, %2.b" + [(set_attr "sve_type" "sve_pred_logical")] ) ;; Same, where only the flags result is interesting. @@ -4022,6 +4108,7 @@ (clobber (match_scratch:PRED_ALL 0 "=Upa"))] "TARGET_SVE" "nots\t%0.b, %1/z, %2.b" + [(set_attr "sve_type" "sve_pred_logical")] ) ;; ========================================================================= @@ -4121,6 +4208,7 @@ [(set (match_dup 0) (SVE_INT_BINARY_IMM:SVE_I_SIMD_DI (match_dup 2) (match_dup 3)))] "" + [(set_attr "sve_type" "sve_")] ) ;; Unpredicated binary operations with a constant (post-RA only). @@ -4135,7 +4223,8 @@ "@ \t%Z0., %Z0., #%2 movprfx\t%Z0, %Z1\;\t%Z0., %Z0., #%2" - [(set_attr "movprfx" "*,yes")] + [(set_attr "movprfx" "*,yes") + (set_attr "sve_type" "sve_")] ) ;; Predicated integer operations with merging. @@ -4166,6 +4255,7 @@ [ w , Upl , 0 , w ; * ] \t%0., %1/m, %0., %3. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %0., %3. } + [(set_attr "sve_type" "sve_")] ) ;; Predicated integer operations, merging with the second input. @@ -4183,6 +4273,7 @@ [ w , Upl , w , 0 ; * ] \t%0., %1/m, %0., %2. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;\t%0., %1/m, %0., %2. } + [(set_attr "sve_type" "sve_")] ) ;; Predicated integer operations, merging with an independent value. @@ -4213,7 +4304,8 @@ operands[4], operands[1])); operands[4] = operands[2] = operands[0]; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_")] ) ;; ------------------------------------------------------------------------- @@ -4246,6 +4338,7 @@ [ ?w , w , vsn ; yes ] movprfx\t%0, %1\;sub\t%0., %0., #%N2 [ w , w , w ; * ] add\t%0., %1., %2. } + [(set_attr "sve_type" "sve_int_general")] ) ;; Merging forms are handled through SVE_INT_BINARY. @@ -4269,6 +4362,7 @@ [ w , vsa , 0 ; * ] subr\t%0., %0., #%D1 [ ?&w , vsa , w ; yes ] movprfx\t%0, %2\;subr\t%0., %0., #%D1 } + [(set_attr "sve_type" "sve_int_general")] ) ;; Merging forms are handled through SVE_INT_BINARY. @@ -4290,6 +4384,7 @@ UNSPEC_ADR))] "TARGET_SVE && TARGET_NON_STREAMING" "adr\t%0., [%1., %2.]" + [(set_attr "sve_type" "sve_int_general")] ) ;; Same, but with the offset being sign-extended from the low 32 bits. @@ -4310,6 +4405,7 @@ { operands[3] = CONSTM1_RTX (VNx2BImode); } + [(set_attr "sve_type" "sve_int_general")] ) ;; Same, but with the offset being zero-extended from the low 32 bits. @@ -4323,6 +4419,7 @@ UNSPEC_ADR))] "TARGET_SVE && TARGET_NON_STREAMING" "adr\t%0.d, [%1.d, %2.d, uxtw]" + [(set_attr "sve_type" "sve_int_general")] ) ;; Same, matching as a PLUS rather than unspec. @@ -4335,6 +4432,7 @@ (match_operand:VNx2DI 1 "register_operand" "w")))] "TARGET_SVE && TARGET_NON_STREAMING" "adr\t%0.d, [%1.d, %2.d, uxtw]" + [(set_attr "sve_type" "sve_int_general")] ) ;; ADR with a nonzero shift. @@ -4357,6 +4455,7 @@ (match_operand:SVE_24I 1 "register_operand" "w")))] "TARGET_SVE && TARGET_NON_STREAMING" "adr\t%0., [%1., %2., lsl %3]" + [(set_attr "sve_type" "sve_int_general")] ) ;; Same, but with the index being sign-extended from the low 32 bits. @@ -4378,6 +4477,7 @@ { operands[4] = CONSTM1_RTX (VNx2BImode); } + [(set_attr "sve_type" "sve_int_general")] ) ;; Same, but with the index being zero-extended from the low 32 bits. @@ -4392,6 +4492,7 @@ (match_operand:VNx2DI 1 "register_operand" "w")))] "TARGET_SVE && TARGET_NON_STREAMING" "adr\t%0.d, [%1.d, %2.d, uxtw %3]" + [(set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -4438,6 +4539,7 @@ [ w , Upl , 0 , w ; * ] abd\t%0., %1/m, %0., %3. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;abd\t%0., %1/m, %0., %3. } + [(set_attr "sve_type" "sve_int_general")] ) (define_expand "@aarch64_cond_abd" @@ -4494,6 +4596,7 @@ { operands[4] = operands[5] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_int_general")] ) ;; Predicated integer absolute difference, merging with the second input. @@ -4525,6 +4628,7 @@ { operands[4] = operands[5] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_int_general")] ) ;; Predicated integer absolute difference, merging with an independent value. @@ -4572,7 +4676,8 @@ else FAIL; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -4598,6 +4703,7 @@ [ ?&w , w , vsS ; yes ] movprfx\t%0, %1\;\t%0., %0., #%N2 [ w , w , w ; * ] \t%0., %1., %2. } + [(set_attr "sve_type" "sve_int_general")] ) ;; Unpredicated saturating unsigned addition and subtraction. @@ -4612,6 +4718,7 @@ [ ?&w , w , vsa ; yes ] movprfx\t%0, %1\;\t%0., %0., #%D2 [ w , w , w ; * ] \t%0., %1., %2. } + [(set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -4653,6 +4760,7 @@ [ w , Upl , 0 , w ; * ] mulh\t%0., %1/m, %0., %3. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;mulh\t%0., %1/m, %0., %3. } + [(set_attr "sve_type" "sve_int_mul")] ) ;; Predicated highpart multiplications with merging. @@ -4690,6 +4798,7 @@ [ w , Upl , 0 , w ; * ] \t%0., %1/m, %0., %3. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %0., %3. } + [(set_attr "sve_type" "sve_int_mul")] ) ;; Predicated highpart multiplications, merging with zero. @@ -4708,7 +4817,9 @@ [ &w , Upl , 0 , w ] movprfx\t%0., %1/z, %0.\;\t%0., %1/m, %0., %3. [ &w , Upl , w , w ] movprfx\t%0., %1/z, %2.\;\t%0., %1/m, %0., %3. } - [(set_attr "movprfx" "yes")]) + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_int_mul")] +) ;; ------------------------------------------------------------------------- ;; ---- [INT] Division @@ -4753,6 +4864,7 @@ [ w , Upl , w , 0 ; * ] r\t%Z0., %1/m, %Z0., %Z2. [ ?&w , Upl , w , w ; yes ] movprfx\t%Z0, %Z2\;\t%Z0., %1/m, %Z0., %Z3. } + [(set_attr "sve_type" "sve_int_div")] ) ;; Predicated integer division with merging. @@ -4783,6 +4895,7 @@ [ w , Upl , 0 , w ; * ] \t%0., %1/m, %0., %3. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %0., %3. } + [(set_attr "sve_type" "sve_int_div")] ) ;; Predicated integer division, merging with the second input. @@ -4800,6 +4913,7 @@ [ w , Upl , w , 0 ; * ] \t%0., %1/m, %0., %2. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;\t%0., %1/m, %0., %2. } + [(set_attr "sve_type" "sve_int_div")] ) ;; Predicated integer division, merging with an independent value. @@ -4830,7 +4944,8 @@ operands[4], operands[1])); operands[4] = operands[2] = operands[0]; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_int_div")] ) ;; ------------------------------------------------------------------------- @@ -4854,6 +4969,7 @@ [ ?w , w , vsl ; yes ] movprfx\t%0, %1\;\t%0., %0., #%C2 [ w , w , w ; * ] \t%0.d, %1.d, %2.d } + [(set_attr "sve_type" "sve_int_general")] ) ;; Merging forms are handled through SVE_INT_BINARY. @@ -4896,6 +5012,7 @@ { operands[3] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_int_general")] ) ;; Predicated BIC with merging. @@ -4927,6 +5044,7 @@ [ w , Upl , 0 , w ; * ] bic\t%0., %1/m, %0., %3. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;bic\t%0., %1/m, %0., %3. } + [(set_attr "sve_type" "sve_int_general")] ) ;; Predicated integer BIC, merging with an independent value. @@ -4955,7 +5073,8 @@ operands[4], operands[1])); operands[4] = operands[2] = operands[0]; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -5058,6 +5177,7 @@ "&& !register_operand (operands[3], mode)" [(set (match_dup 0) (ASHIFT:SVE_I (match_dup 2) (match_dup 3)))] "" + [(set_attr "sve_type" "sve_int_shift")] ) ;; Unpredicated shift operations by a constant. @@ -5069,9 +5189,9 @@ (match_operand:SVE_I 1 "register_operand") (match_operand:SVE_I 2 "aarch64_simd_lshift_imm")))] "TARGET_SVE" - {@ [ cons: =0 , 1 , 2 ] - [ w , w , vs1 ] add\t%0., %1., %1. - [ w , w , Dl ] lsl\t%0., %1., #%2 + {@ [ cons: =0 , 1 , 2 ; attrs: sve_type ] + [ w , w , vs1 ; sve_int_general ] add\t%0., %1., %1. + [ w , w , Dl ; sve_int_shift ] lsl\t%0., %1., #%2 } ) @@ -5082,6 +5202,7 @@ (match_operand:SVE_I 2 "aarch64_simd_rshift_imm")))] "TARGET_SVE" "\t%0., %1., #%2" + [(set_attr "sve_type" "sve_int_shift")] ) ;; Predicated integer shift, merging with the first input. @@ -5099,6 +5220,7 @@ [ w , Upl , 0 ; * ] \t%0., %1/m, %0., #%3 [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %0., #%3 } + [(set_attr "sve_type" "sve_int_shift")] ) ;; Predicated integer shift, merging with an independent value. @@ -5125,7 +5247,8 @@ operands[4], operands[1])); operands[4] = operands[2] = operands[0]; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_int_shift")] ) ;; Unpredicated shifts of narrow elements by 64-bit amounts. @@ -5137,6 +5260,7 @@ SVE_SHIFT_WIDE))] "TARGET_SVE" "\t%0., %1., %2.d" + [(set_attr "sve_type" "sve_int_shift")] ) ;; Merging predicated shifts of narrow elements by 64-bit amounts. @@ -5170,6 +5294,7 @@ [ w , Upl , 0 , w ; * ] \t%0., %1/m, %0., %3.d [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %0., %3.d } + [(set_attr "sve_type" "sve_int_shift")] ) ;; Predicated shifts of narrow elements by 64-bit amounts, merging with zero. @@ -5188,7 +5313,8 @@ [ &w , Upl , 0 , w ] movprfx\t%0., %1/z, %0.\;\t%0., %1/m, %0., %3.d [ &w , Upl , w , w ] movprfx\t%0., %1/z, %2.\;\t%0., %1/m, %0., %3.d } - [(set_attr "movprfx" "yes")]) + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_int_shift")]) ;; ------------------------------------------------------------------------- ;; ---- [INT] Shifts (rounding towards 0) @@ -5231,6 +5357,7 @@ [ w , Upl , 0 ; * ] asrd\t%Z0., %1/m, %Z0., #%3 [ ?&w , Upl , w ; yes ] movprfx\t%Z0, %Z2\;asrd\t%Z0., %1/m, %Z0., #%3 } + [(set_attr "sve_type" "sve_int_shift")] ) ;; Predicated shift with merging. @@ -5276,6 +5403,7 @@ { operands[4] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_int_shift")] ) ;; Predicated shift, merging with an independent value. @@ -5306,7 +5434,8 @@ operands[4], operands[1])); operands[4] = operands[2] = operands[0]; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_int_shift")] ) ;; ------------------------------------------------------------------------- @@ -5343,6 +5472,7 @@ SVE_FP_BINARY_INT))] "TARGET_SVE" "\t%0., %1., %2." + [(set_attr "sve_type" "sve_fp_mul")] ) ;; Predicated floating-point binary operations that take an integer @@ -5360,6 +5490,7 @@ [ w , Upl , 0 , w ; * ] \t%Z0., %1/m, %Z0., %Z3. [ ?&w , Upl , w , w ; yes ] movprfx\t%Z0, %Z2\;\t%Z0., %1/m, %Z0., %Z3. } + [(set_attr "sve_type" "sve_fp_mul")] ) ;; Predicated floating-point binary operations with merging, taking an @@ -5402,6 +5533,7 @@ { operands[4] = copy_rtx (operands[1]); } + [(set_attr "sve_type" "sve_fp_mul")] ) (define_insn "*cond__2_strict" @@ -5421,6 +5553,7 @@ [ w , Upl , 0 , w ; * ] \t%0., %1/m, %0., %3. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %0., %3. } + [(set_attr "sve_type" "sve_fp_mul")] ) ;; Predicated floating-point binary operations that take an integer as @@ -5460,7 +5593,8 @@ else FAIL; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_fp_mul")] ) (define_insn_and_rewrite "*cond__any_strict" @@ -5490,7 +5624,8 @@ operands[4], operands[1])); operands[4] = operands[2] = operands[0]; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_fp_mul")] ) ;; ------------------------------------------------------------------------- @@ -5528,7 +5663,9 @@ (match_operand:SVE_F_B16B16 1 "register_operand" "w") (match_operand:SVE_F_B16B16 2 "register_operand" "w")))] "TARGET_SVE && reload_completed" - "\t%0., %1., %2.") + "\t%0., %1., %2." + [(set_attr "sve_type" "sve_")] +) ;; ------------------------------------------------------------------------- ;; ---- [FP] General binary arithmetic corresponding to unspecs @@ -5565,6 +5702,7 @@ SVE_FP_BINARY))] "TARGET_SVE" "\t%0., %1., %2." + [(set_attr "sve_type" "sve_")] ) ;; Unpredicated floating-point binary operations that need to be predicated @@ -5598,6 +5736,7 @@ [ w , Upl , w , 0 ; * ] \t%0., %1/m, %0., %2. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %0., %3. } + [(set_attr "sve_type" "sve_")] ) ;; Predicated floating-point operations with merging. @@ -5641,6 +5780,7 @@ { operands[4] = copy_rtx (operands[1]); } + [(set_attr "sve_type" "sve_")] ) (define_insn "*cond__2_strict" @@ -5660,6 +5800,7 @@ [ w , Upl , 0 , w ; * ] \t%0., %1/m, %0., %3. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %0., %3. } + [(set_attr "sve_type" "sve_")] ) ;; Same for operations that take a 1-bit constant. @@ -5684,6 +5825,7 @@ { operands[4] = copy_rtx (operands[1]); } + [(set_attr "sve_type" "sve_")] ) (define_insn "*cond__2_const_strict" @@ -5703,6 +5845,7 @@ [ w , Upl , 0 ; * ] \t%0., %1/m, %0., #%3 [ ?w , Upl , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %0., #%3 } + [(set_attr "sve_type" "sve_")] ) ;; Predicated floating-point operations, merging with the second input. @@ -5727,6 +5870,7 @@ { operands[4] = copy_rtx (operands[1]); } + [(set_attr "sve_type" "sve_")] ) (define_insn "*cond__3_strict" @@ -5746,6 +5890,7 @@ [ w , Upl , w , 0 ; * ] \t%0., %1/m, %0., %2. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;\t%0., %1/m, %0., %2. } + [(set_attr "sve_type" "sve_")] ) ;; Predicated floating-point operations, merging with an independent value. @@ -5790,7 +5935,8 @@ } [(set_attr "movprfx" "yes") (set_attr "is_bf16" "") - (set_attr "supports_bf16_rev" "")] + (set_attr "supports_bf16_rev" "") + (set_attr "sve_type" "sve_")] ) (define_insn_and_rewrite "*cond__any_strict" @@ -5827,7 +5973,8 @@ } [(set_attr "movprfx" "yes") (set_attr "is_bf16" "") - (set_attr "supports_bf16_rev" "")] + (set_attr "supports_bf16_rev" "") + (set_attr "sve_type" "sve_")] ) ;; Same for operations that take a 1-bit constant. @@ -5864,7 +6011,8 @@ else FAIL; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_")] ) (define_insn_and_rewrite "*cond__any_const_strict" @@ -5893,7 +6041,8 @@ operands[4], operands[1])); operands[4] = operands[2] = operands[0]; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_")] ) ;; ------------------------------------------------------------------------- @@ -5923,6 +6072,7 @@ [ ?&w , Upl , w , vsN , i ; yes ] movprfx\t%0, %2\;fsub\t%0., %1/m, %0., #%N3 [ ?&w , Upl , w , w , Ui1 ; yes ] movprfx\t%0, %2\;fadd\t%0., %1/m, %0., %3. } + [(set_attr "sve_type" "sve_fp_arith")] ) ;; Predicated floating-point addition of a constant, merging with the @@ -5950,6 +6100,7 @@ { operands[4] = copy_rtx (operands[1]); } + [(set_attr "sve_type" "sve_fp_arith")] ) (define_insn "*cond_add_2_const_strict" @@ -5971,6 +6122,7 @@ [ ?w , Upl , w , vsA ; yes ] movprfx\t%0, %2\;fadd\t%0., %1/m, %0., #%3 [ ?w , Upl , w , vsN ; yes ] movprfx\t%0, %2\;fsub\t%0., %1/m, %0., #%N3 } + [(set_attr "sve_type" "sve_fp_arith")] ) ;; Predicated floating-point addition of a constant, merging with an @@ -6011,7 +6163,8 @@ else FAIL; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_fp_arith")] ) (define_insn_and_rewrite "*cond_add_any_const_strict" @@ -6043,7 +6196,8 @@ operands[4], operands[1])); operands[4] = operands[2] = operands[0]; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_fp_arith")] ) ;; Register merging forms are handled through SVE_COND_FP_BINARY. @@ -6069,6 +6223,7 @@ [ w , Upl , 0 , w ; * ] fcadd\t%0., %1/m, %0., %3., # [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;fcadd\t%0., %1/m, %0., %3., # } + [(set_attr "sve_type" "sve_fp_misc")] ) ;; Predicated FCADD with merging. @@ -6123,6 +6278,7 @@ { operands[4] = copy_rtx (operands[1]); } + [(set_attr "sve_type" "sve_fp_misc")] ) (define_insn "*cond__2_strict" @@ -6142,6 +6298,7 @@ [ w , Upl , 0 , w ; * ] fcadd\t%0., %1/m, %0., %3., # [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;fcadd\t%0., %1/m, %0., %3., # } + [(set_attr "sve_type" "sve_fp_misc")] ) ;; Predicated FCADD, merging with an independent value. @@ -6179,7 +6336,8 @@ else FAIL; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_fp_misc")] ) (define_insn_and_rewrite "*cond__any_strict" @@ -6209,7 +6367,8 @@ operands[4], operands[1])); operands[4] = operands[2] = operands[0]; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_fp_misc")] ) ;; ------------------------------------------------------------------------- @@ -6238,6 +6397,7 @@ [ ?&w , Upl , vsA , w , i ; yes ] movprfx\t%0, %3\;fsubr\t%0., %1/m, %0., #%2 [ ?&w , Upl , w , w , Ui1 ; yes ] movprfx\t%0, %2\;fsub\t%0., %1/m, %0., %3. } + [(set_attr "sve_type" "sve_fp_arith")] ) ;; Predicated floating-point subtraction from a constant, merging with the @@ -6263,6 +6423,7 @@ { operands[4] = copy_rtx (operands[1]); } + [(set_attr "sve_type" "sve_fp_arith")] ) (define_insn "*cond_sub_3_const_strict" @@ -6282,6 +6443,7 @@ [ w , Upl , 0 ; * ] fsubr\t%0., %1/m, %0., #%2 [ ?w , Upl , w ; yes ] movprfx\t%0, %3\;fsubr\t%0., %1/m, %0., #%2 } + [(set_attr "sve_type" "sve_fp_arith")] ) ;; Predicated floating-point subtraction from a constant, merging with an @@ -6319,7 +6481,8 @@ else FAIL; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_fp_arith")] ) (define_insn_and_rewrite "*cond_sub_const_strict" @@ -6348,7 +6511,8 @@ operands[4], operands[1])); operands[4] = operands[3] = operands[0]; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_fp_arith")] ) ;; Register merging forms are handled through SVE_COND_FP_BINARY. @@ -6397,6 +6561,7 @@ { operands[5] = copy_rtx (operands[1]); } + [(set_attr "sve_type" "sve_fp_arith")] ) (define_insn "*aarch64_pred_abd_strict" @@ -6416,6 +6581,7 @@ [ w , Upl , 0 , w ; * ] fabd\t%0., %1/m, %0., %3. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;fabd\t%0., %1/m, %0., %3. } + [(set_attr "sve_type" "sve_fp_arith")] ) (define_expand "@aarch64_cond_abd" @@ -6469,6 +6635,7 @@ operands[4] = copy_rtx (operands[1]); operands[5] = copy_rtx (operands[1]); } + [(set_attr "sve_type" "sve_fp_arith")] ) (define_insn "*aarch64_cond_abd_2_strict" @@ -6492,6 +6659,7 @@ [ w , Upl , 0 , w ; * ] fabd\t%0., %1/m, %0., %3. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;fabd\t%0., %1/m, %0., %3. } + [(set_attr "sve_type" "sve_fp_arith")] ) ;; Predicated floating-point absolute difference, merging with the second @@ -6523,6 +6691,7 @@ operands[4] = copy_rtx (operands[1]); operands[5] = copy_rtx (operands[1]); } + [(set_attr "sve_type" "sve_fp_arith")] ) (define_insn "*aarch64_cond_abd_3_strict" @@ -6546,6 +6715,7 @@ [ w , Upl , w , 0 ; * ] fabd\t%0., %1/m, %0., %2. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;fabd\t%0., %1/m, %0., %2. } + [(set_attr "sve_type" "sve_fp_arith")] ) ;; Predicated floating-point absolute difference, merging with an @@ -6595,7 +6765,8 @@ else FAIL; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_fp_arith")] ) (define_insn_and_rewrite "*aarch64_cond_abd_any_strict" @@ -6632,7 +6803,8 @@ operands[4], operands[1])); operands[4] = operands[3] = operands[0]; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_fp_arith")] ) ;; ------------------------------------------------------------------------- @@ -6660,6 +6832,7 @@ [ ?&w , Upl , w , vsM , i ; yes ] movprfx\t%0, %2\;fmul\t%0., %1/m, %0., #%3 [ ?&w , Upl , w , w , Ui1 ; yes ] movprfx\t%0, %2\;fmul\t%0., %1/m, %0., %3. } + [(set_attr "sve_type" "sve_fp_mul")] ) ;; Merging forms are handled through SVE_COND_FP_BINARY and @@ -6676,6 +6849,7 @@ (match_operand:SVE_FULL_F_B16B16 1 "register_operand" "w")))] "TARGET_SVE" "fmul\t%0., %1., %2.[%3]" + [(set_attr "sve_type" "sve_fp_mul")] ) ;; ------------------------------------------------------------------------- @@ -6739,6 +6913,7 @@ LOGICALF))] "TARGET_SVE" "\t%0.d, %1.d, %2.d" + [(set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -6893,6 +7068,7 @@ [ ?&w , Upl , w , vsB ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %0., #%3 [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %0., %3. } + [(set_attr "sve_type" "sve_fp_arith")] ) ;; Merging forms are handled through SVE_COND_FP_BINARY and @@ -6923,6 +7099,7 @@ [ ?Upa , 0Upa, 0Upa; yes ] ^ [ Upa , Upa , Upa ; no ] ^ } + [(set_attr "sve_type" "sve_pred_logical")] ) ;; Unpredicated predicate EOR and ORR. @@ -6953,6 +7130,7 @@ [ ?Upa , 0Upa, 0Upa, 0Upa; yes ] ^ [ Upa , Upa , Upa , Upa ; no ] ^ } + [(set_attr "sve_type" "sve_pred_logical")] ) ;; Perform a logical operation on operands 2 and 3, using operand 1 as @@ -6979,6 +7157,7 @@ [ ?Upa , 0Upa, 0Upa, 0Upa; yes ] ^ [ Upa , Upa , Upa , Upa ; no ] ^ } + [(set_attr "sve_type" "sve_pred_logical")] ) ;; Same with just the flags result. @@ -7001,6 +7180,7 @@ [ ?Upa , 0Upa, 0Upa, 0Upa; yes ] ^ [ Upa , Upa , Upa , Upa ; no ] ^ } + [(set_attr "sve_type" "sve_pred_logical")] ) ;; ------------------------------------------------------------------------- @@ -7025,6 +7205,7 @@ [ ?Upa , 0Upa, 0Upa, 0Upa; yes ] ^ [ Upa , Upa , Upa , Upa ; no ] ^ } + [(set_attr "sve_type" "sve_pred_logical")] ) ;; Same, but set the flags as a side-effect. @@ -7052,6 +7233,7 @@ [ ?Upa , 0Upa, 0Upa, 0Upa; yes ] ^ [ Upa , Upa , Upa , Upa ; no ] ^ } + [(set_attr "sve_type" "sve_pred_logical")] ) ;; Same with just the flags result. @@ -7075,6 +7257,7 @@ [ ?Upa , 0Upa, 0Upa, 0Upa; yes ] ^ [ Upa , Upa , Upa , Upa ; no ] ^ } + [(set_attr "sve_type" "sve_pred_logical")] ) ;; ------------------------------------------------------------------------- @@ -7099,6 +7282,7 @@ [ ?Upa , 0Upa, 0Upa, 0Upa; yes ] ^ [ Upa , Upa , Upa , Upa ; no ] ^ } + [(set_attr "sve_type" "sve_pred_logical")] ) ;; Same, but set the flags as a side-effect. @@ -7127,6 +7311,7 @@ [ ?Upa , 0Upa, 0Upa, 0Upa; yes ] ^ [ Upa , Upa , Upa , Upa ; no ] ^ } + [(set_attr "sve_type" "sve_pred_logical")] ) ;; Same with just the flags result. @@ -7151,6 +7336,7 @@ [ ?Upa , 0Upa, 0Upa, 0Upa; yes ] ^ [ Upa , Upa , Upa , Upa ; no ] ^ } + [(set_attr "sve_type" "sve_pred_logical")] ) ;; ========================================================================= @@ -7201,6 +7387,7 @@ [ w , Upl , w , w , 0 ; * ] mla\t%0., %1/m, %2., %3. [ ?&w , Upl , w , w , w ; yes ] movprfx\t%0, %4\;mla\t%0., %1/m, %2., %3. } + [(set_attr "sve_type" "sve_int_mul")] ) ;; Predicated integer addition of product with merging. @@ -7243,6 +7430,7 @@ [ w , Upl , 0 , w , w ; * ] mad\t%0., %1/m, %3., %4. [ ?&w , Upl , w , w , w ; yes ] movprfx\t%0, %2\;mad\t%0., %1/m, %3., %4. } + [(set_attr "sve_type" "sve_int_mul")] ) ;; Predicated integer addition of product, merging with the third input. @@ -7262,6 +7450,7 @@ [ w , Upl , w , w , 0 ; * ] mla\t%0., %1/m, %2., %3. [ ?&w , Upl , w , w , w ; yes ] movprfx\t%0, %4\;mla\t%0., %1/m, %2., %3. } + [(set_attr "sve_type" "sve_int_mul")] ) ;; Predicated integer addition of product, merging with an independent value. @@ -7296,7 +7485,8 @@ operands[5], operands[1])); operands[5] = operands[4] = operands[0]; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_int_mul")] ) ;; ------------------------------------------------------------------------- @@ -7343,6 +7533,7 @@ [ w , Upl , w , w , 0 ; * ] mls\t%0., %1/m, %2., %3. [ ?&w , Upl , w , w , w ; yes ] movprfx\t%0, %4\;mls\t%0., %1/m, %2., %3. } + [(set_attr "sve_type" "sve_int_mul")] ) ;; Predicated integer subtraction of product with merging. @@ -7385,6 +7576,7 @@ [ w , Upl , 0 , w , w ; * ] msb\t%0., %1/m, %3., %4. [ ?&w , Upl , w , w , w ; yes ] movprfx\t%0, %2\;msb\t%0., %1/m, %3., %4. } + [(set_attr "sve_type" "sve_int_mul")] ) ;; Predicated integer subtraction of product, merging with the third input. @@ -7404,6 +7596,7 @@ [ w , Upl , w , w , 0 ; * ] mls\t%0., %1/m, %2., %3. [ ?&w , Upl , w , w , w ; yes ] movprfx\t%0, %4\;mls\t%0., %1/m, %2., %3. } + [(set_attr "sve_type" "sve_int_mul")] ) ;; Predicated integer subtraction of product, merging with an @@ -7439,7 +7632,8 @@ operands[5], operands[1])); operands[5] = operands[4] = operands[0]; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_int_mul")] ) ;; ------------------------------------------------------------------------- @@ -7466,6 +7660,7 @@ [ w , w , w , 0 ; * ] dot\t%0., %1., %2. [ ?&w , w , w , w ; yes ] movprfx\t%0, %3\;dot\t%0., %1., %2. } + [(set_attr "sve_type" "sve_int_dot")] ) ;; Four-element integer dot-product by selected lanes with accumulation. @@ -7489,6 +7684,7 @@ [ w , w , , 0 ; * ] dot\t%0., %1., %2.[%3] [ ?&w , w , , w ; yes ] movprfx\t%0, %4\;dot\t%0., %1., %2.[%3] } + [(set_attr "sve_type" "sve_int_dot")] ) (define_insn "@dot_prod" @@ -7504,6 +7700,7 @@ [ w , w , w , 0 ; * ] dot\t%0.s, %1.b, %2.b [ ?&w , w , w , w ; yes ] movprfx\t%0, %3\;dot\t%0.s, %1.b, %2.b } + [(set_attr "sve_type" "sve_int_dot")] ) (define_insn "@aarch64_dot_prod_lane" @@ -7522,6 +7719,7 @@ [ w , w , y , 0 ; * ] dot\t%0.s, %1.b, %2.b[%3] [ ?&w , w , y , w ; yes ] movprfx\t%0, %4\;dot\t%0.s, %1.b, %2.b[%3] } + [(set_attr "sve_type" "sve_int_dot")] ) ;; ------------------------------------------------------------------------- @@ -7577,6 +7775,7 @@ [ w , 0 , w , w ; * ] mmla\t%0.s, %2.b, %3.b [ ?&w , w , w , w ; yes ] movprfx\t%0, %1\;mmla\t%0.s, %2.b, %3.b } + [(set_attr "sve_type" "sve_int_dot")] ) ;; ------------------------------------------------------------------------- @@ -7626,7 +7825,8 @@ [ ?&w , Upl , w , w , w ; yes , * ] movprfx\t%0, %4\;\t%0., %1/m, %2., %3. } [(set_attr "is_bf16" "") - (set_attr "supports_bf16_rev" "false")] + (set_attr "supports_bf16_rev" "false") + (set_attr "sve_type" "sve_fp_mul")] ) ;; Predicated floating-point ternary operations with merging. @@ -7677,6 +7877,7 @@ { operands[5] = copy_rtx (operands[1]); } + [(set_attr "sve_type" "sve_fp_mul")] ) (define_insn "*cond__2_strict" @@ -7697,6 +7898,7 @@ [ w , Upl , 0 , w , w ; * ] \t%0., %1/m, %3., %4. [ ?&w , Upl , w , w , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %3., %4. } + [(set_attr "sve_type" "sve_fp_mul")] ) ;; Predicated floating-point ternary operations, merging with the @@ -7723,6 +7925,7 @@ { operands[5] = copy_rtx (operands[1]); } + [(set_attr "sve_type" "sve_fp_mul")] ) (define_insn "*cond__4_strict" @@ -7743,6 +7946,7 @@ [ w , Upl , w , w , 0 ; * ] \t%0., %1/m, %2., %3. [ ?&w , Upl , w , w , w ; yes ] movprfx\t%0, %4\;\t%0., %1/m, %2., %3. } + [(set_attr "sve_type" "sve_fp_mul")] ) ;; Predicated floating-point ternary operations, merging with an @@ -7790,7 +7994,8 @@ } [(set_attr "movprfx" "yes") (set_attr "is_bf16" "") - (set_attr "supports_bf16_rev" "false")] + (set_attr "supports_bf16_rev" "false") + (set_attr "sve_type" "sve_fp_mul")] ) (define_insn_and_rewrite "*cond__any_strict" @@ -7829,7 +8034,8 @@ } [(set_attr "movprfx" "yes") (set_attr "is_bf16" "") - (set_attr "supports_bf16_rev" "false")] + (set_attr "supports_bf16_rev" "false") + (set_attr "sve_type" "sve_fp_mul")] ) ;; Unpredicated FMLA and FMLS by selected lanes. It doesn't seem worth using @@ -7849,6 +8055,7 @@ [ w , w , , 0 ; * ] \t%0., %1., %2.[%3] [ ?&w , w , , w ; yes ] movprfx\t%0, %4\;\t%0., %1., %2.[%3] } + [(set_attr "sve_type" "sve_fp_mul")] ) ;; ------------------------------------------------------------------------- @@ -7873,6 +8080,7 @@ [ w , Upl , w , w , 0 ; * ] fcmla\t%0., %1/m, %2., %3., # [ ?&w , Upl , w , w , w ; yes ] movprfx\t%0, %4\;fcmla\t%0., %1/m, %2., %3., # } + [(set_attr "sve_type" "sve_fp_mul")] ) ;; unpredicated optab pattern for auto-vectorizer @@ -7971,6 +8179,7 @@ { operands[5] = copy_rtx (operands[1]); } + [(set_attr "sve_type" "sve_fp_mul")] ) (define_insn "*cond__4_strict" @@ -7991,6 +8200,7 @@ [ w , Upl , w , w , 0 ; * ] fcmla\t%0., %1/m, %2., %3., # [ ?&w , Upl , w , w , w ; yes ] movprfx\t%0, %4\;fcmla\t%0., %1/m, %2., %3., # } + [(set_attr "sve_type" "sve_fp_mul")] ) ;; Predicated FCMLA, merging with an independent value. @@ -8029,7 +8239,8 @@ else FAIL; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_fp_mul")] ) (define_insn_and_rewrite "*cond__any_strict" @@ -8060,7 +8271,8 @@ operands[5], operands[1])); operands[5] = operands[4] = operands[0]; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_fp_mul")] ) ;; Unpredicated FCMLA with indexing. @@ -8079,6 +8291,7 @@ [ w , w , , 0 ; * ] fcmla\t%0., %1., %2.[%3], # [ ?&w , w , , w ; yes ] movprfx\t%0, %4\;fcmla\t%0., %1., %2.[%3], # } + [(set_attr "sve_type" "sve_fp_mul")] ) ;; ------------------------------------------------------------------------- @@ -8100,6 +8313,7 @@ [ w , 0 , w ; * ] ftmad\t%0., %0., %2., #%3 [ ?&w , w , w ; yes ] movprfx\t%0, %1\;ftmad\t%0., %0., %2., #%3 } + [(set_attr "sve_type" "sve_fp_mul")] ) ;; ------------------------------------------------------------------------- @@ -8126,6 +8340,7 @@ [ w , 0 , w , w ; * ] \t%0.s, %2.h, %3.h [ ?&w , w , w , w ; yes ] movprfx\t%0, %1\;\t%0.s, %2.h, %3.h } + [(set_attr "sve_type" "sve_fp_mul")] ) ;; The immediate range is enforced before generating the instruction. @@ -8142,6 +8357,7 @@ [ w , 0 , w , y ; * ] \t%0.s, %2.h, %3.h[%4] [ ?&w , w , w , y ; yes ] movprfx\t%0, %1\;\t%0.s, %2.h, %3.h[%4] } + [(set_attr "sve_type" "sve_fp_mul")] ) ;; ------------------------------------------------------------------------- @@ -8164,6 +8380,7 @@ [ w , 0 , w , w ; * ] \t%0., %2., %3. [ ?&w , w , w , w ; yes ] movprfx\t%0, %1\;\t%0., %2., %3. } + [(set_attr "sve_type" "sve_fp_mul")] ) ;; ========================================================================= @@ -8356,6 +8573,7 @@ [ ?Upl , 0 , w , w ; yes ] ^ [ Upa , Upl, w , w ; no ] ^ } + [(set_attr "sve_type" "sve_int_cmp_set")] ) ;; Likewise, but yield a VNx16BI result regardless of the element width. @@ -8462,6 +8680,7 @@ operands[6] = copy_rtx (operands[4]); operands[7] = operands[5]; } + [(set_attr "sve_type" "sve_int_cmp_set")] ) (define_insn_and_rewrite "*cmp_acle_cc" @@ -8539,6 +8758,7 @@ operands[6] = copy_rtx (operands[4]); operands[7] = operands[5]; } + [(set_attr "sve_type" "sve_int_cmp_set")] ) ;; Predicated integer comparisons, formed by combining a PTRUE-predicated @@ -8570,6 +8790,8 @@ (match_dup 3))] UNSPEC_PRED_Z)) (clobber (reg:CC_NZC CC_REGNUM))])] + {} + [(set_attr "sve_type" "sve_int_cmp_set")] ) (define_insn_and_split "*cmp_acle_and" @@ -8628,6 +8850,7 @@ [ ?Upl , 0 , , w, w; yes ] ^ [ Upa , Upl, , w, w; no ] ^ } + [(set_attr "sve_type" "sve_int_cmp_set")] ) (define_expand "@aarch64_pred_cmp_wide" @@ -8713,6 +8936,7 @@ operands[6] = copy_rtx (operands[4]); operands[7] = operands[5]; } + [(set_attr "sve_type" "sve_int_cmp_set")] ) (define_insn_and_rewrite "*aarch64_pred_cmp_wide_cc" @@ -8755,6 +8979,7 @@ operands[6] = copy_rtx (operands[4]); operands[7] = operands[5]; } + [(set_attr "sve_type" "sve_int_cmp_set")] ) ;; Predicated integer wide comparisons in which only the flags result @@ -8787,6 +9012,7 @@ operands[6] = copy_rtx (operands[4]); operands[7] = operands[5]; } + [(set_attr "sve_type" "sve_int_cmp_set")] ) ;; ------------------------------------------------------------------------- @@ -8822,6 +9048,7 @@ (clobber (reg:CC_NZC CC_REGNUM))] "TARGET_SVE" "while\t%0., %1, %2" + [(set_attr "sve_type" "sve_pred_cnt_ctrl")] ) ;; Likewise, but yield a VNx16BI result regardless of the element width. @@ -8905,6 +9132,7 @@ operands[3] = CONSTM1_RTX (VNx16BImode); operands[4] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_pred_cnt_ctrl")] ) (define_insn_and_rewrite "*while__acle_cc" @@ -8962,6 +9190,7 @@ operands[3] = CONSTM1_RTX (VNx16BImode); operands[4] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_pred_cnt_ctrl")] ) ;; ------------------------------------------------------------------------- @@ -9007,6 +9236,7 @@ [ Upa , Upl , w , Dz ] fcm\t%0., %1/z, %3., #0.0 [ Upa , Upl , w , w ] fcm\t%0., %1/z, %3., %4. } + [(set_attr "sve_type" "sve_fp_cmp")] ) (define_expand "@aarch64_pred_fcm_acle" @@ -9057,6 +9287,7 @@ UNSPEC_COND_FCMUO))] "TARGET_SVE" "fcmuo\t%0., %1/z, %3., %4." + [(set_attr "sve_type" "sve_fp_cmp")] ) (define_expand "@aarch64_pred_fcmuo_acle" @@ -9121,6 +9352,8 @@ (match_dup 2) (match_dup 3)] SVE_COND_FP_CMP_I0))] + {} + [(set_attr "sve_type" "sve_fp_cmp")] ) ;; Same for unordered comparisons. @@ -9144,6 +9377,8 @@ (match_dup 2) (match_dup 3)] UNSPEC_COND_FCMUO))] + {} + [(set_attr "sve_type" "sve_fp_cmp")] ) ;; Similar to *fcm_and_combine, but for BIC rather than AND. @@ -9182,6 +9417,7 @@ if (can_create_pseudo_p ()) operands[5] = gen_reg_rtx (mode); } + [(set_attr "sve_type" "sve_fp_cmp")] ) ;; Make sure that we expand to a nor when the operand 4 of @@ -9223,6 +9459,7 @@ if (can_create_pseudo_p ()) operands[5] = gen_reg_rtx (mode); } + [(set_attr "sve_type" "sve_fp_cmp")] ) ;; Same for unordered comparisons. @@ -9259,6 +9496,7 @@ if (can_create_pseudo_p ()) operands[5] = gen_reg_rtx (mode); } + [(set_attr "sve_type" "sve_fp_cmp")] ) (define_insn_and_split "*fcmuo_nor_combine" @@ -9298,6 +9536,7 @@ if (can_create_pseudo_p ()) operands[5] = gen_reg_rtx (mode); } + [(set_attr "sve_type" "sve_fp_cmp")] ) ;; ------------------------------------------------------------------------- @@ -9361,6 +9600,7 @@ operands[5] = copy_rtx (operands[1]); operands[6] = copy_rtx (operands[1]); } + [(set_attr "sve_type" "sve_fp_cmp")] ) (define_insn "*aarch64_pred_fac_strict" @@ -9381,6 +9621,7 @@ SVE_COND_FP_ABS_CMP))] "TARGET_SVE" "fac\t%0., %1/z, %2., %3." + [(set_attr "sve_type" "sve_fp_cmp")] ) (define_insn "*aarch64_pred_fac_strict_acle" @@ -9425,6 +9666,7 @@ (match_operand:PRED_ALL 2 "register_operand" "Upa"))))] "TARGET_SVE" "sel\t%0.b, %3, %1.b, %2.b" + [(set_attr "sve_type" "sve_pred_logical")] ) ;; ------------------------------------------------------------------------- @@ -9473,6 +9715,7 @@ UNSPEC_PTEST))] "TARGET_SVE" "ptest\t%0, %3.b" + [(set_attr "sve_type" "sve_pred_logical")] ) ;; ========================================================================= @@ -9497,10 +9740,11 @@ (match_operand:SVE_ALL 3 "register_operand")] CLAST))] "TARGET_SVE" - {@ [ cons: =0 , 1 , 2 , 3 ] - [ ?r , 0 , Upl , w ] clast\t%0, %2, %0, %3. - [ w , 0 , Upl , w ] clast\t%0, %2, %0, %3. + {@ [ cons: =0 , 1 , 2 , 3 ] + [ ?r , 0 , Upl , w ] clast\t%0, %2, %0, %3. + [ w , 0 , Upl , w ] clast\t%0, %2, %0, %3. } + [(set_attr "sve_type" "sve_int_extract")] ) (define_insn "@aarch64_fold_extract_vector__" @@ -9515,6 +9759,7 @@ [ w , 0 , Upl , w ] clast\t%0., %2, %0., %3. [ ?&w , w , Upl , w ] movprfx\t%0, %1\;clast\t%0., %2, %0., %3. } + [(set_attr "sve_type" "sve_int_extract")] ) ;; ------------------------------------------------------------------------- @@ -9555,6 +9800,7 @@ SVE_INT_ADDV))] "TARGET_SVE && >= " "addv\t%d0, %1, %2." + [(set_attr "sve_type" "sve_int_reduc")] ) ;; Unpredicated integer reductions. @@ -9577,6 +9823,7 @@ SVE_INT_REDUCTION))] "TARGET_SVE" "\t%0, %1, %2." + [(set_attr "sve_type" "sve_int_reduc")] ) ;; ------------------------------------------------------------------------- @@ -9621,6 +9868,7 @@ SVE_FP_REDUCTION))] "TARGET_SVE" "\t%0, %1, %2." + [(set_attr "sve_type" "sve_fp_reduc")] ) ;; ------------------------------------------------------------------------- @@ -9652,6 +9900,7 @@ UNSPEC_FADDA))] "TARGET_SVE && TARGET_NON_STREAMING" "fadda\t%0, %3, %0, %2." + [(set_attr "sve_type" "sve_fp_assoc_add")] ) ;; ========================================================================= @@ -9687,6 +9936,7 @@ SVE_TBL))] "TARGET_SVE" "\t%0., {%1.}, %2." + [(set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -9707,6 +9957,7 @@ UNSPEC_SVE_COMPACT))] "TARGET_SVE && TARGET_NON_STREAMING" "compact\t%0., %1, %2." + [(set_attr "sve_type" "sve_int_extract")] ) ;; Duplicate one element of a vector. @@ -9719,6 +9970,7 @@ "TARGET_SVE && IN_RANGE (INTVAL (operands[2]) * / 8, 0, 63)" "dup\t%0., %1.[%2]" + [(set_attr "sve_type" "sve_int_general")] ) ;; Use DUP.Q to duplicate a 128-bit segment of a register. @@ -9755,6 +10007,7 @@ operands[2] = gen_int_mode (byte / 16, DImode); return "dup\t%0.q, %1.q[%2]"; } + [(set_attr "sve_type" "sve_int_general")] ) ;; Reverse the order of elements within a full vector. @@ -9764,7 +10017,9 @@ [(match_operand:SVE_ALL 1 "register_operand" "w")] UNSPEC_REV))] "TARGET_SVE" - "rev\t%0., %1.") + "rev\t%0., %1." + [(set_attr "sve_type" "sve_int_general")] +) ;; ------------------------------------------------------------------------- ;; ---- [INT,FP] Special-purpose binary permutes @@ -9797,6 +10052,7 @@ [ w , Upl , 0 , w ; * ] splice\t%0., %1, %0., %3. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;splice\t%0., %1, %0., %3. } + [(set_attr "sve_type" "sve_int_extract")] ) ;; Permutes that take half the elements from one vector and half the @@ -9809,6 +10065,7 @@ SVE_PERMUTE))] "TARGET_SVE" "\t%0., %1., %2." + [(set_attr "sve_type" "sve_int_general")] ) ;; Apply PERMUTE to 128-bit sequences. The behavior of these patterns @@ -9821,6 +10078,7 @@ PERMUTEQ))] "TARGET_SVE_F64MM" "\t%0.q, %1.q, %2.q" + [(set_attr "sve_type" "sve_int_general")] ) ;; Concatenate two vectors and extract a subvector. Note that the @@ -9840,7 +10098,8 @@ ? "ext\\t%0.b, %0.b, %2.b, #%3" : "movprfx\t%0, %1\;ext\\t%0.b, %0.b, %2.b, #%3"); } - [(set_attr "movprfx" "*,yes")] + [(set_attr "movprfx" "*,yes") + (set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -9856,6 +10115,7 @@ UNSPEC_REV))] "TARGET_SVE" "rev\t%0., %1." + [(set_attr "sve_type" "sve_pred_misc")] ) (define_expand "@aarch64_sve_rev_acle" @@ -9878,6 +10138,7 @@ UNSPEC_REV_PRED))] "TARGET_SVE" "rev\t%0., %1." + [(set_attr "sve_type" "sve_pred_misc")] ) ;; ------------------------------------------------------------------------- @@ -9901,6 +10162,7 @@ PERMUTE))] "TARGET_SVE" "\t%0., %1., %2." + [(set_attr "sve_type" "sve_pred_misc")] ) ;; Special-purpose permutes used by the ACLE intrinsics and predicate @@ -9936,6 +10198,7 @@ UNSPEC_PERMUTE_PRED))] "TARGET_SVE" "\t%0., %1., %2." + [(set_attr "sve_type" "sve_pred_misc")] ) ;; ========================================================================= @@ -9959,6 +10222,7 @@ UNSPEC_PACK))] "TARGET_SVE" "uzp1\t%0., %1., %2." + [(set_attr "sve_type" "sve_int_general")] ) ;; Integer partial pack packing two partial SVE types into a single full SVE @@ -9972,6 +10236,7 @@ (match_operand: 2 "register_operand" "w")))] "TARGET_SVE" "uzp1\t%0., %1., %2." + [(set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -10008,6 +10273,7 @@ UNPACK))] "TARGET_SVE" "unpk\t%0., %1." + [(set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -10065,6 +10331,7 @@ [ w , Upl , 0 ; * ] fcvtz\t%0., %1/m, %2. [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;fcvtz\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; As above, for pairs used by the auto-vectorizer only. @@ -10081,6 +10348,7 @@ [ w , Upl , 0 ; * ] fcvtz\t%0., %1/m, %2. [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;fcvtz\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; Predicated narrowing float-to-integer conversion. The VNx2DF->VNx4SI @@ -10099,6 +10367,7 @@ [ w , Upl , 0 ; * ] fcvtz\t%0., %1/m, %2. [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;fcvtz\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; Predicated float-to-integer conversion with merging, either to the same @@ -10143,6 +10412,7 @@ { operands[4] = copy_rtx (operands[1]); } + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; As above, for pairs that are used by the auto-vectorizer only. @@ -10187,6 +10457,7 @@ [ &w , Upl , w , Dz ; yes ] movprfx\t%0., %1/z, %2.\;fcvtz\t%0., %1/m, %2. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;fcvtz\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; Predicated narrowing float-to-integer conversion with merging. @@ -10221,6 +10492,7 @@ [ &w , Upl , w , Dz ; yes ] movprfx\t%0., %1/z, %2.\;fcvtz\t%0., %1/m, %2. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;fcvtz\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_fp_cvt")] ) (define_insn_and_rewrite "*cond__trunc_relaxed" @@ -10320,6 +10592,7 @@ [ w , Upl , 0 ; * ] cvtf\t%0., %1/m, %2. [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;cvtf\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_int_cvt")] ) ;; As above, for pairs that are used by the auto-vectorizer only. @@ -10336,6 +10609,7 @@ [ w , Upl , 0 ; * ] cvtf\t%0., %1/m, %2. [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;cvtf\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_int_cvt")] ) ;; Predicated widening integer-to-float conversion. @@ -10351,6 +10625,7 @@ [ w , Upl , 0 ; * ] cvtf\t%0., %1/m, %2. [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;cvtf\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_int_cvt")] ) ;; Predicated integer-to-float conversion with merging, either to the same @@ -10395,6 +10670,7 @@ { operands[4] = copy_rtx (operands[1]); } + [(set_attr "sve_type" "sve_int_cvt")] ) ;; As above, for pairs that are used by the auto-vectorizer only. @@ -10439,6 +10715,7 @@ [ &w , Upl , w , Dz ; yes ] movprfx\t%0., %1/z, %2.\;cvtf\t%0., %1/m, %2. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;cvtf\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_int_cvt")] ) ;; Predicated widening integer-to-float conversion with merging. @@ -10473,6 +10750,7 @@ [ ?&w , Upl , w , Dz ; yes ] movprfx\t%0., %1/z, %2.\;cvtf\t%0., %1/m, %2. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;cvtf\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_int_cvt")] ) ;; ------------------------------------------------------------------------- @@ -10580,6 +10858,7 @@ [ w , Upl , 0 ; * ] fcvt\t%0., %1/m, %2. [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;fcvt\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; As above, for pairs that are used by the auto-vectorizer only. @@ -10595,6 +10874,7 @@ [ w , Upl , 0 ; * ] fcvt\t%0., %1/m, %2. [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;fcvt\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; Predicated float-to-float truncation with merging. @@ -10629,6 +10909,7 @@ [ ?&w , Upl , w , Dz ; yes ] movprfx\t%0., %1/z, %2.\;fcvt\t%0., %1/m, %2. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;fcvt\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; As above, for pairs that are used by the auto-vectorizer only. @@ -10676,6 +10957,7 @@ [ w , Upl , 0 ; * ] bfcvt\t%0.h, %1/m, %2.s [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;bfcvt\t%0.h, %1/m, %2.s } + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; Predicated BFCVT with merging. @@ -10710,6 +10992,7 @@ [ ?&w , Upl , w , Dz ; yes ] movprfx\t%0.s, %1/z, %2.s\;bfcvt\t%0.h, %1/m, %2.s [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;bfcvt\t%0.h, %1/m, %2.s } + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; Predicated BFCVTNT. This doesn't give a natural aarch64_pred_*/cond_* @@ -10727,6 +11010,7 @@ UNSPEC_COND_FCVTNT))] "TARGET_SVE_BF16" "bfcvtnt\t%0.h, %2/m, %3.s" + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; ------------------------------------------------------------------------- @@ -10797,6 +11081,7 @@ [ w , Upl , 0 ; * ] fcvt\t%0., %1/m, %2. [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;fcvt\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; As above, for pairs that are used by the auto-vectorizer only. @@ -10812,6 +11097,7 @@ [ w , Upl , 0 ; * ] fcvt\t%0., %1/m, %2. [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;fcvt\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; Predicated float-to-float extension with merging. @@ -10846,6 +11132,7 @@ [ ?&w , Upl , w , Dz ; yes ] movprfx\t%0., %1/z, %2.\;fcvt\t%0., %1/m, %2. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;fcvt\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; As above, for pairs that are used by the auto-vectorizer only. @@ -10889,6 +11176,7 @@ UNSPEC_PACK))] "TARGET_SVE" "uzp1\t%0., %1., %2." + [(set_attr "sve_type" "sve_pred_misc")] ) ;; ------------------------------------------------------------------------- @@ -10922,6 +11210,7 @@ UNPACK_UNSIGNED))] "TARGET_SVE" "punpk\t%0.h, %1.b" + [(set_attr "sve_type" "sve_pred_misc")] ) (define_expand "@aarch64_sve_punpk_acle" @@ -10985,6 +11274,7 @@ [ ?Upa , 0Upa, 0Upa, 0 ; yes ] ^ [ Upa , Upa , Upa , 0 ; no ] ^ } + [(set_attr "sve_type" "sve_pred_cnt_ctrl")] ) ;; Same, but also producing a flags result. @@ -11012,6 +11302,7 @@ [ ?Upa , 0Upa, 0Upa; yes ] ^ [ Upa , Upa , Upa ; no ] ^ } + [(set_attr "sve_type" "sve_pred_cnt_ctrl")] ) ;; Same, but with only the flags result being interesting. @@ -11034,6 +11325,7 @@ [ ?Upa , 0Upa, 0Upa; yes ] ^ [ Upa , Upa , Upa ; no ] ^ } + [(set_attr "sve_type" "sve_pred_cnt_ctrl")] ) ;; ------------------------------------------------------------------------- @@ -11062,6 +11354,7 @@ [ ?Upa , 0Upa, 0Upa, 0; yes ] ^ [ Upa , Upa , Upa , ; no ] ^ } + [(set_attr "sve_type" "sve_pred_cnt_ctrl")] ) ;; BRKN, producing both a predicate and a flags result. Unlike other @@ -11092,6 +11385,7 @@ operands[4] = CONST0_RTX (VNx16BImode); operands[5] = CONST0_RTX (VNx16BImode); } + [(set_attr "sve_type" "sve_pred_cnt_ctrl")] ) ;; Same, but with only the flags result being interesting. @@ -11116,6 +11410,7 @@ operands[4] = CONST0_RTX (VNx16BImode); operands[5] = CONST0_RTX (VNx16BImode); } + [(set_attr "sve_type" "sve_pred_cnt_ctrl")] ) ;; BRKPA and BRKPB, producing both a predicate and a flags result. @@ -11143,6 +11438,7 @@ [ ?Upa , 0Upa, 0Upa, 0Upa, ; yes ] ^ [ Upa , Upa , Upa , Upa , ; no ] ^ } + [(set_attr "sve_type" "sve_pred_cnt_ctrl")] ) ;; Same, but with only the flags result being interesting. @@ -11165,6 +11461,7 @@ [ ?Upa , 0Upa, 0Upa, 0Upa; yes ] ^ [ Upa , Upa , Upa , Upa ; no ] ^ } + [(set_attr "sve_type" "sve_pred_cnt_ctrl")] ) ;; ------------------------------------------------------------------------- @@ -11220,6 +11517,7 @@ (clobber (reg:CC_NZC CC_REGNUM))] "TARGET_SVE" "\t%0., %1, %0." + [(set_attr "sve_type" "sve_pred_cnt_ctrl")] ) ;; Same, but also producing a flags result. @@ -11250,6 +11548,7 @@ operands[4] = operands[2]; operands[5] = operands[3]; } + [(set_attr "sve_type" "sve_pred_cnt_ctrl")] ) (define_insn_and_rewrite "*aarch64_sve__cc" @@ -11307,6 +11606,7 @@ operands[4] = operands[2]; operands[5] = operands[3]; } + [(set_attr "sve_type" "sve_pred_cnt_ctrl")] ) ;; ========================================================================= @@ -11339,6 +11639,7 @@ { return aarch64_output_sve_cnt_pat_immediate ("cnt", "%x0", operands + 1); } + [(set_attr "sve_type" "sve_pred_cnt_scalar")] ) ;; ------------------------------------------------------------------------- @@ -11365,6 +11666,7 @@ return aarch64_output_sve_cnt_pat_immediate ("", "%x0", operands + 2); } + [(set_attr "sve_type" "sve_pred_cnt_scalar")] ) ;; Increment an SImode register by the number of elements in an svpattern @@ -11381,6 +11683,7 @@ { return aarch64_output_sve_cnt_pat_immediate ("inc", "%x0", operands + 2); } + [(set_attr "sve_type" "sve_pred_cnt_scalar")] ) ;; Increment an SImode register by the number of elements in an svpattern @@ -11402,6 +11705,7 @@ return aarch64_output_sve_cnt_pat_immediate ("", registers, operands + 2); } + [(set_attr "sve_type" "sve_pred_cnt_scalar")] ) ;; ------------------------------------------------------------------------- @@ -11432,7 +11736,8 @@ return aarch64_output_sve_cnt_pat_immediate ("", "%0.", operands + 2); } - [(set_attr "movprfx" "*,yes")] + [(set_attr "movprfx" "*,yes") + (set_attr "sve_type" "sve_pred_vec")] ) ;; Increment a vector of SIs by the number of elements in an svpattern. @@ -11453,7 +11758,8 @@ return aarch64_output_sve_cnt_pat_immediate ("", "%0.", operands + 2); } - [(set_attr "movprfx" "*,yes")] + [(set_attr "movprfx" "*,yes") + (set_attr "sve_type" "sve_pred_vec")] ) ;; Increment a vector of HIs by the number of elements in an svpattern. @@ -11488,7 +11794,8 @@ return aarch64_output_sve_cnt_pat_immediate ("", "%0.", operands + 2); } - [(set_attr "movprfx" "*,yes")] + [(set_attr "movprfx" "*,yes") + (set_attr "sve_type" "sve_pred_vec")] ) ;; ------------------------------------------------------------------------- @@ -11515,6 +11822,7 @@ return aarch64_output_sve_cnt_pat_immediate ("", "%x0", operands + 2); } + [(set_attr "sve_type" "sve_pred_cnt_scalar")] ) ;; Decrement an SImode register by the number of elements in an svpattern @@ -11531,6 +11839,7 @@ { return aarch64_output_sve_cnt_pat_immediate ("dec", "%x0", operands + 2); } + [(set_attr "sve_type" "sve_pred_cnt_scalar")] ) ;; Decrement an SImode register by the number of elements in an svpattern @@ -11552,6 +11861,7 @@ return aarch64_output_sve_cnt_pat_immediate ("", registers, operands + 2); } + [(set_attr "sve_type" "sve_pred_cnt_scalar")] ) ;; ------------------------------------------------------------------------- @@ -11582,7 +11892,8 @@ return aarch64_output_sve_cnt_pat_immediate ("", "%0.", operands + 2); } - [(set_attr "movprfx" "*,yes")] + [(set_attr "movprfx" "*,yes") + (set_attr "sve_type" "sve_pred_vec")] ) ;; Decrement a vector of SIs by the number of elements in an svpattern. @@ -11603,7 +11914,8 @@ return aarch64_output_sve_cnt_pat_immediate ("", "%0.", operands + 2); } - [(set_attr "movprfx" "*,yes")] + [(set_attr "movprfx" "*,yes") + (set_attr "sve_type" "sve_pred_vec")] ) ;; Decrement a vector of HIs by the number of elements in an svpattern. @@ -11638,7 +11950,8 @@ return aarch64_output_sve_cnt_pat_immediate ("", "%0.", operands + 2); } - [(set_attr "movprfx" "*,yes")] + [(set_attr "movprfx" "*,yes") + (set_attr "sve_type" "sve_pred_vec")] ) ;; ------------------------------------------------------------------------- @@ -11658,7 +11971,9 @@ (match_operand:PRED_ALL 3 "register_operand" "Upa")] UNSPEC_CNTP)))] "TARGET_SVE" - "cntp\t%x0, %1, %3.") + "cntp\t%x0, %1, %3." + [(set_attr "sve_type" "sve_pred_cnt_scalar")] +) ;; ------------------------------------------------------------------------- ;; ---- [INT] Increment by the number of elements in a predicate (scalar) @@ -11701,6 +12016,7 @@ { operands[3] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_pred_cnt_scalar")] ) ;; Increment an SImode register by the number of set bits in a predicate @@ -11720,6 +12036,7 @@ { operands[3] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_pred_cnt_scalar")] ) ;; Increment an SImode register by the number of set bits in a predicate @@ -11761,6 +12078,7 @@ { operands[3] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_pred_cnt_scalar")] ) ;; ------------------------------------------------------------------------- @@ -11811,6 +12129,7 @@ { operands[3] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_pred_vec")] ) ;; Increment a vector of SIs by the number of set bits in a predicate. @@ -11850,6 +12169,7 @@ { operands[3] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_pred_vec")] ) ;; Increment a vector of HIs by the number of set bits in a predicate. @@ -11891,6 +12211,7 @@ { operands[4] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_pred_vec")] ) ;; ------------------------------------------------------------------------- @@ -11934,6 +12255,7 @@ { operands[3] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_pred_cnt_scalar")] ) ;; Decrement an SImode register by the number of set bits in a predicate @@ -11953,6 +12275,7 @@ { operands[3] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_pred_cnt_scalar")] ) ;; Decrement an SImode register by the number of set bits in a predicate @@ -11994,6 +12317,7 @@ { operands[3] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_pred_cnt_scalar")] ) ;; ------------------------------------------------------------------------- @@ -12044,6 +12368,7 @@ { operands[3] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_pred_vec")] ) ;; Decrement a vector of SIs by the number of set bits in a predicate. @@ -12083,6 +12408,7 @@ { operands[3] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_pred_vec")] ) ;; Decrement a vector of HIs by the number of set bits in a predicate. @@ -12124,6 +12450,7 @@ { operands[4] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_pred_vec")] ) (define_insn_and_split "@aarch64_sve_get_neonq_" @@ -12153,4 +12480,5 @@ "TARGET_SVE && BYTES_BIG_ENDIAN" "sel\t%0., %3, %Z2., %1." + [(set_attr "sve_type" "sve_int_general")] ) diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index a3cbbce8b31..69a376706fa 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -153,6 +153,7 @@ UNSPEC_PMOV_UNPACK))] "TARGET_SVE2p1 && TARGET_NON_STREAMING" "pmov\t%0, %1." + [(set_attr "sve_type" "sve_pred_vec")] ) (define_insn "@aarch64_pmov_lane_to_" @@ -164,6 +165,7 @@ UNSPEC_PMOV_UNPACK_LANE))] "TARGET_SVE2p1 && TARGET_NON_STREAMING" "pmov\t%0[%3], %2." + [(set_attr "sve_type" "sve_pred_vec")] ) ;; ------------------------------------------------------------------------- @@ -180,6 +182,7 @@ UNSPEC_PMOV_PACK))] "TARGET_SVE2p1 && TARGET_NON_STREAMING" "pmov\t%0., %1" + [(set_attr "sve_type" "sve_pred_vec")] ) (define_insn "@aarch64_pmov_lane_from_" @@ -190,6 +193,7 @@ UNSPEC_PMOV_PACK_LANE))] "TARGET_SVE2p1 && TARGET_NON_STREAMING" "pmov\t%0., %1[%2]" + [(set_attr "sve_type" "sve_pred_vec")] ) ;; ========================================================================= @@ -228,6 +232,7 @@ UNSPEC_LD1_EXTENDQ))] "TARGET_SVE2p1 && TARGET_NON_STREAMING" "ld1\t{%0.q}, %2/z, %1" + [(set_attr "sve_type" "sve_load_1reg")] ) ;; ------------------------------------------------------------------------- @@ -248,6 +253,7 @@ UNSPEC_LDNQ))] "TARGET_SVE2p1 && TARGET_NON_STREAMING" "ldq\t{%S0.q - %0.q}, %2/z, %1" + [(set_attr "sve_type" "sve_load_reg")] ) ;; ------------------------------------------------------------------------- @@ -274,7 +280,8 @@ LD1_COUNT))] "TARGET_SVE2p1_OR_SME2" "\t%0, %K2/z, %1" - [(set_attr "stride_type" "ld1_consecutive")] + [(set_attr "stride_type" "ld1_consecutive") + (set_attr "sve_type" "sve_load_reg")] ) (define_insn "@aarch64__strided2" @@ -293,7 +300,8 @@ "TARGET_STREAMING_SME2 && aarch64_strided_registers_p (operands, 2, 8)" "\t{%0., %1.}, %K3/z, %2" - [(set_attr "stride_type" "ld1_strided")] + [(set_attr "stride_type" "ld1_strided") + (set_attr "sve_type" "sve_load_2reg")] ) (define_insn "@aarch64__strided4" @@ -324,7 +332,8 @@ "TARGET_STREAMING_SME2 && aarch64_strided_registers_p (operands, 4, 4)" "\t{%0., %1., %2., %3.}, %K5/z, %4" - [(set_attr "stride_type" "ld1_strided")] + [(set_attr "stride_type" "ld1_strided") + (set_attr "sve_type" "sve_load_4reg")] ) ;; ------------------------------------------------------------------------- @@ -361,6 +370,7 @@ [&w, Upl, r, w] ld1q\t{%0.q}, %1/z, [%3.d, %2] [?w, Upl, r, 0] ^ } + [(set_attr "sve_type" "sve_gatherload_64")] ) ;; ------------------------------------------------------------------------- @@ -389,6 +399,7 @@ [&w, Upl, r, w ] ldnt1\t%0., %1/z, [%3., %2] [?w, Upl, r, 0 ] ^ } + [(set_attr "sve_type" "sve_gatherload_64")] ) ;; Extending loads. @@ -417,6 +428,7 @@ { operands[4] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_gatherload_64")] ) ;; ========================================================================= @@ -442,6 +454,7 @@ UNSPEC_ST1_TRUNCQ))] "TARGET_SVE2p1 && TARGET_NON_STREAMING" "st1\t{%1.q}, %2, %0" + [(set_attr "sve_type" "sve_store_1reg")] ) ;; ------------------------------------------------------------------------- @@ -463,6 +476,7 @@ UNSPEC_STNQ))] "TARGET_SVE2p1 && TARGET_NON_STREAMING" "stq\t{%S1.q - %1.q}, %2, %0" + [(set_attr "sve_type" "sve_store_reg")] ) ;; ------------------------------------------------------------------------- @@ -488,7 +502,8 @@ ST1_COUNT))] "TARGET_SVE2p1_OR_SME2" "\t%1, %K2, %0" - [(set_attr "stride_type" "st1_consecutive")] + [(set_attr "stride_type" "st1_consecutive") + (set_attr "sve_type" "sve_store_1reg")] ) (define_insn "@aarch64__strided2" @@ -502,7 +517,8 @@ "TARGET_STREAMING_SME2 && aarch64_strided_registers_p (operands + 2, 2, 8)" "\t{%2., %3.}, %K1, %0" - [(set_attr "stride_type" "st1_strided")] + [(set_attr "stride_type" "st1_strided") + (set_attr "sve_type" "sve_store_1reg")] ) (define_insn "@aarch64__strided4" @@ -518,7 +534,8 @@ "TARGET_STREAMING_SME2 && aarch64_strided_registers_p (operands + 2, 4, 4)" "\t{%2., %3., %4., %5.}, %K1, %0" - [(set_attr "stride_type" "st1_strided")] + [(set_attr "stride_type" "st1_strided") + (set_attr "sve_type" "sve_store_1reg")] ) ;; ------------------------------------------------------------------------- @@ -541,6 +558,7 @@ [ Upl , Z , w , w ] st1q\t{%3.q}, %0, [%2.d] [ Upl , r , w , w ] st1q\t{%3.q}, %0, [%2.d, %1] } + [(set_attr "sve_type" "sve_scatterstore_64")] ) ;; ------------------------------------------------------------------------- @@ -568,6 +586,7 @@ [ Upl , Z , w , w ] stnt1\t%3., %0, [%2.] [ Upl , r , w , w ] stnt1\t%3., %0, [%2., %1] } + [(set_attr "sve_type" "sve_scatterstore_64")] ) ;; Truncating stores. @@ -587,6 +606,7 @@ [ Upl , Z , w , w ] stnt1\t%3., %0, [%2.] [ Upl , r , w , w ] stnt1\t%3., %0, [%2., %1] } + [(set_attr "sve_type" "sve_scatterstore_64")] ) ;; ========================================================================= @@ -604,6 +624,7 @@ (unspec:VNx16BI [(const_int BHSD_BITS)] UNSPEC_PTRUE_C))] "TARGET_SVE2p1_OR_SME2" "ptrue\t%K0." + [(set_attr "sve_type" "sve_pred_misc")] ) ;; ------------------------------------------------------------------------- @@ -622,6 +643,7 @@ UNSPEC_PEXT))] "TARGET_SVE2p1_OR_SME2" "pext\t%0., %K1[%2]" + [(set_attr "sve_type" "sve_pred_misc")] ) (define_insn "@aarch64_sve_pextx2" @@ -633,6 +655,7 @@ UNSPEC_PEXTx2))] "TARGET_SVE2p1_OR_SME2" "pext\t{%S0., %T0.}, %K1[%2]" + [(set_attr "sve_type" "sve_pred_misc")] ) ;; ------------------------------------------------------------------------- @@ -652,6 +675,7 @@ UNSPEC_PSEL))] "TARGET_SVE2p1_OR_SME" "psel\t%0, %1, %2.[%w3, 0]" + [(set_attr "sve_type" "sve_pred_misc")] ) (define_insn "*aarch64_sve_psel_plus" @@ -667,6 +691,7 @@ "TARGET_SVE2p1_OR_SME && UINTVAL (operands[4]) < 128 / " "psel\t%0, %1, %2.[%w3, %4]" + [(set_attr "sve_type" "sve_pred_misc")] ) ;; ------------------------------------------------------------------------- @@ -685,6 +710,7 @@ UNSPEC_CNTP_C))] "TARGET_SVE2p1_OR_SME2" "cntp\t%x0, %K1., vlx%2" + [(set_attr "sve_type" "sve_pred_cnt_scalar")] ) ;; ========================================================================= @@ -708,6 +734,7 @@ SVE2_SFx24_UNARY))] "TARGET_STREAMING_SME2" "frint\t%0, %1" + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; ========================================================================= @@ -743,6 +770,7 @@ (match_operand:SVE_Ix24 2 "aligned_register_operand" "Uw")))] "TARGET_STREAMING_SME2" "\t%0, %0, %2" + [(set_attr "sve_type" "sve_")] ) (define_insn "@aarch64_sve_single_" @@ -753,6 +781,7 @@ (match_operand: 2 "register_operand" "x"))))] "TARGET_STREAMING_SME2" "\t%0, %0, %2." + [(set_attr "sve_type" "sve_")] ) (define_insn "@aarch64_sve_" @@ -763,6 +792,7 @@ SVE_INT_BINARY_MULTI))] "TARGET_STREAMING_SME2" "\t%0, %0, %2" + [(set_attr "sve_type" "sve_")] ) (define_insn "@aarch64_sve_single_" @@ -774,6 +804,7 @@ SVE_INT_BINARY_MULTI))] "TARGET_STREAMING_SME2" "\t%0, %0, %2." + [(set_attr "sve_type" "sve_")] ) ;; ------------------------------------------------------------------------- @@ -797,6 +828,7 @@ [ w, 0, w, w; * ] clamp\t%0., %2., %3. [ ?&w, w, w, w; yes ] movprfx\t%0, %1\;clamp\t%0., %2., %3. } + [(set_attr "sve_type" "sve_int_general")] ) (define_insn_and_split "*aarch64_sve_clamp_x" @@ -837,6 +869,7 @@ (match_operand: 3 "register_operand" "w"))))] "TARGET_STREAMING_SME2" "clamp\t%0, %2., %3." + [(set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -856,6 +889,7 @@ (match_operand:SVE_FULL_HSDI_SIMD_DI 1 "register_operand" "w")))] "TARGET_SVE2" "mul\t%Z0., %Z1., %Z2.[%3]" + [(set_attr "sve_type" "sve_int_mul")] ) ;; The 2nd and 3rd alternatives are valid for just TARGET_SVE as well but @@ -871,6 +905,7 @@ [ w , 0 , vsm ; * ] mul\t%Z0., %Z0., #%2 [ ?&w , w , vsm ; yes ] movprfx\t%Z0, %Z1\;mul\t%Z0., %Z0., #%2 } + [(set_attr "sve_type" "sve_int_mul")] ) ;; ------------------------------------------------------------------------- @@ -990,7 +1025,8 @@ "@ sqadd\t%0., %0., #%D2 movprfx\t%0, %1\;sqadd\t%0., %0., #%D2" - [(set_attr "movprfx" "*,yes")] + [(set_attr "movprfx" "*,yes") + (set_attr "sve_type" "sve_int_general")] ) ;; General predicated binary arithmetic. All operations handled here @@ -1010,6 +1046,7 @@ [ w , Upl , w , 0 ; * ] \t%0., %1/m, %0., %2. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %0., %3. } + [(set_attr "sve_type" "sve_int_general")] ) ;; Predicated binary arithmetic with merging. @@ -1055,6 +1092,7 @@ { operands[4] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_int_general")] ) ;; Predicated binary arithmetic, merging with the second input. @@ -1080,6 +1118,7 @@ { operands[4] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_int_general")] ) ;; Predicated binary operations, merging with an independent value. @@ -1121,7 +1160,8 @@ else FAIL; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_int_general")] ) ;; Predicated binary operations with no reverse form, merging with zero. @@ -1150,7 +1190,8 @@ { operands[5] = CONSTM1_RTX (mode); } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -1182,6 +1223,7 @@ SVE2_INT_BINARY_LANE))] "TARGET_SVE2" "\t%0., %1., %2.[%3]" + [(set_attr "sve_type" "sve_int_mul")] ) ;; ------------------------------------------------------------------------- @@ -1212,6 +1254,7 @@ [ ?&w , Upl , w , D ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %0., #%3 [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %0., %3. } + [(set_attr "sve_type" "sve_int_shift")] ) ;; Predicated left shifts with merging. @@ -1259,6 +1302,7 @@ { operands[4] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_int_shift")] ) ;; Predicated left shifts, merging with the second input. @@ -1284,6 +1328,7 @@ { operands[4] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_int_shift")] ) ;; Predicated left shifts, merging with an independent value. @@ -1329,7 +1374,8 @@ else FAIL; } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_int_shift")] ) ;; ------------------------------------------------------------------------- @@ -1360,7 +1406,8 @@ [ ?&w , Upl , w , w ; yes , * ] movprfx\t%0, %2\;\t%0., %1/m, %0., %3. } [(set_attr "is_bf16" "") - (set_attr "supports_bf16_rev" "")] + (set_attr "supports_bf16_rev" "") + (set_attr "sve_type" "sve_")] ) ;; ------------------------------------------------------------------------- @@ -1386,6 +1433,7 @@ [ w, 0, w, w; * ] fclamp\t%0., %2., %3. [ ?&w, w, w, w; yes ] movprfx\t%0, %1\;fclamp\t%0., %2., %3. } + [(set_attr "sve_type" "sve_fp_arith")] ) (define_insn_and_split "*aarch64_sve_fclamp_x" @@ -1430,6 +1478,7 @@ UNSPEC_FMINNM))] "TARGET_STREAMING_SME2" "fclamp\t%0, %2., %3." + [(set_attr "sve_type" "sve_fp_arith")] ) ;; ========================================================================= @@ -1462,6 +1511,7 @@ [ w , 0 , w , w ; * ] \t%0., %2., %3. [ ?&w , w , w , w ; yes ] movprfx\t%0, %1\;\t%0., %2., %3. } + [(set_attr "sve_type" "sve_")] ) (define_insn "@aarch64_sve__lane_" @@ -1479,6 +1529,7 @@ [ w , 0 , w , ; * ] \t%0., %2., %3.[%4] [ ?&w , w , w , ; yes ] movprfx\t%0, %1\;\t%0., %2., %3.[%4] } + [(set_attr "sve_type" "sve_")] ) ;; ------------------------------------------------------------------------- @@ -1504,6 +1555,7 @@ [ w , 0 , w , ; * ] mla\t%0., %2., %3.[%4] [ ?&w , w , w , ; yes ] movprfx\t%0, %1\;mla\t%0., %2., %3.[%4] } + [(set_attr "sve_type" "sve_int_mul")] ) (define_insn "@aarch64_sve_sub_mul_lane_" @@ -1521,6 +1573,7 @@ [ w , 0 , w , ; * ] mls\t%0., %2., %3.[%4] [ ?&w , w , w , ; yes ] movprfx\t%0, %1\;mls\t%0., %2., %3.[%4] } + [(set_attr "sve_type" "sve_int_mul")] ) ;; ------------------------------------------------------------------------- @@ -1551,7 +1604,8 @@ return "xar\t%Z0., %Z0., %Z2., #%3"; return "movprfx\t%Z0, %Z1\;xar\t%Z0., %Z0., %Z2., #%3"; } - [(set_attr "movprfx" "*,yes")] + [(set_attr "movprfx" "*,yes") + (set_attr "sve_type" "sve_crypto_sha3")] ) ;; ------------------------------------------------------------------------- @@ -1604,6 +1658,7 @@ { operands[4] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_crypto_sha3")] ) ;; Unpredicated 3-way exclusive OR. @@ -1621,6 +1676,7 @@ [ w , w , w , 0 ; * ] eor3\t%0.d, %0.d, %1.d, %2.d [ ?&w , w , w , w ; yes ] movprfx\t%0, %1\;eor3\t%0.d, %0.d, %2.d, %3.d } + [(set_attr "sve_type" "sve_crypto_sha3")] ) ;; Use NBSL for vector NOR. @@ -1643,6 +1699,7 @@ { operands[3] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_int_general")] ) (define_insn "*aarch64_sve2_unpred_nor" @@ -1657,6 +1714,7 @@ [ w , 0 , w ; * ] nbsl\t%Z0.d, %Z0.d, %Z2.d, %Z0.d [ ?&w , w , w ; yes ] movprfx\t%Z0, %Z1\;nbsl\t%Z0.d, %Z0.d, %Z2.d, %Z1.d } + [(set_attr "sve_type" "sve_int_general")] ) ;; Use NBSL for vector NAND. @@ -1679,6 +1737,7 @@ { operands[3] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_int_general")] ) ;; Same as above but unpredicated and including Advanced SIMD modes. @@ -1694,6 +1753,7 @@ [ w , 0 , w ; * ] nbsl\t%Z0.d, %Z0.d, %Z2.d, %Z2.d [ ?&w , w , w ; yes ] movprfx\t%Z0, %Z1\;nbsl\t%Z0.d, %Z0.d, %Z2.d, %Z2.d } + [(set_attr "sve_type" "sve_int_general")] ) ;; Unpredicated bitwise select. @@ -1724,6 +1784,7 @@ [ w , , , w ; * ] bsl\t%0.d, %0.d, %.d, %3.d [ ?&w , w , w , w ; yes ] movprfx\t%0, %\;bsl\t%0.d, %0.d, %.d, %3.d } + [(set_attr "sve_type" "sve_int_general")] ) ;; Unpredicated bitwise inverted select. @@ -1769,6 +1830,7 @@ { operands[4] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_int_general")] ) (define_insn "*aarch64_sve2_nbsl_unpred" @@ -1786,6 +1848,7 @@ [ w , , , w ; * ] nbsl\t%Z0.d, %Z0.d, %Z.d, %Z3.d [ ?&w , w , w , w ; yes ] movprfx\t%Z0, %Z\;nbsl\t%Z0.d, %Z0.d, %Z.d, %Z3.d } + [(set_attr "sve_type" "sve_int_general")] ) ;; Unpredicated bitwise select with inverted first operand. @@ -1831,6 +1894,7 @@ { operands[4] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_int_general")] ) (define_insn "*aarch64_sve2_bsl1n_unpred" @@ -1848,6 +1912,7 @@ [ w , , , w ; * ] bsl1n\t%Z0.d, %Z0.d, %Z.d, %Z3.d [ ?&w , w , w , w ; yes ] movprfx\t%Z0, %Z\;bsl1n\t%Z0.d, %Z0.d, %Z.d, %Z3.d } + [(set_attr "sve_type" "sve_int_general")] ) ;; Unpredicated bitwise select with inverted second operand. @@ -1895,6 +1960,7 @@ { operands[4] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_int_general")] ) ;; Unpredicated bitwise select with inverted second operand, alternative form. @@ -1922,6 +1988,7 @@ { operands[4] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_int_general")] ) (define_insn "*aarch64_sve2_bsl2n_unpred" @@ -1938,6 +2005,7 @@ [ w , , , w ; * ] bsl2n\t%Z0.d, %Z0.d, %Z3.d, %Z.d [ ?&w , w , w , w ; yes ] movprfx\t%Z0, %Z\;bsl2n\t%Z0.d, %Z0.d, %Z3.d, %Z.d } + [(set_attr "sve_type" "sve_int_general")] ) (define_insn "*aarch64_sve2_bsl2n_unpred" @@ -1954,6 +2022,7 @@ [ w , , , w ; * ] bsl2n\t%Z0.d, %Z0.d, %Z3.d, %Z.d [ ?&w , w , w , w ; yes ] movprfx\t%Z0, %Z\;bsl2n\t%Z0.d, %Z0.d, %Z3.d, %Z.d } + [(set_attr "sve_type" "sve_int_general")] ) ;; Vector EON (~(x, y)) using BSL2N. @@ -1975,6 +2044,7 @@ { operands[3] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_int_general")] ) (define_insn "*aarch64_sve2_eon_bsl2n_unpred" @@ -1988,6 +2058,7 @@ [ w , 0, w ; * ] bsl2n\t%Z0.d, %Z0.d, %Z0.d, %Z2.d [ ?&w, w, w ; yes ] movprfx\t%Z0, %Z1\;bsl2n\t%Z0.d, %Z0.d, %Z1.d, %Z2.d } + [(set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -2025,6 +2096,7 @@ [ w , 0 , w ; * ] sra\t%0., %2., #%3 [ ?&w , w , w ; yes ] movprfx\t%0, %1\;sra\t%0., %2., #%3 } + [(set_attr "sve_type" "sve_int_shift")] ) ;; SRSRA and URSRA. @@ -2041,6 +2113,7 @@ [ w , 0 , w ; * ] sra\t%0., %2., #%3 [ ?&w , w , w ; yes ] movprfx\t%0, %1\;sra\t%0., %2., #%3 } + [(set_attr "sve_type" "sve_int_shift")] ) ;; ------------------------------------------------------------------------- @@ -2061,6 +2134,7 @@ SVE2_INT_SHIFT_INSERT))] "TARGET_SVE2" "\t%0., %2., #%3" + [(set_attr "sve_type" "sve_int_shift")] ) ;; ------------------------------------------------------------------------- @@ -2119,6 +2193,7 @@ [ w , 0 , w , w ; * ] aba\t%0., %2., %3. [ ?&w , w , w , w ; yes ] movprfx\t%0, %1\;aba\t%0., %2., %3. } + [(set_attr "sve_type" "sve_int_accum")] ) ;; ------------------------------------------------------------------------- @@ -2152,6 +2227,7 @@ [ w , 0 , w , w ; * ] \t%0.h, %2.b, %3.b [ ?&w , w , w , w ; yes ] movprfx\t%0, %1\;\t%0.h, %2.b, %3.b } + [(set_attr "sve_type" "sve_fp_mul")] ) (define_insn "@aarch64_sve_add_" @@ -2167,6 +2243,7 @@ [ w , 0 , w , w ; * ] \t%0.s, %2.b, %3.b [ ?&w , w , w , w ; yes ] movprfx\t%0, %1\;\t%0.s, %2.b, %3.b } + [(set_attr "sve_type" "sve_fp_mul")] ) (define_insn "@aarch64_sve_add_lane_" @@ -2183,6 +2260,7 @@ [ w , 0 , w , y ; * ] \t%0.h, %2.b, %3.b[%4] [ ?&w , w , w , y ; yes ] movprfx\t%0, %1\;\t%0.h, %2.b, %3.b[%4] } + [(set_attr "sve_type" "sve_fp_mul")] ) (define_insn "@aarch64_sve_add_lane_" @@ -2199,6 +2277,7 @@ [ w , 0 , w , y ; * ] \t%0.s, %2.b, %3.b[%4] [ ?&w , w , w , y ; yes ] movprfx\t%0, %1\;\t%0.s, %2.b, %3.b[%4] } + [(set_attr "sve_type" "sve_fp_mul")] ) ;; ------------------------------------------------------------------------- @@ -2223,6 +2302,7 @@ [ w , 0 , w , w ; * ] fdot\t%0., %2.b, %3.b [ ?&w , w , w , w ; yes ] movprfx\t%0, %1\;fdot\t%0., %2.b, %3.b } + [(set_attr "sve_type" "sve_fp_mul")] ) (define_insn "@aarch64_sve_dot_lane" @@ -2239,6 +2319,7 @@ [ w , 0 , w , y ; * ] fdot\t%0., %2.b, %3.b[%4] [ ?&w , w , w , y ; yes ] movprfx\t%0, %1\;fdot\t%0., %2.b, %3.b[%4] } + [(set_attr "sve_type" "sve_fp_mul")] ) ;; ========================================================================= @@ -2259,6 +2340,7 @@ (match_operand:SVE_FULL_BHSI 1 "register_operand" "w")))] "TARGET_STREAMING_SME2" "unpk\t%0, %1." + [(set_attr "sve_type" "sve_int_general")] ) (define_insn "2" @@ -2267,6 +2349,7 @@ (match_operand:SVE_FULL_BHSIx2 1 "aligned_register_operand" "Uw2")))] "TARGET_STREAMING_SME2" "unpk\t%0, %1" + [(set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -2291,6 +2374,7 @@ SVE2_INT_BINARY_WIDE))] "TARGET_SVE2" "\t%0., %1., %2." + [(set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -2328,6 +2412,7 @@ SVE2_INT_BINARY_LONG))] "TARGET_SVE2" "\t%0., %1., %2." + [(set_attr "sve_type" "sve_")] ) (define_insn "@aarch64_sve__lane_" @@ -2341,6 +2426,7 @@ SVE2_INT_BINARY_LONG_LANE))] "TARGET_SVE2" "\t%0., %1., %2.[%3]" + [(set_attr "sve_type" "sve_")] ) ;; ------------------------------------------------------------------------- @@ -2362,6 +2448,7 @@ SVE2_INT_SHIFT_IMM_LONG))] "TARGET_SVE2" "\t%0., %1., #%2" + [(set_attr "sve_type" "sve_int_shift")] ) ;; ------------------------------------------------------------------------- @@ -2404,6 +2491,7 @@ [ w , 0 , w , w ; * ] \t%0., %2., %3. [ ?&w , w , w , w ; yes ] movprfx\t%0, %1\;\t%0., %2., %3. } + [(set_attr "sve_type" "sve_")] ) ;; Non-saturating MLA operations with lane select. @@ -2423,6 +2511,7 @@ [ w , 0 , w , ; * ] \t%0., %2., %3.[%4] [ ?&w , w , w , ; yes ] movprfx\t%0, %1\;\t%0., %2., %3.[%4] } + [(set_attr "sve_type" "sve_")] ) ;; Saturating MLA operations. @@ -2439,6 +2528,7 @@ [ w , 0 , w , w ; * ] \t%0., %2., %3. [ ?&w , w , w , w ; yes ] movprfx\t%0, %1\;\t%0., %2., %3. } + [(set_attr "sve_type" "sve_")] ) ;; Saturating MLA operations with lane select. @@ -2458,6 +2548,7 @@ [ w , 0 , w , ; * ] \t%0., %2., %3.[%4] [ ?&w , w , w , ; yes ] movprfx\t%0, %1\;\t%0., %2., %3.[%4] } + [(set_attr "sve_type" "sve_")] ) ;; Non-saturating MLS operations. @@ -2474,6 +2565,7 @@ [ w , 0 , w , w ; * ] \t%0., %2., %3. [ ?&w , w , w , w ; yes ] movprfx\t%0, %1\;\t%0., %2., %3. } + [(set_attr "sve_type" "sve_")] ) ;; Non-saturating MLS operations with lane select. @@ -2493,6 +2585,7 @@ [ w , 0 , w , ; * ] \t%0., %2., %3.[%4] [ ?&w , w , w , ; yes ] movprfx\t%0, %1\;\t%0., %2., %3.[%4] } + [(set_attr "sve_type" "sve_")] ) ;; Saturating MLS operations. @@ -2509,6 +2602,7 @@ [ w , 0 , w , w ; * ] \t%0., %2., %3. [ ?&w , w , w , w ; yes ] movprfx\t%0, %1\;\t%0., %2., %3. } + [(set_attr "sve_type" "sve_")] ) ;; Saturating MLS operations with lane select. @@ -2528,6 +2622,7 @@ [ w , 0 , w , ; * ] \t%0., %2., %3.[%4] [ ?&w , w , w , ; yes ] movprfx\t%0, %1\;\t%0., %2., %3.[%4] } + [(set_attr "sve_type" "sve_")] ) ;; Two-way dot-product. @@ -2544,6 +2639,7 @@ [ w , w , w , 0 ; * ] dot\t%0.s, %1.h, %2.h [ ?&w , w , w , w ; yes ] movprfx\t%0, %3\;dot\t%0.s, %1.h, %2.h } + [(set_attr "sve_type" "sve_int_dot")] ) ;; ------------------------------------------------------------------------- @@ -2573,6 +2669,7 @@ SVE_FP_BINARY_MULTI))] "TARGET_STREAMING_SME2" "\t%0, %0, %2" + [(set_attr "sve_type" "sve_")] ) (define_insn "@aarch64_sve_single_" @@ -2584,6 +2681,7 @@ SVE_FP_BINARY_MULTI))] "TARGET_STREAMING_SME2" "\t%0, %0, %2." + [(set_attr "sve_type" "sve_")] ) ;; ------------------------------------------------------------------------- @@ -2609,6 +2707,7 @@ [ w , w , w , 0 ; * ] \t%0., %1., %2. [ ?&w , w , w , w ; yes ] movprfx\t%0, %3\;\t%0., %1., %2. } + [(set_attr "sve_type" "sve_")] ) (define_insn "@aarch64__lane_" @@ -2626,6 +2725,7 @@ [ w , w , , 0 ; * ] \t%0., %1., %2.[%3] [ ?&w , w , , w ; yes ] movprfx\t%0, %4\;\t%0., %1., %2.[%3] } + [(set_attr "sve_type" "sve_")] ) ;; Two-way dot-product. @@ -2642,6 +2742,7 @@ [ w , w , w , 0 ; * ] fdot\t%0.s, %1.h, %2.h [ ?&w , w , w , w ; yes ] movprfx\t%0, %3\;fdot\t%0.s, %1.h, %2.h } + [(set_attr "sve_type" "sve_fp_mul")] ) (define_insn "aarch64_fdot_prod_lanevnx4sfvnx8hf" @@ -2660,6 +2761,7 @@ [ w , w , y , 0 ; * ] fdot\t%0.s, %1.h, %2.h[%3] [ ?&w , w , y , w ; yes ] movprfx\t%0, %4\;fdot\t%0.s, %1.h, %2.h[%3] } + [(set_attr "sve_type" "sve_fp_mul")] ) ;; ========================================================================= @@ -2685,6 +2787,7 @@ SVE2_INT_UNARY_NARROWB))] "TARGET_SVE2" "\t%0., %1." + [(set_attr "sve_type" "sve_int_extract")] ) ;; These instructions do not take MOVPRFX. @@ -2696,6 +2799,7 @@ SVE2_INT_UNARY_NARROWT))] "TARGET_SVE2" "\t%0., %2." + [(set_attr "sve_type" "sve_int_extract")] ) ;; ------------------------------------------------------------------------- @@ -2715,6 +2819,7 @@ SVE_QCVTxN))] "TARGET_STREAMING_SME2" "\t%0.b, %1" + [(set_attr "sve_type" "sve_int_extract")] ) (define_insn "@aarch64_sve_" @@ -2724,6 +2829,7 @@ SVE_QCVTxN))] "" "\t%0.h, %1" + [(set_attr "sve_type" "sve_int_extract")] ) (define_insn "@aarch64_sve_" @@ -2733,6 +2839,7 @@ SVE_QCVTxN))] "TARGET_STREAMING_SME2" "\t%0.h, %1" + [(set_attr "sve_type" "sve_int_extract")] ) ;; ------------------------------------------------------------------------- @@ -2757,6 +2864,7 @@ SVE2_INT_BINARY_NARROWB))] "TARGET_SVE2" "\t%0., %1., %2." + [(set_attr "sve_type" "sve_int_general")] ) ;; These instructions do not take MOVPRFX. @@ -2769,6 +2877,7 @@ SVE2_INT_BINARY_NARROWT))] "TARGET_SVE2" "\t%0., %2., %3." + [(set_attr "sve_type" "sve_int_general")] ) ;; Optimize ((a + b) >> n) where n is half the bitsize of the vector @@ -2782,6 +2891,7 @@ "aarch64_simd_shift_imm_vec_exact_top" "")))] "TARGET_SVE2" "addhnb\t%0., %1., %2." + [(set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -2815,6 +2925,7 @@ SVE2_INT_SHIFT_IMM_NARROWB))] "TARGET_SVE2" "\t%0., %1., #%2" + [(set_attr "sve_type" "sve_int_shift")] ) ;; The immediate range is enforced before generating the instruction. @@ -2828,6 +2939,7 @@ SVE2_INT_SHIFT_IMM_NARROWT))] "TARGET_SVE2" "\t%0., %2., #%3" + [(set_attr "sve_type" "sve_int_shift")] ) ;; ------------------------------------------------------------------------- @@ -2850,6 +2962,7 @@ SVE2_INT_SHIFT_IMM_NARROWxN))] "(mode == VNx8SImode || TARGET_STREAMING_SME2)" "\t%0., %1, #%2" + [(set_attr "sve_type" "sve_int_shift")] ) ;; ========================================================================= @@ -2879,6 +2992,7 @@ [ w , Upl , 0 , w ; * ] \t%0., %1/m, %0., %3. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %0., %3. } + [(set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -2904,6 +3018,7 @@ [ w , Upl , 0 , w ; * ] \t%0., %1/m, %0., %3. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %0., %3. } + [(set_attr "sve_type" "sve_fp_arith")] ) ;; ------------------------------------------------------------------------- @@ -2956,6 +3071,7 @@ { operands[4] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_int_accum")] ) ;; Predicated pairwise absolute difference and accumulate, merging with zero. @@ -2979,7 +3095,8 @@ { operands[5] = CONSTM1_RTX (mode); } - [(set_attr "movprfx" "yes")] + [(set_attr "movprfx" "yes") + (set_attr "sve_type" "sve_int_accum")] ) ;; ------------------------------------------------------------------------- @@ -3017,6 +3134,7 @@ operands[5] = copy_rtx (operands[1]); operands[6] = copy_rtx (operands[1]); } + [(set_attr "sve_type" "sve_fp_arith")] ) ;; ========================================================================= @@ -3042,6 +3160,7 @@ [ w , 0 , w ; * ] \t%0., %0., %2., # [ ?&w , w , w ; yes ] movprfx\t%0, %1\;\t%0., %0., %2., # } + [(set_attr "sve_type" "sve_int_general")] ) ;; unpredicated optab pattern for auto-vectorizer @@ -3074,6 +3193,7 @@ [ w , 0 , w , w ; * ] \t%0., %2., %3., # [ ?&w , w , w , w ; yes ] movprfx\t%0, %1\;\t%0., %2., %3., # } + [(set_attr "sve_type" "sve_int_mul")] ) (define_insn "@aarch64__lane_" @@ -3091,6 +3211,7 @@ [ w , 0 , w , ; * ] \t%0., %2., %3.[%4], # [ ?&w , w , w , ; yes ] movprfx\t%0, %1\;\t%0., %2., %3.[%4], # } + [(set_attr "sve_type" "sve_int_mul")] ) ;; unpredicated optab pattern for auto-vectorizer @@ -3154,6 +3275,7 @@ [ w , 0 , w , w ; * ] \t%0., %2., %3., # [ ?&w , w , w , w ; yes ] movprfx\t%0, %1\;\t%0., %2., %3., # } + [(set_attr "sve_type" "sve_int_dot")] ) (define_insn "@aarch64__lane_" @@ -3171,6 +3293,7 @@ [ w , 0 , w , ; * ] \t%0., %2., %3.[%4], # [ ?&w , w , w , ; yes ] movprfx\t%0, %1\;\t%0., %2., %3.[%4], # } + [(set_attr "sve_type" "sve_int_dot")] ) ;; ========================================================================= @@ -3202,6 +3325,7 @@ SVE2_COND_FP_UNARY_LONG))] "TARGET_SVE2" "\t%0., %1/m, %0." + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; Predicated convert long top with merging. @@ -3237,6 +3361,7 @@ { operands[4] = copy_rtx (operands[1]); } + [(set_attr "sve_type" "sve_fp_cvt")] ) (define_insn "*cond__strict" @@ -3252,6 +3377,7 @@ UNSPEC_SEL))] "TARGET_SVE2" "\t%0., %1/m, %2." + [(set_attr "sve_type" "sve_fp_cvt")] ) (define_insn "@aarch64_sve2_fp8_cvt_" @@ -3262,6 +3388,7 @@ FP8CVT_UNS))] "TARGET_SSVE_FP8" "\t%0.h, %1.b" + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; ------------------------------------------------------------------------- @@ -3288,6 +3415,7 @@ UNSPEC_COND_FCVTNT))] "TARGET_SVE2" "fcvtnt\t%0., %2/m, %3." + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; Predicated FCVTX (equivalent to what would be FCVTXNB, except that @@ -3304,6 +3432,7 @@ [ w , Upl , 0 ; * ] \t%0., %1/m, %2. [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; Predicated FCVTX with merging. @@ -3342,6 +3471,7 @@ { operands[4] = copy_rtx (operands[1]); } + [(set_attr "sve_type" "sve_fp_cvt")] ) (define_insn "*cond__any_strict" @@ -3361,6 +3491,7 @@ [ &w , Upl , w , Dz ; yes ] movprfx\t%0., %1/z, %2.\;\t%0., %1/m, %2. [ &w , Upl , w , w ; yes ] movprfx\t%0, %3\;\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; Predicated FCVTXNT. This doesn't give a natural aarch64_pred_*/cond_* @@ -3378,6 +3509,7 @@ UNSPEC_COND_FCVTXNT))] "TARGET_SVE2" "fcvtxnt\t%0., %2/m, %3." + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; ------------------------------------------------------------------------- @@ -3394,6 +3526,7 @@ (match_operand:VNx8HF 1 "register_operand" "w")))] "TARGET_STREAMING_SME_F16F16" "fcvt\t%0, %1.h" + [(set_attr "sve_type" "sve_fp_cvt")] ) (define_insn "@aarch64_sve_cvtl" @@ -3403,6 +3536,7 @@ UNSPEC_FCVTL))] "TARGET_STREAMING_SME_F16F16" "fcvtl\t%0, %1.h" + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; ------------------------------------------------------------------------- @@ -3423,6 +3557,7 @@ (match_operand:VNx8SF 1 "aligned_register_operand" "Uw2")))] "TARGET_STREAMING_SME2" "fcvt\t%0.h, %1" + [(set_attr "sve_type" "sve_fp_cvt")] ) (define_insn "@aarch64_sve_cvtn" @@ -3432,6 +3567,7 @@ UNSPEC_FCVTN))] "TARGET_STREAMING_SME2" "fcvtn\t%0.h, %1" + [(set_attr "sve_type" "sve_fp_cvt")] ) (define_insn "@aarch64_sve2_fp8_cvtn" @@ -3442,6 +3578,7 @@ UNSPEC_FP8FCVTN))] "TARGET_SSVE_FP8" "fcvtn\t%0.b, %1" + [(set_attr "sve_type" "sve_fp_cvt")] ) (define_insn "@aarch64_sve2_fp8_cvtnb" @@ -3452,6 +3589,7 @@ UNSPEC_FCVTNB))] "TARGET_SSVE_FP8" "fcvtnb\t%0.b, %1" + [(set_attr "sve_type" "sve_fp_cvt")] ) (define_insn "@aarch64_sve_cvtnt" @@ -3463,6 +3601,7 @@ UNSPEC_FCVTNT))] "TARGET_SSVE_FP8" "fcvtnt\t%0.b, %2" + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; ------------------------------------------------------------------------- @@ -3479,6 +3618,7 @@ (match_operand: 1 "aligned_register_operand" "Uw")))] "TARGET_STREAMING_SME2" "cvtf\t%0, %1" + [(set_attr "sve_type" "sve_int_cvt")] ) ;; ------------------------------------------------------------------------- @@ -3495,6 +3635,7 @@ (match_operand:SVE_SFx24 1 "aligned_register_operand" "Uw")))] "TARGET_STREAMING_SME2" "fcvtz\t%0, %1" + [(set_attr "sve_type" "sve_fp_cvt")] ) ;; ========================================================================= @@ -3523,6 +3664,7 @@ [ w , Upl , 0 ; * ] \t%0., %1/m, %2. [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_int_recip_est")] ) ;; Predicated integer unary operations with merging. @@ -3566,6 +3708,7 @@ { operands[4] = CONSTM1_RTX (mode); } + [(set_attr "sve_type" "sve_int_recip_est")] ) ;; ------------------------------------------------------------------------- @@ -3588,6 +3731,7 @@ [ w , Upl , 0 ; * ] \t%0., %1/m, %2. [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_fp_log")] ) ;; Predicated FLOGB with merging. @@ -3626,6 +3770,7 @@ { operands[4] = copy_rtx (operands[1]); } + [(set_attr "sve_type" "sve_fp_log")] ) (define_insn "*cond__strict" @@ -3645,6 +3790,7 @@ [ ?&w , Upl , w , Dz ; yes ] movprfx\t%0., %1/z, %2.\;\t%0., %1/m, %2. [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;\t%0., %1/m, %2. } + [(set_attr "sve_type" "sve_fp_log")] ) ;; ------------------------------------------------------------------------- @@ -3665,6 +3811,7 @@ UNSPEC_PMUL))] "TARGET_SVE2" "pmul\t%0., %1., %2." + [(set_attr "sve_type" "sve_int_pmul")] ) ;; Extending PMUL, with the results modeled as wider vectors. @@ -3677,6 +3824,7 @@ SVE2_PMULL))] "TARGET_SVE2" "\t%0., %1., %2." + [(set_attr "sve_type" "sve_int_pmul")] ) ;; Extending PMUL, with the results modeled as pairs of values. @@ -3690,6 +3838,7 @@ SVE2_PMULL_PAIR))] "TARGET_SVE2" "\t%0., %1., %2." + [(set_attr "sve_type" "sve_int_pmul")] ) ;; ========================================================================= @@ -3709,6 +3858,7 @@ UNSPEC_SEL))] "TARGET_STREAMING_SME2" "sel\t%0, %K3, %1, %2" + [(set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -3736,6 +3886,7 @@ (clobber (reg:CC_NZC CC_REGNUM))] "TARGET_SVE2p1_OR_SME2" "while\t{%S0., %T0.}, %x1, %x2" + [(set_attr "sve_type" "sve_pred_cnt_ctrl")] ) (define_insn "@aarch64_sve_while_c" @@ -3750,6 +3901,7 @@ (clobber (reg:CC_NZC CC_REGNUM))] "TARGET_SVE2p1_OR_SME2" "while\t%K0., %x1, %x2, vlx%3" + [(set_attr "sve_type" "sve_pred_cnt_ctrl")] ) ;; ========================================================================= @@ -3778,6 +3930,7 @@ SVE_INT_REDUCTION_128))] "TARGET_SVE2p1 && TARGET_NON_STREAMING" "\t%0., %1, %2." + [(set_attr "sve_type" "sve_int_reduc")] ) ;; ------------------------------------------------------------------------- @@ -3799,6 +3952,7 @@ SVE_FP_REDUCTION_128))] "TARGET_SVE2p1 && TARGET_NON_STREAMING" "\t%0., %1, %2." + [(set_attr "sve_type" "sve_fp_reduc")] ) ;; ========================================================================= @@ -3825,6 +3979,7 @@ [ w , Upl , 0 ; * ] revd\t%0.q, %1/m, %2.q [ ?&w , Upl , w ; yes ] movprfx\t%0, %2\;revd\t%0.q, %1/m, %2.q } + [(set_attr "sve_type" "sve_int_general")] ) (define_insn "@cond_" @@ -3841,6 +3996,7 @@ [ w , Upl , w , 0 ; * ] revd\t%0.q, %1/m, %2.q [ ?&w , Upl , w , w ; yes ] movprfx\t%0, %3\;revd\t%0.q, %1/m, %2.q } + [(set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -3861,6 +4017,7 @@ && TARGET_NON_STREAMING && IN_RANGE (INTVAL (operands[2]) * ( / 8), 0, 15)" "dupq\t%0., %1.[%2]" + [(set_attr "sve_type" "sve_int_general")] ) (define_insn "@aarch64_sve_extq" @@ -3879,7 +4036,8 @@ ? "extq\\t%0.b, %0.b, %2.b, #%3" : "movprfx\t%0, %1\;extq\\t%0.b, %0.b, %2.b, #%3"); } - [(set_attr "movprfx" "*,yes")] + [(set_attr "movprfx" "*,yes") + (set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -3900,6 +4058,7 @@ UNSPEC_TBL2))] "TARGET_SVE2" "tbl\t%0., %1, %2." + [(set_attr "sve_type" "sve_int_general")] ) ;; TBX(Q). These instructions do not take MOVPRFX. @@ -3912,6 +4071,7 @@ SVE_TBX))] "TARGET_SVE2" "\t%0., %2., %3." + [(set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -3930,6 +4090,7 @@ SVE2_x24_PERMUTE))] "TARGET_STREAMING_SME2" "\t%0, %1., %2." + [(set_attr "sve_type" "sve_int_general")] ) (define_insn "@aarch64_sve_" @@ -3940,6 +4101,7 @@ SVE2_x24_PERMUTEQ))] "TARGET_STREAMING_SME2" "\t{%S0.q - %T0.q}, %1.q, %2.q" + [(set_attr "sve_type" "sve_int_general")] ) (define_insn "@aarch64_sve_" @@ -3949,6 +4111,7 @@ SVE2_x24_PERMUTE))] "TARGET_STREAMING_SME2" "\t%0, %1" + [(set_attr "sve_type" "sve_int_general")] ) (define_insn "@aarch64_sve_" @@ -3958,6 +4121,7 @@ SVE2_x24_PERMUTEQ))] "TARGET_STREAMING_SME2" "\t{%S0.q - %V0.q}, {%S1.q - %V1.q}" + [(set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -3977,6 +4141,7 @@ SVE2_INT_BITPERM))] "TARGET_SVE2_BITPERM" "\t%0., %1., %2." + [(set_attr "sve_type" "sve_int_bit_perm")] ) ;; ========================================================================= @@ -4041,6 +4206,7 @@ UNSPEC_HISTCNT))] "TARGET_SVE2 && TARGET_NON_STREAMING" "histcnt\t%0., %1/z, %2., %3." + [(set_attr "sve_type" "sve_int_general")] ) (define_insn "@aarch64_sve2_histseg" @@ -4051,6 +4217,7 @@ UNSPEC_HISTSEG))] "TARGET_SVE2 && TARGET_NON_STREAMING" "histseg\t%0., %1., %2." + [(set_attr "sve_type" "sve_int_general")] ) ;; ------------------------------------------------------------------------- @@ -4079,6 +4246,7 @@ [ ?Upl , 0 , w, w; yes ] ^ [ Upa , Upl, w, w; no ] ^ } + [(set_attr "sve_type" "sve_int_match")] ) (define_expand "@aarch64_pred_" @@ -4161,6 +4329,7 @@ operands[6] = copy_rtx (operands[4]); operands[7] = operands[5]; } + [(set_attr "sve_type" "sve_int_match")] ) (define_insn_and_rewrite "*aarch64_pred__cc" @@ -4228,6 +4397,7 @@ operands[6] = copy_rtx (operands[4]); operands[7] = operands[5]; } + [(set_attr "sve_type" "sve_int_match")] ) ;; ------------------------------------------------------------------------- @@ -4248,6 +4418,7 @@ UNSPEC_SVE_LUTI))] "TARGET_LUT && TARGET_SVE2_OR_SME2" "luti\t%0., { %1. }, %2[%3]" + [(set_attr "sve_type" "sve_int_general")] ) (define_insn "@aarch64_sve_luti" @@ -4260,6 +4431,7 @@ UNSPEC_SVE_LUTI))] "TARGET_LUT && TARGET_SVE2_OR_SME2" "luti\t%0., %1, %2[%3]" + [(set_attr "sve_type" "sve_int_general")] ) ;; ========================================================================= diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index ca612dac600..36363e8f7c5 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -647,6 +647,26 @@ ;; patterns. (define_attr "ldpstp" "ldp,stp,none" (const_string "none")) +;; Attribute that classifies SVE instructions by their functional type. +;; This attribute is currently only used for dispatch scheduling. +(define_attr "sve_type" + "none,\ + sve_pred_logical,sve_pred_cnt_ctrl,sve_pred_cnt_scalar,sve_pred_misc,\ + sve_pred_vec,\ + sve_fp_arith,sve_fp_mul,sve_fp_assoc_add,sve_fp_cmp,sve_fp_cvt,sve_fp_log,\ + sve_fp_exp,sve_fp_div,sve_fp_sqrt,sve_fp_reduc,sve_fp_misc,\ + sve_int_general,sve_int_shift,sve_int_mul,sve_int_dot,sve_int_cmp_set,\ + sve_int_extend,sve_int_extract,sve_int_cvt,sve_int_div,sve_int_index,\ + sve_int_match,sve_int_recip_est,sve_int_reduc,sve_int_accum,\ + sve_int_pmul,sve_int_bit_perm,\ + sve_load_pred,sve_load_1reg,sve_load_2reg,sve_load_3reg,sve_load_4reg,\ + sve_gatherload_32,sve_gatherload_64,\ + sve_store_pred,sve_store_1reg,sve_store_2reg,sve_store_3reg,sve_store_4reg,\ + sve_scatterstore_32,sve_scatterstore_64,\ + sve_ffr,\ + sve_crypto_sha3" + (const_string "none")) + ;; ------------------------------------------------------------------- ;; Pipeline descriptions and scheduling ;; ------------------------------------------------------------------- diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 451b00f55af..332e7ffd2ea 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -4681,6 +4681,102 @@ (UNSPEC_SQDMULLBT "sqdmlslbt") (UNSPEC_SQDMULLT "sqdmlslt")]) +;; The value of the attribute "sve_type" associated with an unspec. +(define_int_attr sve_type_unspec [(UNSPEC_COND_FABS "fp_arith") + (UNSPEC_COND_FNEG "fp_arith") + (UNSPEC_FRECPE "fp_log") + (UNSPEC_COND_FRECPX "fp_log") + (UNSPEC_COND_FRINTA "fp_cvt") + (UNSPEC_COND_FRINTI "fp_cvt") + (UNSPEC_COND_FRINTM "fp_cvt") + (UNSPEC_COND_FRINTN "fp_cvt") + (UNSPEC_COND_FRINTP "fp_cvt") + (UNSPEC_COND_FRINTX "fp_cvt") + (UNSPEC_COND_FRINTZ "fp_cvt") + (UNSPEC_RSQRTE "fp_log") + (UNSPEC_COND_FSQRT "fp_sqrt") + (UNSPEC_FRECPS "fp_mul") + (UNSPEC_RSQRTS "fp_mul") + (UNSPEC_COND_FDIV "fp_div") + (UNSPEC_COND_FMULX "fp_mul") + (UNSPEC_COND_FAMAX "fp_arith") + (UNSPEC_COND_FAMIN "fp_arith") + (UNSPEC_COND_FADD "fp_arith") + (UNSPEC_COND_FMAX "fp_arith") + (UNSPEC_COND_FMAXNM "fp_arith") + (UNSPEC_COND_FMIN "fp_arith") + (UNSPEC_COND_FMINNM "fp_arith") + (UNSPEC_COND_FMUL "fp_mul") + (UNSPEC_COND_FSUB "fp_arith") + (UNSPEC_FMLALB "fp_mul") + (UNSPEC_FMLALT "fp_mul") + (UNSPEC_FMLSLB "fp_mul") + (UNSPEC_FMLSLT "fp_mul") + (UNSPEC_FMAX "fp_arith") + (UNSPEC_FMAXNM "fp_arith") + (UNSPEC_FMIN "fp_arith") + (UNSPEC_FMINNM "fp_arith") + (UNSPEC_FDOT "fp_mul") + (UNSPEC_COND_SMAX "fp_arith") + (UNSPEC_COND_SMIN "fp_arith") + (UNSPEC_ADCLB "int_general") + (UNSPEC_ADCLT "int_general") + (UNSPEC_EORBT "int_general") + (UNSPEC_EORTB "int_general") + (UNSPEC_SBCLB "int_general") + (UNSPEC_SBCLT "int_general") + (UNSPEC_SQRDMLAH "int_mul") + (UNSPEC_SQRDMLSH "int_mul") + (UNSPEC_SABDLB "int_general") + (UNSPEC_SABDLT "int_general") + (UNSPEC_SADDLB "int_general") + (UNSPEC_SADDLBT "int_general") + (UNSPEC_SADDLT "int_general") + (UNSPEC_SMULLB "int_mul") + (UNSPEC_SMULLT "int_mul") + (UNSPEC_SQDMULLB "int_mul") + (UNSPEC_SQDMULLBT "int_mul") + (UNSPEC_SQDMULLT "int_mul") + (UNSPEC_SSUBLB "int_general") + (UNSPEC_SSUBLBT "int_general") + (UNSPEC_SSUBLT "int_general") + (UNSPEC_SSUBLTB "int_general") + (UNSPEC_UABDLB "int_general") + (UNSPEC_UABDLT "int_general") + (UNSPEC_UADDLB "int_general") + (UNSPEC_UADDLT "int_general") + (UNSPEC_UMULLB "int_mul") + (UNSPEC_UMULLT "int_mul") + (UNSPEC_USUBLB "int_general") + (UNSPEC_USUBLT "int_general") + (UNSPEC_SQDMULH "int_mul") + (UNSPEC_URSHL "int_shift") + (UNSPEC_SRSHL "int_shift")]) + +;; The value of the attribute "sve_type" associated with an int code. +(define_code_attr sve_type_int [(mult "int_mul") + (smax "int_general") + (smin "int_general") + (umax "int_general") + (umin "int_general") + (plus "int_general") + (minus "int_general") + (ashift "int_shift") + (ashiftrt "int_shift") + (lshiftrt "int_shift") + (and "int_general") + (ior "int_general") + (xor "int_general") + (ss_plus "int_general") + (us_plus "int_general") + (ss_minus "int_general") + (us_minus "int_general")]) + +;; The value of the attribute "sve_type" associated with an fp code. +(define_code_attr sve_type_fp [(mult "fp_mul") + (plus "fp_arith") + (minus "fp_arith")]) + (define_int_attr sve_fp_op [(UNSPEC_BFDOT "bfdot") (UNSPEC_BFMLALB "bfmlalb") (UNSPEC_BFMLALT "bfmlalt")