From: Greg Kroah-Hartman Date: Wed, 21 Feb 2024 12:41:06 +0000 (+0100) Subject: drop powerpc patch from older queues X-Git-Tag: v4.19.307~10 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=cc49a3ef522219ddd9c5f0c8c99b8dd5a635f987;p=thirdparty%2Fkernel%2Fstable-queue.git drop powerpc patch from older queues --- diff --git a/queue-5.10/powerpc-6xx-set-high-bat-enable-flag-on-g2_le-cores.patch b/queue-5.10/powerpc-6xx-set-high-bat-enable-flag-on-g2_le-cores.patch deleted file mode 100644 index 9ff15c66058..00000000000 --- a/queue-5.10/powerpc-6xx-set-high-bat-enable-flag-on-g2_le-cores.patch +++ /dev/null @@ -1,85 +0,0 @@ -From e786cd77f90d16843c3c0634de6f13624af55d54 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Wed, 24 Jan 2024 11:38:38 +0100 -Subject: powerpc/6xx: set High BAT Enable flag on G2_LE cores - -From: Matthias Schiffer - -[ Upstream commit a038a3ff8c6582404834852c043dadc73a5b68b4 ] - -MMU_FTR_USE_HIGH_BATS is set for G2_LE cores and derivatives like e300cX, -but the high BATs need to be enabled in HID2 to work. Add register -definitions and add the needed setup to __setup_cpu_603. - -This fixes boot on CPUs like the MPC5200B with STRICT_KERNEL_RWX enabled -on systems where the flag has not been set by the bootloader already. - -Fixes: e4d6654ebe6e ("powerpc/mm/32s: rework mmu_mapin_ram()") -Signed-off-by: Matthias Schiffer -Reviewed-by: Christophe Leroy -Signed-off-by: Michael Ellerman -Link: https://msgid.link/20240124103838.43675-1-matthias.schiffer@ew.tq-group.com -Signed-off-by: Sasha Levin ---- - arch/powerpc/include/asm/reg.h | 2 ++ - arch/powerpc/kernel/cpu_setup_6xx.S | 20 +++++++++++++++++++- - 2 files changed, 21 insertions(+), 1 deletion(-) - -diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h -index 6afb14b6bbc2..01006de8a900 100644 ---- a/arch/powerpc/include/asm/reg.h -+++ b/arch/powerpc/include/asm/reg.h -@@ -612,6 +612,8 @@ - #endif - #define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */ - #define SPRN_HID2_GEKKO 0x398 /* Gekko HID2 Register */ -+#define SPRN_HID2_G2_LE 0x3F3 /* G2_LE HID2 Register */ -+#define HID2_G2_LE_HBE (1<<18) /* High BAT Enable (G2_LE) */ - #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ - #define SPRN_IABR2 0x3FA /* 83xx */ - #define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */ -diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S b/arch/powerpc/kernel/cpu_setup_6xx.S -index f8b5ff64b604..6cbad50c71f6 100644 ---- a/arch/powerpc/kernel/cpu_setup_6xx.S -+++ b/arch/powerpc/kernel/cpu_setup_6xx.S -@@ -24,6 +24,15 @@ BEGIN_FTR_SECTION - bl __init_fpu_registers - END_FTR_SECTION_IFCLR(CPU_FTR_FPU_UNAVAILABLE) - bl setup_common_caches -+ -+ /* -+ * This assumes that all cores using __setup_cpu_603 with -+ * MMU_FTR_USE_HIGH_BATS are G2_LE compatible -+ */ -+BEGIN_MMU_FTR_SECTION -+ bl setup_g2_le_hid2 -+END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS) -+ - mtlr r5 - blr - _GLOBAL(__setup_cpu_604) -@@ -111,6 +120,16 @@ setup_604_hid0: - isync - blr - -+/* Enable high BATs for G2_LE and derivatives like e300cX */ -+SYM_FUNC_START_LOCAL(setup_g2_le_hid2) -+ mfspr r11,SPRN_HID2_G2_LE -+ oris r11,r11,HID2_G2_LE_HBE@h -+ mtspr SPRN_HID2_G2_LE,r11 -+ sync -+ isync -+ blr -+SYM_FUNC_END(setup_g2_le_hid2) -+ - /* 7400 <= rev 2.7 and 7410 rev = 1.0 suffer from some - * erratas we work around here. - * Moto MPC710CE.pdf describes them, those are errata -@@ -485,4 +504,3 @@ _GLOBAL(__restore_cpu_setup) - mtcr r7 - blr - _ASM_NOKPROBE_SYMBOL(__restore_cpu_setup) -- --- -2.43.0 - diff --git a/queue-5.10/series b/queue-5.10/series index 0490d9e779f..f84227d13d3 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -304,7 +304,6 @@ usb-ucsi_acpi-fix-command-completion-handling.patch usb-hub-check-for-alternate-port-before-enabling-a_alt_hnp_support.patch usb-f_mass_storage-forbid-async-queue-when-shutdown-happen.patch media-ir_toy-fix-a-memleak-in-irtoy_tx.patch -powerpc-6xx-set-high-bat-enable-flag-on-g2_le-cores.patch powerpc-kasan-fix-addr-error-caused-by-page-alignmen.patch i2c-i801-remove-i801_set_block_buffer_mode.patch i2c-i801-fix-block-process-call-transactions.patch diff --git a/queue-5.15/powerpc-6xx-set-high-bat-enable-flag-on-g2_le-cores.patch b/queue-5.15/powerpc-6xx-set-high-bat-enable-flag-on-g2_le-cores.patch deleted file mode 100644 index 2b90ed23e8f..00000000000 --- a/queue-5.15/powerpc-6xx-set-high-bat-enable-flag-on-g2_le-cores.patch +++ /dev/null @@ -1,85 +0,0 @@ -From f8b3cbb2b94fee115afddb75897d25edc8bd6c30 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Wed, 24 Jan 2024 11:38:38 +0100 -Subject: powerpc/6xx: set High BAT Enable flag on G2_LE cores - -From: Matthias Schiffer - -[ Upstream commit a038a3ff8c6582404834852c043dadc73a5b68b4 ] - -MMU_FTR_USE_HIGH_BATS is set for G2_LE cores and derivatives like e300cX, -but the high BATs need to be enabled in HID2 to work. Add register -definitions and add the needed setup to __setup_cpu_603. - -This fixes boot on CPUs like the MPC5200B with STRICT_KERNEL_RWX enabled -on systems where the flag has not been set by the bootloader already. - -Fixes: e4d6654ebe6e ("powerpc/mm/32s: rework mmu_mapin_ram()") -Signed-off-by: Matthias Schiffer -Reviewed-by: Christophe Leroy -Signed-off-by: Michael Ellerman -Link: https://msgid.link/20240124103838.43675-1-matthias.schiffer@ew.tq-group.com -Signed-off-by: Sasha Levin ---- - arch/powerpc/include/asm/reg.h | 2 ++ - arch/powerpc/kernel/cpu_setup_6xx.S | 20 +++++++++++++++++++- - 2 files changed, 21 insertions(+), 1 deletion(-) - -diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h -index e9d27265253b..6a982aee50c8 100644 ---- a/arch/powerpc/include/asm/reg.h -+++ b/arch/powerpc/include/asm/reg.h -@@ -611,6 +611,8 @@ - #endif - #define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */ - #define SPRN_HID2_GEKKO 0x398 /* Gekko HID2 Register */ -+#define SPRN_HID2_G2_LE 0x3F3 /* G2_LE HID2 Register */ -+#define HID2_G2_LE_HBE (1<<18) /* High BAT Enable (G2_LE) */ - #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ - #define SPRN_IABR2 0x3FA /* 83xx */ - #define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */ -diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S b/arch/powerpc/kernel/cpu_setup_6xx.S -index f8b5ff64b604..6cbad50c71f6 100644 ---- a/arch/powerpc/kernel/cpu_setup_6xx.S -+++ b/arch/powerpc/kernel/cpu_setup_6xx.S -@@ -24,6 +24,15 @@ BEGIN_FTR_SECTION - bl __init_fpu_registers - END_FTR_SECTION_IFCLR(CPU_FTR_FPU_UNAVAILABLE) - bl setup_common_caches -+ -+ /* -+ * This assumes that all cores using __setup_cpu_603 with -+ * MMU_FTR_USE_HIGH_BATS are G2_LE compatible -+ */ -+BEGIN_MMU_FTR_SECTION -+ bl setup_g2_le_hid2 -+END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS) -+ - mtlr r5 - blr - _GLOBAL(__setup_cpu_604) -@@ -111,6 +120,16 @@ setup_604_hid0: - isync - blr - -+/* Enable high BATs for G2_LE and derivatives like e300cX */ -+SYM_FUNC_START_LOCAL(setup_g2_le_hid2) -+ mfspr r11,SPRN_HID2_G2_LE -+ oris r11,r11,HID2_G2_LE_HBE@h -+ mtspr SPRN_HID2_G2_LE,r11 -+ sync -+ isync -+ blr -+SYM_FUNC_END(setup_g2_le_hid2) -+ - /* 7400 <= rev 2.7 and 7410 rev = 1.0 suffer from some - * erratas we work around here. - * Moto MPC710CE.pdf describes them, those are errata -@@ -485,4 +504,3 @@ _GLOBAL(__restore_cpu_setup) - mtcr r7 - blr - _ASM_NOKPROBE_SYMBOL(__restore_cpu_setup) -- --- -2.43.0 - diff --git a/queue-5.15/series b/queue-5.15/series index c28849e9ec0..de09b5fb434 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -368,7 +368,6 @@ usb-hub-check-for-alternate-port-before-enabling-a_alt_hnp_support.patch usb-f_mass_storage-forbid-async-queue-when-shutdown-happen.patch usb-dwc3-gadget-fix-null-pointer-dereference-in-dwc3_gadget_suspend.patch media-ir_toy-fix-a-memleak-in-irtoy_tx.patch -powerpc-6xx-set-high-bat-enable-flag-on-g2_le-cores.patch powerpc-kasan-fix-addr-error-caused-by-page-alignmen.patch i2c-i801-remove-i801_set_block_buffer_mode.patch i2c-i801-fix-block-process-call-transactions.patch diff --git a/queue-6.1/powerpc-6xx-set-high-bat-enable-flag-on-g2_le-cores.patch b/queue-6.1/powerpc-6xx-set-high-bat-enable-flag-on-g2_le-cores.patch deleted file mode 100644 index 3421154a01b..00000000000 --- a/queue-6.1/powerpc-6xx-set-high-bat-enable-flag-on-g2_le-cores.patch +++ /dev/null @@ -1,85 +0,0 @@ -From f763e638b2d4bb0e47f9164068ccf0e869c283d6 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Wed, 24 Jan 2024 11:38:38 +0100 -Subject: powerpc/6xx: set High BAT Enable flag on G2_LE cores - -From: Matthias Schiffer - -[ Upstream commit a038a3ff8c6582404834852c043dadc73a5b68b4 ] - -MMU_FTR_USE_HIGH_BATS is set for G2_LE cores and derivatives like e300cX, -but the high BATs need to be enabled in HID2 to work. Add register -definitions and add the needed setup to __setup_cpu_603. - -This fixes boot on CPUs like the MPC5200B with STRICT_KERNEL_RWX enabled -on systems where the flag has not been set by the bootloader already. - -Fixes: e4d6654ebe6e ("powerpc/mm/32s: rework mmu_mapin_ram()") -Signed-off-by: Matthias Schiffer -Reviewed-by: Christophe Leroy -Signed-off-by: Michael Ellerman -Link: https://msgid.link/20240124103838.43675-1-matthias.schiffer@ew.tq-group.com -Signed-off-by: Sasha Levin ---- - arch/powerpc/include/asm/reg.h | 2 ++ - arch/powerpc/kernel/cpu_setup_6xx.S | 20 +++++++++++++++++++- - 2 files changed, 21 insertions(+), 1 deletion(-) - -diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h -index 8fda87af2fa5..6c0ab745f0c8 100644 ---- a/arch/powerpc/include/asm/reg.h -+++ b/arch/powerpc/include/asm/reg.h -@@ -608,6 +608,8 @@ - #endif - #define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */ - #define SPRN_HID2_GEKKO 0x398 /* Gekko HID2 Register */ -+#define SPRN_HID2_G2_LE 0x3F3 /* G2_LE HID2 Register */ -+#define HID2_G2_LE_HBE (1<<18) /* High BAT Enable (G2_LE) */ - #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ - #define SPRN_IABR2 0x3FA /* 83xx */ - #define SPRN_IBCR 0x135 /* 83xx Insn Breakpoint Control Reg */ -diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S b/arch/powerpc/kernel/cpu_setup_6xx.S -index f8b5ff64b604..6cbad50c71f6 100644 ---- a/arch/powerpc/kernel/cpu_setup_6xx.S -+++ b/arch/powerpc/kernel/cpu_setup_6xx.S -@@ -24,6 +24,15 @@ BEGIN_FTR_SECTION - bl __init_fpu_registers - END_FTR_SECTION_IFCLR(CPU_FTR_FPU_UNAVAILABLE) - bl setup_common_caches -+ -+ /* -+ * This assumes that all cores using __setup_cpu_603 with -+ * MMU_FTR_USE_HIGH_BATS are G2_LE compatible -+ */ -+BEGIN_MMU_FTR_SECTION -+ bl setup_g2_le_hid2 -+END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS) -+ - mtlr r5 - blr - _GLOBAL(__setup_cpu_604) -@@ -111,6 +120,16 @@ setup_604_hid0: - isync - blr - -+/* Enable high BATs for G2_LE and derivatives like e300cX */ -+SYM_FUNC_START_LOCAL(setup_g2_le_hid2) -+ mfspr r11,SPRN_HID2_G2_LE -+ oris r11,r11,HID2_G2_LE_HBE@h -+ mtspr SPRN_HID2_G2_LE,r11 -+ sync -+ isync -+ blr -+SYM_FUNC_END(setup_g2_le_hid2) -+ - /* 7400 <= rev 2.7 and 7410 rev = 1.0 suffer from some - * erratas we work around here. - * Moto MPC710CE.pdf describes them, those are errata -@@ -485,4 +504,3 @@ _GLOBAL(__restore_cpu_setup) - mtcr r7 - blr - _ASM_NOKPROBE_SYMBOL(__restore_cpu_setup) -- --- -2.43.0 - diff --git a/queue-6.1/series b/queue-6.1/series index 042c93056c1..f304d29c031 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -53,7 +53,6 @@ usb-dwc3-gadget-fix-null-pointer-dereference-in-dwc3_gadget_suspend.patch interconnect-qcom-sc8180x-mark-co0-bcm-keepalive.patch media-ir_toy-fix-a-memleak-in-irtoy_tx.patch driver-core-fw_devlink-improve-detection-of-overlapp.patch -powerpc-6xx-set-high-bat-enable-flag-on-g2_le-cores.patch powerpc-kasan-fix-addr-error-caused-by-page-alignmen.patch cifs-fix-underflow-in-parse_server_interfaces.patch i2c-qcom-geni-correct-i2c-tre-sequence.patch