From: Greg Kroah-Hartman Date: Wed, 2 Nov 2022 01:28:30 +0000 (+0100) Subject: 5.10-stable patches X-Git-Tag: v4.9.332~12 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=cc6b893b86e1abaa92d398ba667b6f0eb7888050;p=thirdparty%2Fkernel%2Fstable-queue.git 5.10-stable patches added patches: arm64-kexec-test-page-size-support-with-new-tgran-range-values.patch arm64-mm-fix-__enable_mmu-for-new-tgran-range-values.patch --- diff --git a/queue-5.10/arm64-kexec-test-page-size-support-with-new-tgran-range-values.patch b/queue-5.10/arm64-kexec-test-page-size-support-with-new-tgran-range-values.patch new file mode 100644 index 00000000000..6c3a9485d06 --- /dev/null +++ b/queue-5.10/arm64-kexec-test-page-size-support-with-new-tgran-range-values.patch @@ -0,0 +1,109 @@ +From 79d82cbcbb3d2a56c009ad6a6df92c5dee061dad Mon Sep 17 00:00:00 2001 +From: Anshuman Khandual +Date: Wed, 14 Jul 2021 10:16:15 +0530 +Subject: arm64/kexec: Test page size support with new TGRAN range values + +From: Anshuman Khandual + +commit 79d82cbcbb3d2a56c009ad6a6df92c5dee061dad upstream. + +The commit 26f55386f964 ("arm64/mm: Fix __enable_mmu() for new TGRAN range +values") had already switched into testing ID_AA64MMFR0_TGRAN range values. +This just changes system_supports_[4|16|64]kb_granule() helpers to perform +similar range tests as well. While here, it standardizes page size specific +supported min and max TGRAN values. + +Cc: Will Deacon +Cc: James Morse +Cc: linux-arm-kernel@lists.infradead.org +Cc: linux-kernel@vger.kernel.org +Signed-off-by: Anshuman Khandual +Link: https://lore.kernel.org/r/1626237975-1909-1-git-send-email-anshuman.khandual@arm.com +Signed-off-by: Catalin Marinas +Signed-off-by: Zenghui Yu +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/include/asm/cpufeature.h | 9 ++++++--- + arch/arm64/include/asm/sysreg.h | 28 ++++++++++++++++------------ + 2 files changed, 22 insertions(+), 15 deletions(-) + +--- a/arch/arm64/include/asm/cpufeature.h ++++ b/arch/arm64/include/asm/cpufeature.h +@@ -648,7 +648,8 @@ static inline bool system_supports_4kb_g + val = cpuid_feature_extract_unsigned_field(mmfr0, + ID_AA64MMFR0_TGRAN4_SHIFT); + +- return val == ID_AA64MMFR0_TGRAN4_SUPPORTED; ++ return (val >= ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN) && ++ (val <= ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX); + } + + static inline bool system_supports_64kb_granule(void) +@@ -660,7 +661,8 @@ static inline bool system_supports_64kb_ + val = cpuid_feature_extract_unsigned_field(mmfr0, + ID_AA64MMFR0_TGRAN64_SHIFT); + +- return val == ID_AA64MMFR0_TGRAN64_SUPPORTED; ++ return (val >= ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN) && ++ (val <= ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX); + } + + static inline bool system_supports_16kb_granule(void) +@@ -672,7 +674,8 @@ static inline bool system_supports_16kb_ + val = cpuid_feature_extract_unsigned_field(mmfr0, + ID_AA64MMFR0_TGRAN16_SHIFT); + +- return val == ID_AA64MMFR0_TGRAN16_SUPPORTED; ++ return (val >= ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN) && ++ (val <= ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX); + } + + static inline bool system_supports_mixed_endian_el0(void) +--- a/arch/arm64/include/asm/sysreg.h ++++ b/arch/arm64/include/asm/sysreg.h +@@ -786,12 +786,16 @@ + #define ID_AA64MMFR0_ASID_SHIFT 4 + #define ID_AA64MMFR0_PARANGE_SHIFT 0 + +-#define ID_AA64MMFR0_TGRAN4_NI 0xf +-#define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 +-#define ID_AA64MMFR0_TGRAN64_NI 0xf +-#define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 +-#define ID_AA64MMFR0_TGRAN16_NI 0x0 +-#define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 ++#define ID_AA64MMFR0_TGRAN4_NI 0xf ++#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN 0x0 ++#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX 0x7 ++#define ID_AA64MMFR0_TGRAN64_NI 0xf ++#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN 0x0 ++#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX 0x7 ++#define ID_AA64MMFR0_TGRAN16_NI 0x0 ++#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN 0x1 ++#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX 0xf ++ + #define ID_AA64MMFR0_PARANGE_48 0x5 + #define ID_AA64MMFR0_PARANGE_52 0x6 + +@@ -961,16 +965,16 @@ + + #if defined(CONFIG_ARM64_4K_PAGES) + #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT +-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN4_SUPPORTED +-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX 0x7 ++#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN ++#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX + #elif defined(CONFIG_ARM64_16K_PAGES) + #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT +-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN16_SUPPORTED +-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX 0xF ++#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN ++#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX + #elif defined(CONFIG_ARM64_64K_PAGES) + #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT +-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN64_SUPPORTED +-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX 0x7 ++#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN ++#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX + #endif + + #define MVFR2_FPMISC_SHIFT 4 diff --git a/queue-5.10/arm64-mm-fix-__enable_mmu-for-new-tgran-range-values.patch b/queue-5.10/arm64-mm-fix-__enable_mmu-for-new-tgran-range-values.patch new file mode 100644 index 00000000000..cd7d98a3181 --- /dev/null +++ b/queue-5.10/arm64-mm-fix-__enable_mmu-for-new-tgran-range-values.patch @@ -0,0 +1,131 @@ +From 26f55386f964cefa92ab7ccbed68f1a313074215 Mon Sep 17 00:00:00 2001 +From: James Morse +Date: Wed, 10 Mar 2021 11:23:10 +0530 +Subject: arm64/mm: Fix __enable_mmu() for new TGRAN range values + +From: James Morse + +commit 26f55386f964cefa92ab7ccbed68f1a313074215 upstream. + +As per ARM ARM DDI 0487G.a, when FEAT_LPA2 is implemented, ID_AA64MMFR0_EL1 +might contain a range of values to describe supported translation granules +(4K and 16K pages sizes in particular) instead of just enabled or disabled +values. This changes __enable_mmu() function to handle complete acceptable +range of values (depending on whether the field is signed or unsigned) now +represented with ID_AA64MMFR0_TGRAN_SUPPORTED_[MIN..MAX] pair. While here, +also fix similar situations in EFI stub and KVM as well. + +Cc: Catalin Marinas +Cc: Will Deacon +Cc: Marc Zyngier +Cc: James Morse +Cc: Suzuki K Poulose +Cc: Ard Biesheuvel +Cc: Mark Rutland +Cc: linux-arm-kernel@lists.infradead.org +Cc: kvmarm@lists.cs.columbia.edu +Cc: linux-efi@vger.kernel.org +Cc: linux-kernel@vger.kernel.org +Acked-by: Marc Zyngier +Signed-off-by: James Morse +Signed-off-by: Anshuman Khandual +Link: https://lore.kernel.org/r/1615355590-21102-1-git-send-email-anshuman.khandual@arm.com +Signed-off-by: Will Deacon +Signed-off-by: Zenghui Yu +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/include/asm/sysreg.h | 20 ++++++++++++++------ + arch/arm64/kernel/head.S | 6 ++++-- + arch/arm64/kvm/reset.c | 10 ++++++---- + drivers/firmware/efi/libstub/arm64-stub.c | 2 +- + 4 files changed, 25 insertions(+), 13 deletions(-) + +--- a/arch/arm64/include/asm/sysreg.h ++++ b/arch/arm64/include/asm/sysreg.h +@@ -795,6 +795,11 @@ + #define ID_AA64MMFR0_PARANGE_48 0x5 + #define ID_AA64MMFR0_PARANGE_52 0x6 + ++#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT 0x0 ++#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE 0x1 ++#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN 0x2 ++#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX 0x7 ++ + #ifdef CONFIG_ARM64_PA_BITS_52 + #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_52 + #else +@@ -955,14 +960,17 @@ + #define ID_PFR1_PROGMOD_SHIFT 0 + + #if defined(CONFIG_ARM64_4K_PAGES) +-#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT +-#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED ++#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT ++#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN4_SUPPORTED ++#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX 0x7 + #elif defined(CONFIG_ARM64_16K_PAGES) +-#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT +-#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED ++#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT ++#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN16_SUPPORTED ++#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX 0xF + #elif defined(CONFIG_ARM64_64K_PAGES) +-#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT +-#define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED ++#define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT ++#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_TGRAN64_SUPPORTED ++#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX 0x7 + #endif + + #define MVFR2_FPMISC_SHIFT 4 +--- a/arch/arm64/kernel/head.S ++++ b/arch/arm64/kernel/head.S +@@ -797,8 +797,10 @@ SYM_FUNC_END(__secondary_too_slow) + SYM_FUNC_START(__enable_mmu) + mrs x2, ID_AA64MMFR0_EL1 + ubfx x2, x2, #ID_AA64MMFR0_TGRAN_SHIFT, 4 +- cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED +- b.ne __no_granule_support ++ cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED_MIN ++ b.lt __no_granule_support ++ cmp x2, #ID_AA64MMFR0_TGRAN_SUPPORTED_MAX ++ b.gt __no_granule_support + update_early_cpu_boot_status 0, x2, x3 + adrp x2, idmap_pg_dir + phys_to_ttbr x1, x1 +--- a/arch/arm64/kvm/reset.c ++++ b/arch/arm64/kvm/reset.c +@@ -397,16 +397,18 @@ int kvm_set_ipa_limit(void) + } + + switch (cpuid_feature_extract_unsigned_field(mmfr0, tgran_2)) { +- default: +- case 1: ++ case ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE: + kvm_err("PAGE_SIZE not supported at Stage-2, giving up\n"); + return -EINVAL; +- case 0: ++ case ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT: + kvm_debug("PAGE_SIZE supported at Stage-2 (default)\n"); + break; +- case 2: ++ case ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN ... ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX: + kvm_debug("PAGE_SIZE supported at Stage-2 (advertised)\n"); + break; ++ default: ++ kvm_err("Unsupported value for TGRAN_2, giving up\n"); ++ return -EINVAL; + } + + kvm_ipa_limit = id_aa64mmfr0_parange_to_phys_shift(parange); +--- a/drivers/firmware/efi/libstub/arm64-stub.c ++++ b/drivers/firmware/efi/libstub/arm64-stub.c +@@ -24,7 +24,7 @@ efi_status_t check_platform_features(voi + return EFI_SUCCESS; + + tg = (read_cpuid(ID_AA64MMFR0_EL1) >> ID_AA64MMFR0_TGRAN_SHIFT) & 0xf; +- if (tg != ID_AA64MMFR0_TGRAN_SUPPORTED) { ++ if (tg < ID_AA64MMFR0_TGRAN_SUPPORTED_MIN || tg > ID_AA64MMFR0_TGRAN_SUPPORTED_MAX) { + if (IS_ENABLED(CONFIG_ARM64_64K_PAGES)) + efi_err("This 64 KB granular kernel is not supported by your CPU\n"); + else diff --git a/queue-5.10/series b/queue-5.10/series index bc5f68f603c..4e04c224c4f 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -86,3 +86,5 @@ net-mlx5-fix-crash-during-sync-firmware-reset.patch net-enetc-survive-memory-pressure-without-crashing.patch arm64-add-ampere1-to-the-spectre-bhb-affected-list.patch scsi-sd-revert-scsi-sd-remove-a-local-variable.patch +arm64-mm-fix-__enable_mmu-for-new-tgran-range-values.patch +arm64-kexec-test-page-size-support-with-new-tgran-range-values.patch